JPH0497416A - Control system for receiving buffer - Google Patents

Abstract

PURPOSE:To improve the operation and performance of the whole device by providing this control system with a timer processing means, a releasing means and a data receiving means. CONSTITUTION:Data 2 from a host computer are inputted to a receiving buffer 4 by a CPU 7 started by an interruption signal Int1 generated from a timer processing part 3 based upon a data strobe signal inputted almost simultaneously with the data 2 through the data receiving part 3. Then, the CPU 7 checks the receivable capacity of a buffer memory receiving data out of the buffers 4, and when the switching of the buffer memory is necessary, the buffer memory is switched and an idle buffer memory is allowed to receive data. After the lapse of a previously set time from the reception of the end of a data strobe signal, the timer processing part 6 sends an interruption signal Int2 to the CPU 7, which receives the signal Int2 and starts the release processing part 8. Consequently, useless time generated in the device can be reduced, receiving performance can be improved as compared with a convensional case and the performance of the device itself can also be improved as compared with the conventional case.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for controlling a reception buffer consisting of a plurality of buffer memories for storing data to be printed out from a host computer.

[Conventional technology]

Conventionally, a control method for this type of reception buffer is a control method in which the reception buffer is switched between reception and buffer at the following three timings, and the reception buffer containing the received data is released to the analysis unit. It became.

(1) When the receive buffer becomes full of received data.

(2) When a special factor such as a change in communication mode occurs.

(3) When the firmware itself monitors the reception buffer at preset intervals using an internally generated timer and there is a reception buffer that has already received data.

[Invention or problem to be solved]

In the conventional reception buffer control method described above, the third
The need for the reception buffer switching timing mentioned in the above section arises from the meaning of searching for received data when the received data does not fill the capacity of one reception buffer.

However, in the conventional reception buffer control method, the firmware itself monitors the reception buffer for a certain period of time, which inevitably reduces the time for performing other processes, which greatly affects the operation and performance of the entire device. Also, if the monitoring time is too short, the amount of processing required to switch the receive buffer will be greater than the amount of data being received, and the time required for that overhead will be wasted; if the monitoring time is too long, the received data will be The reaction of recognizing it is sudden. Even if the optimum time is set again, it will be averaged over various data lengths, so there will always be waste or a slow response.

[Means to solve the problem]

The control method of the reception buffer of the present invention includes receiving a data strobe signal from a host computer as an internal counter start, clear signal, and internal start-up signal, and after a preset period, transmits the first and second data strobe signals to the control unit. a timer processing means that outputs an interrupt signal of a release means for making settings so that one of the reception buffers in the host computer can be used; and a release means for reading data from the host computer and reading the data from the host computer by the second interrupt 5 signal to the control unit corresponding to the data strobe signal. and data receiving means for storing data in a buffer.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing a time chart of generation of an interrupt signal from a data strobe signal to the control unit in this embodiment, and FIG. 3 is a diagram showing this embodiment. 3 is a flowchart showing an example of processing of a control unit in FIG.

In FIG. 1, this embodiment includes an interface unit 1 that interfaces with a host computer (not shown), a data receiving unit 3 that receives data from the host computer via the interface unit 1, and an interface unit 1.
a timer processing unit 6 that generates an interrupt signal at a predetermined timing from a data strobe signal from the host computer to the control unit 7 via the host computer; and a reception buffer 4 that includes a plurality of buffer memories that accumulate received data.
, a release processing unit 8 that performs release processing of the reception buffer 4, a data analysis unit that analyzes data from the reception buffer 4, and a control unit (hereinafter referred to as CP) that controls the entire embodiment.
(denoted as U) 7.

Next, the operation of this embodiment will be explained using FIG. 1, FIG. 2, and FIG. 3.

Data 2 from the host computer is sent to the CPU 7 activated by an interrupt signal (Intl>) generated in the timer processing section 6 by a data strobe signal inputted at almost the same time.
The data is read into the reception buffer 4 via the data reception section 3 (S20).

Next, the CPU 7 checks the receivable capacity of the buffer memory receiving the data in the reception buffer 4 (S2
1). If it is necessary to switch the buffer memory (S22), data is received, the buffer memory is switched, and an empty buffer memory receives the data (323>).

The CPU 7 activates the release processing unit 8 for the switched buffer memory, and the release processing unit 8 performs release processing (S24).

As shown in FIG. 2, at a preset time while receiving the final cheetah strobe signal, the timer processing section 6
An interrupt signal (Int2) is sent to 7. Interrupt signal (In
t2), the CPU 7 activates the release processing section 8, and the release processing section 8 controls the buffer memory that has received the data in the reception buffer 4 to be separated from the data reception section 3 and to be read by the data analysis section 9. .

〔Effect of the invention〕

As explained above, the present invention does not have the firmware perform the operation of switching the reception buffer at a preset period of time after receiving the last data from the host computer, as in the conventional case, but uses a timer processing means and a release means. By doing this, you can reduce wasted time inside the device, improve reception performance compared to before,
This also has the effect of improving the performance of the device compared to conventional methods.

Oribe.

Claims (1)

[Claims] a timer processing means that receives a data strobe signal from the host computer as an internal counter start and clear signal and for starting the internal unit, and outputs first and second interrupt signals to the control unit after a preset period; Then, it is activated by the first interrupt signal, releases the currently used receive buffer among the multiple receive buffers to the data analysis unit, and sets it so that one of the free receive buffers can be used. and data receiving means that is activated by the second interrupt signal to the control unit corresponding to the data strobe signal to read data from the host computer and store it in the reception buffer. Features a receive buffer control method.