JP2002351816A - Data transfer method trough bus and bus master control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer method and a bus master control unit having a common bus and enabling to improve data transfer efficiency in both devices. SOLUTION: This is a data transfer method via a bus, and constituted of a stage in which a first device occupies the above bus as a bus master, a stage in which a prescribed number of data are transferred out of the data to be transferred under the state that the above first device occupies the above data, a stage in which the above first device determines whether the above bus to be released or not in accordance with presence of a request from a second device after the end of transfer of prescribed number of above data, and a stage in which the above first device releases the above bus if the above first bus is determined to release the above buss.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data transfer method via a bus in an information processing apparatus and a bus master control device.

[0002]

2. Description of the Related Art A DMA (Direct Memory Access) controller transfers data between external devices such as a memory and an I / O (input / output) device connected to a common bus at a high speed without using a CPU. It is a control device used to execute.

FIGS. 5A to 5D show a conventional DMA.
1 conceptually shows a data transfer method using a controller.
One box indicates one data transfer (for example, one word data transfer in one cycle period), and the data transfer is performed in order from left to right. The bus masters for each data transfer are shown in boxes. What is a bus master?
A device that occupies a bus in data transfer and controls data transfer, and corresponds to a CPU, a DMA controller, and the like. In FIGS. 5A to 5D, "DMA"
Indicates that the DMA controller occupies the bus as a bus master, and "other" indicates that the DMA controller is occupying the bus.
This indicates that a bus other than the controller (for example, CPU) occupies the bus as a bus master.

FIG. 5A shows data transfer by the "burst transfer method". When the DMA transfer is activated,
The DMA controller occupies the bus until the end of the DMA transfer. Therefore, when another device such as a CPU performs data transfer with the memory via the bus, if another device is performing burst transfer, the other device must wait until the DMA transfer is completed. In order to prevent other devices from being kept on standby for a long time during burst transfer, data transfer methods shown in FIGS. 5B, 5C and 5D have been proposed.

FIG. 5B shows a "single word transfer method" in which a DMA controller and another device are alternately and forcibly switched as a bus master occupying the bus every time one word data is transferred.
Shows the data transfer by. FIG. 5C shows the data transfer by the "cycle steal transfer method" in which the DMA controller occupies the bus as the bus master and executes the DMA transfer only when no other device uses the bus as the bus master. FIG. 5D shows data transfer by the “timer interrupt transfer method” in which each device alternately occupies the bus by interrupting for a predetermined time by a timer. In the timer interrupt transfer method, DM
The DMA controller is forcibly interrupted the DMA transfer by an interrupt after a predetermined time from the start of the A transfer, and another device occupies the bus as a bus master. Further, another device is forcibly suspended from occupying the bus by an interrupt after a predetermined time, and the DMA controller resumes the DMA transfer by occupying the bus again.

[0006]

In a data transfer, for example, a DMA transfer in a system in which a plurality of devices that can be bus masters share a bus, a DMA is used.
There is a need to increase the transfer efficiency of both the controller and other devices.

However, in the above-mentioned "one-word transfer method", since DMA transfer cannot be performed continuously, especially the DRA
The memory cannot be accessed using a high-speed transfer mode such as the M page mode. Therefore, there has been a problem that the DMA transfer efficiency becomes very poor.

In the "cycle stealing transfer method", in addition to the same problems as described above, when another device occupies the bus as a bus master for a long time, the DMA controller cannot access the bus. As a result, there is a problem that the DMA transfer is awaited and the transfer cannot be completed within a predetermined time.

Further, in the "timer interrupt transfer method", the device which occupies the bus as the bus master is forcibly switched by the timer interrupt regardless of the convenience of the device acting as the bus master, so that the data transfer efficiency is poor. was there.

In view of the above, the present invention does not allow another device to wait for a long time even when a certain device is transferring data as a bus master (for example, during DMA transfer) and continuously transfers a predetermined number of data. It is an object of the present invention to provide a data transfer method and a bus master control device which can occupy a bus while transferring data and improve the data transfer efficiency in both devices.

[0011]

The method of the present invention is a method for transferring data over a bus, wherein a first device occupies the bus as a bus master, and wherein the first device comprises Transferring a first predetermined number of data among the data to be transferred while occupying the bus; and determining whether the transfer of the first predetermined number of data is completed; After determining that the transfer of the first predetermined number of data has been completed, determining whether or not the first device releases the bus in accordance with the presence or absence of a request from a second device; If it is determined that the first device releases the bus, the first device releases the bus, thereby achieving the above object.

In one embodiment, after the first device releases the bus, the second device occupies the bus as a bus master, and the second device finishes accessing the bus. After the second device releases the bus, after the second device releases the bus, the first device re-occupies the bus; and Further transferring a second predetermined number of data subsequent to the transferred first predetermined number of data while the bus is occupying the bus again.

In one embodiment, if it is determined that the first device does not release the bus, the first device continues to occupy the bus and follows the first predetermined number of transferred data. Transferring a second predetermined number of data.

In one embodiment, a step of determining whether or not the transfer of all of the data to be transferred has been completed, and a step of determining that the transfer of all of the data to be transferred has been completed,
Releasing the bus.

[0015] In one embodiment, the first device comprises a D
An MA controller, and the second device is a CPU.

A bus master control device according to the present invention is a bus master control device for controlling the operation of a bus master that performs data transfer via a bus, and responds to a data transfer request.
Bus occupancy requesting means for outputting a signal requesting occupation of the bus, and data transfer means for transferring a first predetermined number of data to be transferred while the bus master is occupying the bus. And bus release instructing means for outputting a signal for instructing release of the bus after the transfer of the first predetermined number of data is completed, thereby achieving the above object.

In one embodiment, the bus occupancy request means outputs a signal requesting occupation of the bus again after the bus release instruction means outputs the bus release instruction signal, and the data transfer means comprises: While the bus master is re-occupying the bus, the bus master transfers a second predetermined number of data following the transferred first predetermined number of data.

In one embodiment, the bus release instructing means outputs a signal for instructing release of the bus after all the data to be transferred have been transferred.

In one embodiment, the data transfer means includes a first counter for counting the number of transferred data out of the first predetermined number of data, and the second counter based on an output of the first counter. A first determination unit that determines whether the transfer of the predetermined number of data has been completed.

In one embodiment, the data transfer means includes a second counter for counting the number of transferred data out of all the data to be transferred, and the data to be transferred based on an output of the second counter. And a second determination unit for determining whether or not all the transfer has been completed.

The operation will be described below.

According to the present invention, with the above structure, after the first device has completed the transfer of a predetermined number of data as a bus master, the first device releases the bus in response to a request from the second device. Accordingly, even when data transfer is being performed by the first device, the second device does not wait for a long time because it becomes the bus master.

After the second device releases the bus, the first device again occupies the bus as a bus master, and transfers a predetermined number of data following the transferred predetermined number of data. By performing data transfer every predetermined number in this manner, data transfer by the first device is efficiently performed.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing the configuration of the information processing device 408. The information processing device 408 includes the CPU 40
1, a peripheral device 404, a DMA controller 11, and a bus controller 9. The CPU 401, the peripheral device 404, and the bus controller 9 are connected by an internal bus 406. Further, the information processing device 408 is connected to the external memory 405 via the bus controller 9 and the external bus 407. Reference numeral 301 denotes a CPU transfer request signal for requesting the bus controller 9 to occupy the internal bus 406 and the external bus 407 by the CPU 401.
01 is a DMA activation request signal for requesting the DMA transfer from the DMA controller 11 by the peripheral device 404. D
The MA controller 11 and the bus controller 9 are connected by a line for transmitting a control signal and an address as described later.

The CPU 401 is a central processing unit that performs arithmetic processing and controls and controls overall processing of the information processing device 408. The peripheral device 404 is a device that performs a group of processes based on an instruction from the CPU 401.
For example, an external storage device such as a hard disk or an optical disk or a printer corresponds to this. The bus controller 9 controls access to the internal bus 406 and the external bus 407, and the CPU 401 and the D
It has an MA controller 11. The bus controller 9
Internal bus 406 and external bus 40 from these devices
The arbitration is performed for the occupation request of No. 7 to determine which device occupies the bus as a bus master. The DMA controller 11 controls data transfer (DMA transfer) between the peripheral device 404 and the external memory 405 without the intervention of the CPU 401 based on a request from the peripheral device 404.

FIG. 2 is a block diagram showing the configuration of the DMA controller 11.

The DMA controller 11 includes a source address register 1a, a destination address register 1b, and an address generator 7. Source address register 1a
Stores a source address which is a transfer source address in the DMA transfer. The transfer destination address register 1b stores the D
A destination address, which is a transfer destination address in MA transfer, is stored. Source address register 1a
And the output of the transfer destination address register 1b are connected to the address generator 7. In addition, the read acknowledge signal 106 and the write acknowledge signal 110 output from the bus controller 9 are input to the address generator 7. Read acknowledge signal 106
Indicates that the bus controller 9 accepts the DMA transfer request,
This signal indicates that reading of data to be DMA-transferred has started. Write acknowledge signal 110
Is a signal notifying that the bus controller 9 has started writing data to be DMA-transferred. The address generator 7 reads the contents of the transfer source address register 1a and the transfer destination address register 1b as a data transfer start address, and outputs the contents to the bus controller 9 as the transfer source address 105a and the transfer destination address 105b. Further, based on the read acknowledge signal 106 and the write acknowledge signal 110, the address generation unit 7 updates the addresses to be read and written next, and outputs them to the bus controller 9 as the transfer source address 105a and the transfer destination address 105b, respectively. As a result, a predetermined number of data are sequentially transferred.

The DMA controller 11 further includes a transfer number register 2 and an intermittent transfer number register 3. The transfer count register 2 stores the number of transfers to be DMA-transferred. The intermittent transfer count register 3 stores a predetermined value as the number of data to be transferred in one intermittent transfer. The DMA controller 11 intermittently transfers all data to be DMA-transferred several times for each predetermined number of data. In the present invention, a block transfer in which the bus master occupies the bus and transfers a predetermined number of data continuously is called intermittent transfer.

The DMA controller 11 has a counter 4,
It further includes a counter 5 and a decrementer 6. The counter 4 is reset at the start of the intermittent transfer, and the read acknowledge signal 1 input from the bus controller 9 is reset.
06 is counted. That is, the counter 4 counts the number of data that has been read from the transfer source out of the predetermined number of data to be transferred in the intermittent transfer.
The counter 5 is reset at the start of the intermittent transfer, and counts the transfer end signal 102 input from the bus controller 9. The transfer end signal 102 is a signal output by the bus controller 9 to notify that the DMA transfer of one data has been completed. That is, the counter 5
Counts the number of pieces of data that have been transferred after the data writing to the transfer destination has been completed among the predetermined number of pieces of data to be transferred in the intermittent transfer. The transfer end signal 102 is also input to the transfer count register 2 and the decrementer 6. The decrementer 6 decrements the output of the transfer number register 2 by one each time the transfer end signal 102 is asserted and outputs the result to the transfer number register 2. Therefore, the transfer number register 2 and the decrementer 6 count the number of transferred data out of all the data to be transferred, and the remaining number of data to be transferred is stored in the transfer number register 2.

DMA controller 11 further includes a DMA transfer control unit 8 for controlling DMA transfer. DMA
The transfer control unit 8 includes a DMA activation request signal 101, a read acknowledge signal 106, a write acknowledge signal 1
10, transfer end signal 102, output 108 of counter 4,
It receives the output 109 of the counter 5, the output 111 of the intermittent transfer number register 3 and the output 112 of the transfer number register 2 as inputs, and outputs an all transfer end signal 103 and a DMA transfer request signal 104. The DMA transfer control unit 8
In response to the DMA activation request signal 101 from the peripheral device 404, the bus controller 9 asserts the DMA transfer request signal 104 to request the bus occupation. Also, D
The MA transfer control unit 8 determines whether or not the transfer of a predetermined number of data in the intermittent transfer has been completed, based on the output 108 of the counter 4, the output 109 of the counter 5, and the output 111 of the intermittent transfer count register 3. DMA transfer control unit 8
Terminates the assertion of the DMA transfer request signal 104 output to the bus controller when it is determined that the transfer of a predetermined number of data in the intermittent transfer has been completed,
Instruct the release of the bus. The DMA transfer control unit 8 determines whether or not all data to be transferred has been transferred based on the output 112 of the transfer count register 2. When it is determined that the transfer of all data to be transferred has not been completed, after one intermittent transfer has been completed, the DMA transfer control unit 8 asserts the DMA transfer request signal Request for occupancy again, and control of the next intermittent transfer is performed similarly. When it is determined that the transfer of all the data to be transferred has been completed, the DMA transfer control unit 8
The assertion of the DMA transfer request signal 104 output to the bus controller 9 is terminated, and the release of the bus is instructed.

The bus controller 9 performs arbitration based on a DMA transfer request signal 104 from the DMA transfer control unit 8 and a CPU transfer request signal 301 from the CPU 401.
Either the DMA controller 11 or the CPU 401 serves as a bus master, and the internal bus 406 and the external bus 40
7 is occupied. DMA controller 1
1 is determined to occupy these buses, the bus controller 9 transfers the contents of the transfer source address 105a and the transfer destination address 105b output from the address generator 7 in the DMA controller 11 to the internal bus 40, respectively.
7 and the external bus 406 (or outputs the contents of the source address 105a and the destination address 105b to the internal bus 406 and the external bus 407, respectively). In this way, data reading and writing are controlled. The bus controller 9 outputs a read acknowledge signal 106 or a write acknowledge signal 1 indicating that data reading or writing has started, respectively.
10 is output to the DMA controller 11.

Next, the operation of the DMA controller 11 will be described with reference to FIGS.

FIG. 3 is an operation conceptual diagram showing an operation example of the DMA controller 11. One box is 1 as in FIG.
The data transfer is performed sequentially from left to right. The bus master for each data transfer is shown in a box. In the example shown in FIG.
The data transfer is divided into first to third intermittent transfer, each of which includes four data transfers. The CPU 401 occupies the bus between one intermittent transfer and the next intermittent transfer. When all 12 data transfers are completed, the DMA controller 11 releases the bus, and
Thereafter, the CPU occupies the bus.

FIG. 3A shows an example in which the CPU 401 occupies one cycle of the bus every time during intermittent transfer. Here, an example is shown in which the period during which the CPU 401 occupies the bus during intermittent transfer is one cycle, but the period during which the CPU 401 occupies the bus during intermittent transfer is not limited to one cycle. CPU40
1 can occupy the bus only for the required period, but usually, the CPU 401 needs to occupy the bus continuously for a short period of time. Therefore, immediately after releasing the bus, the DMA controller 11 can occupy the bus again, and transfer four data following the four data transferred earlier.

FIG. 3B shows that the CPU 401 occupies the bus for three cycles between the first intermittent transfer and the second intermittent transfer, and the CPU 4 occupies the bus between the second intermittent transfer and the third intermittent transfer.
An example in which the DMA controller 11 keeps occupying the bus and continuously performing data transfer because no bus occupation request is issued from 01 is shown.

In any case, the number of data transferred in one intermittent transfer is constant.

FIG. 4 is an operation timing chart of the first intermittent transfer in FIG. Information processing device 40 in order from the top
8, a DMA start request signal 101, a DMA transfer request signal 104, a read acknowledgment signal 106 for receiving a DMA transfer request from the bus controller 9 to the DMA transfer control unit 8, and notifying that reading has been started; The output 108 of the counter 4 and the write acknowledge signal 11 for notifying that the writing has been started from the bus controller 9 to the DMA transfer controller 8.
0, a transfer end signal 102 for notifying that the transfer has been completed from the bus controller 9 to the DMA transfer control unit 8, an output 109 of the counter 5, a transfer count register 2, a transfer source address 105a, a transfer destination address 105b, and a CPU transfer request signal 301 , An external bus 407, and an internal bus 406 for each clock cycle.

The DMA start request signal 101 and the CPU
The transfer request signal 301 is an active high signal whose signal is asserted in a high state. Also, a DMA transfer request signal 104, a read acknowledge signal 106, a write acknowledge signal 110, and a transfer end signal 10
An active low signal 2 is asserted when the signal is in a low state.

Next, the operation of the information processing apparatus 408 when the DMA controller 11 executes data transfer from the external memory 405 to the peripheral device 404 will be described in detail for each cycle. Here, it is assumed that four pieces of data are continuously transferred by one intermittent transfer, and one data at addresses 1000 to 1011 of the external memory 405 is stored.
The two pieces of data are stored in the peripheral device 404 at addresses 2000 to 20
An example is shown in which data is transferred to address 11 in three intermittent transfers.

(Preprocessing) First, based on a command from the CPU 401 or an external device, the DMA transfer control unit 8
The source address register 1a and the destination address register 1b store the source and destination addresses 10 respectively.
00 and 2000 are set, and “1
2 "and" 4 "in the intermittent transfer count register 3.

(T0 cycle) The peripheral device 404 receives the DM
A to the DMA transfer control unit 8 of the A controller 11
A start request signal 101 is asserted.

(T1 cycle) The DMA transfer control unit 8
It is detected that the MA activation request signal 101 has been asserted and has gone high, and the DMA transfer request signal 104 (low state)
Is output to the bus controller 9. Further, based on an instruction from the DMA transfer control unit 8, the address generation unit 7 transmits the source address register 1a and the destination address register 1a.
b, and reads 1 as the transfer source address 105a.
2,000 as the transfer destination address 105b
The address is output to the bus controller 9. In addition, DMA
The transfer control unit 8 resets the counter 4 and the counter 5.

(T2 cycle) The bus controller 9 which has detected that the DMA transfer request 104 from the DMA transfer control unit 8 has been set to the low state, generates the CPU transfer request signal 301.
Is not asserted, it is determined that the DMA controller 11 occupies the bus. The bus controller 9
Reading of address 1000 from the external memory 405 is started from the external bus 407, and at the same time, the read acknowledge signal 1
06 (low state) is output to the DMA transfer control unit 8.

(T3 cycle) When the address generation unit 7 detects that the read acknowledge signal 106 in the low state has been input, the address generation unit 7 changes the transfer source address 105a to the next 1001.
The address is updated to the address and output to the bus controller 9. The counter 4 counts the read acknowledge signal 106 and sets the content to 1.

(T4 cycle) The bus controller 9
When the reading of the address 1000 by the external bus 407 is completed, the reading of the next address 1001 from the external memory 405 is started, and the address of the external memory 1000 is transferred to the address 2000 of the peripheral device 404 via the internal bus 406.
Writing of the data read from the address starts. At the same time, the bus controller 9 reads the read acknowledge signal 1
06 (low state) and write acknowledge signal 11
0 (low state) is output to the DMA transfer control unit 8.

(T5 cycle) When the address generation unit 7 detects that the read acknowledge signal 106 in the low state has been input, the address generation unit 7 changes the transfer source address 105a to the next 1002.
Address, and write acknowledge signal 1 in low state
10 is detected, the transfer destination address 105 is detected.
b is updated to the next address 2001, and each address is output to the bus controller 9. Further, the counter 4 counts the read acknowledge signal 106 and sets the content to 2. The bus controller 9 returns the read acknowledge signal 106 and the write acknowledge signal 110 to the high state after the timing when they are received by the address generator 7. Note that these signals are returned to the high state at the same timing in the next data transfer, but description thereof will be omitted.

(T6 cycle) The bus controller 9
When the reading of the address 1001 by the external bus 407 is completed, the reading of the next address 1002 from the external memory 405 is started, and the address of the external memory 100 is transferred to the address 2001 of the peripheral device 404 via the internal bus 406.
Writing of the data read from address 1 is started. At the same time, the bus controller 9 outputs the read acknowledge signal 106 (low state) and the write acknowledge signal 1
10 (low state) is output to the DMA transfer control unit 8. Further, when the writing of the address 2000 by the internal bus 406 is completed, the bus controller 9 sends a transfer end signal 102 (low state) to the DMA transfer control unit 8.

(T7 cycle) Upon detecting that the low-level read acknowledge signal 106 has been input, the address generation unit 7 changes the transfer source address 105a to the next 1003.
Address, and write acknowledge signal 1 in low state
10 is detected, the transfer destination address 105 is detected.
b is updated to the next address 2002, and each address is output to the bus controller 9. The counter 4 counts the read acknowledge signal 106 and sets the content to 3,
The counter 5 counts the transfer end signal 102 and sets the content to 1
To Furthermore, the content “12” stored in the transfer count register 2 is decremented by 1 by the decrementer 6 according to the transfer end signal 102, and the value is output to the transfer count register 2. Therefore, a new value “11” is stored in the transfer count register 2.

(T8 cycle) The bus controller 9
When the reading of the address 1002 by the external bus 407 is completed, the reading of the next address 1003 from the external memory 405 is started, and the address of the external memory 100 is transferred to the address 2002 of the peripheral device 404 via the internal bus 406.
Writing of the data read from address 2 is started. At the same time, the bus controller 9 outputs the read acknowledge signal 106 (low state) and the write acknowledge signal 1
10 (low state) is output to the DMA transfer control unit 8. In addition, when the writing of the address 2001 by the internal bus 406 is completed, the bus controller 9 sends the transfer end signal 102 to the DMA transfer control unit 8 to be in the low state.

(T9 cycle) When the address generation unit 7 detects that the write acknowledge signal 110 in the low state has been input, the address generation unit 7 changes the transfer destination address 105b to the next 2003.
The address is updated to the address and output to the bus controller 9. The counter 4 counts the read acknowledge signal 106 and sets the content to 4, and the counter 5 counts the transfer end signal 102 and sets the content to 2. Further, in response to the transfer end signal 102, the content "1"
"1" is decremented by 1 by the decrementer 6, and the value is output to the transfer number register 2. Therefore, a new value “10” is stored in the transfer count register 2.

(T10 cycle) Bus controller 9
Indicates that reading of the address 1003 by the external bus 407 has been completed and the peripheral device 4 via the internal bus 406
Writing of data read from address 1003 of the external memory to address 2003 of address 04 starts. At the same time, the bus controller 9 outputs a write acknowledge signal 110 (low state) to the DMA transfer control unit 8. When the writing of the address 2002 by the internal bus 406 is completed, the bus controller 9 sends a transfer end signal 102 (low state) to the DMA transfer control unit 8.

The output 111 of the intermittent transfer number register 3 and the output 1 of the counter 4 input to the DMA transfer controller 8
Since the values of 08 and 4 coincide with each other, the DMA transfer control unit 8 determines that the data read from the transfer source of one intermittent transfer has been completed, terminates the assertion of the DMA transfer request signal 104, and Instruct release.

(T11 cycle) The counter 5 counts the transfer end signal 102 and sets the content to 3. Further, the content “10” stored in the transfer count register 2 is decremented by 1 by the decrementer 6 according to the transfer end signal 102, and the value is output to the transfer count register 2. Therefore, a new value “9” is stored in the transfer count register 2.

(T12 cycle) Bus controller 9
When the writing of the address 2003 by the internal bus 406 is completed, the bus controller 9 sends a transfer end signal 102 (low state) to the DMA transfer control unit 8.

(T13 cycle) The counter 5 counts the transfer end signal 102 and sets the content to 4. Furthermore, the content “9” stored in the transfer count register 2 is decremented by 1 by the decrementer 6 according to the transfer end signal 102, and the value is output to the transfer count register 2. Therefore, a new value “8” is stored in the transfer count register 2.

CPU transfer request signal 3 from CPU 401
An example is shown where 01 is in the high state and there is a bus occupation request from the CPU 401. The bus controller 9
A CPU transfer request signal 301 from the CPU 401 is detected, and arbitration for bus occupation is performed. Since the DMA controller 11 does not issue the bus occupation request by setting the DMA transfer request signal 104 to the high state, the DMA
It is decided to occupy the bus from 14 cycles.

(T14 cycle) Since the output 111 of the intermittent transfer number register 3 and the output 109 of the counter 5 input to the DMA transfer control unit 8 are both 4 and coincide with each other, the DMA transfer control unit 8 performs It is determined that the intermittent transfer has been completed including the data writing to the transfer destination. DM
The A transfer control unit 8 outputs the DMA transfer request signal 104 (low state) again to the bus controller 9 for the second intermittent transfer. However, the bus controller 9 receives the CPU transfer request signal 3 from the CPU 401 in the cycle t13.
01 is detected, and in the cycle t14, as a result of the bus arbitration, the CPU 401 occupies the bus as a bus master and starts the transfer. This transfer corresponds to the transfer between the first intermittent transfer and the second intermittent transfer in FIG. Therefore, D
The MA transfer request signal 104 continues to be output and the CPU 401
Releases the bus, the bus controller 9 accepts the bus occupation request of the DMA controller 11.

If there is no transfer request 301 from the CPU 401, the bus controller 9 receives the DMA transfer request signal 104 in the cycle following the t14 cycle. In this case, the DMA controller 11 keeps occupying the bus without releasing it, and performs the next intermittent transfer.

The first intermittent transfer is executed by the above process, and the external memory 405 is connected via the external bus 407.
Are read from the addresses 1000 to 1003 of the peripheral device 404 via the internal bus 406.
It is written to address 03. The second intermittent transfer in FIG. 3 is started when the CPU 401 releases the bus and the DMA transfer request signal 104 continuously output from the cycle t14 is detected by the bus controller 9, and is executed in the same manner as the first intermittent transfer. The external memory 4 via the external bus 407.
05 read from addresses 1004 to 1007 of the peripheral device 404 via the internal bus 406.
It is written to address 2007. Similarly, in the third intermittent transfer, data read from the addresses 1008 to 1011 of the external memory 405 via the external bus 407 are transferred to the peripheral devices 404 via the internal bus 406.
It is written to address 1. In the third intermittent transfer, when the fourth transfer end signal 102 is asserted, the content of the transfer count register 2 becomes 0. Detecting that the output 112 of the transfer count register 2 input to the DMA transfer control unit 8 has become 0, the DMA transfer control unit 8 determines that the transfer of all data to be transferred has been completed, and An all transfer end signal 103 for instructing the release of the bus is output to the controller 9, and all the transfer processes are completed.

It should be noted that even if there is a cycle in which the bus cannot be used for data transfer due to a DRAM refresh process having a higher priority interrupted during the DMA transfer, the end of the intermittent transfer is determined not by time but by transfer. This is performed based on the number of data. Therefore, the number of data in one intermittent transfer is guaranteed.

The number of data in one intermittent transfer has been described as four. However, the number of data need not be limited to four. It is also possible to set to 3.

In the embodiment of the present invention, the CPU 401 is used as a device other than the DMA controller 11, but the same applies to a case where a device other than the CPU acts as a bus master. It is needless to say that the present invention is applicable even when there are three or more devices that can be bus masters.

In the embodiment of the present invention, the DMA transfer of the DMA controller 11 performs the intermittent transfer every predetermined number of data. However, the data transfer by the CPU 401 performs the intermittent transfer every predetermined number of data. The DMA controller 11 may be configured to perform data transfer during intermittent transfer by the CPU 401.

In the embodiment of the present invention, the end of one intermittent transfer is determined based on the output 111 of the intermittent transfer count register 3 and the output 108 of the counter 4 from the transfer source of one intermittent transfer. When it is determined that the data reading has been completed, it is determined that one intermittent transfer has been completed.
The assertion of the A-transfer request signal 104 is terminated and the release of the bus is instructed.
Based on 1 and the output 109 of the counter 5, 1
It may be determined that the intermittent transfer has been completed one time, and the assertion of the DMA transfer request signal 104 is ended to instruct the release of the bus.

[0066]

As described above, according to the present invention, after the first device has completed the transfer of a predetermined number of data as the bus master, the first device transfers the bus in response to the request from the second device. Is released, for example, even when the first device is performing the DMA transfer in which the number of data to be transferred is large as the bus master, the second device does not wait for a long time to become the bus master. .

Also, after the second device releases the bus, the first device occupies the bus again, and can transfer a predetermined number of data following the transferred predetermined number of data. Since the number of data transferred by the transfer is guaranteed, the data transfer by the first device is efficiently performed.

In the present invention, the time period during which the device can occupy the bus as a bus master is not fixed and the occupation and release of the bus are not forcibly switched as in the prior art. Therefore, for example, the time from the DMA start request to the acceptance is not constant, or there is a cycle in which the bus cannot be used for the data transfer due to the interruption of the DRAM refresh processing having a higher priority during the DMA transfer. For this reason, there is no inconvenience that the number of data that can be transferred in one continuous data transfer is not guaranteed. Since the end of the intermittent transfer is determined not based on the time but on the number of transferred data, the number of data that can be continuously transferred in one intermittent transfer is guaranteed. Due to the data processing in the CPU and peripheral devices, there is a case where data can be efficiently processed by performing data transfer in a predetermined number of data, for example, in units of 8 bytes. Also, DRA
If, for example, 256 bytes of data of the same page are continuously transferred as in the M high-speed page mode, data transfer can be performed very quickly and efficiently. Particularly in such a case, a great effect of the present invention can be obtained.

Further, after the second device occupies the bus as a bus master, the bus is not forcibly released depending on the time, so that the data transfer can be performed efficiently also for the second device.

Therefore, according to the present invention, it is possible to provide a data transfer method and a bus master control device capable of improving data transfer efficiency in both devices acting as bus masters.

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing apparatus using a DMA controller according to an embodiment of the present invention.

FIG. 2 is a block diagram of a DMA controller according to an embodiment of the present invention.

FIGS. 3A and 3B are operation conceptual diagrams showing an example of an operation of DMA transfer according to the embodiment of the present invention;

4 is an operation timing chart of the first intermittent transfer shown in FIG. 3 in the embodiment of the present invention.

FIGS. 5A to 5D are conceptual diagrams of the operation of a conventional DMA controller.

[Explanation of symbols]

 1a transfer source address register 1b transfer destination address register 2 transfer count register 3 intermittent transfer count register 4,5 counter 6 decrementer 7 address generator 8 DMA transfer controller 9 bus controller 11 DMA controller 401 CPU 404 peripheral device 408 information processing device 406 Internal bus 407 External bus 405 External memory

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masato Suzuki 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. 72) Inventor Junichi Yasui 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture F-term in Matsushita Electric Industrial Co., Ltd. 5B061 BA01 BA03 BB12 BB14 DD11 RR03 RR05

Claims (10)

[Claims] 1. A method for transferring data via a bus, wherein a first device occupies the bus as a bus master, and wherein the first device occupies the bus and transfers the data. Transferring a first predetermined number of data among the data to be transferred; determining whether the transfer of the first predetermined number of data is completed; and transferring the first predetermined number of data. Determining that the first device has released the bus according to the presence or absence of a request from a second device after the determination has been completed; and the first device has released the bus. If so, the first device releases the bus. 2. After the first device releases the bus, the second device occupies the bus as a bus master; and after the second device finishes accessing the bus,
The second device releasing the bus; the second device releasing the bus, the first device re-occupying the bus; and the first device releasing the bus. While occupying again,
The method of claim 1, further comprising transferring a second predetermined number of data subsequent to the transferred first predetermined number of data. 3. If it is determined that the first device does not release the bus, the first device continues to occupy the bus, and the second device follows the transferred first predetermined number of data.
Transferring a predetermined number of data. 4. The method according to claim 1, further comprising: determining whether or not the transfer of all the data to be transferred is completed; and releasing the bus after determining that the transfer of all the data to be transferred is completed. The method of claim 1 comprising: 5. The method according to claim 1, wherein said first device is a DMA controller, and said second device is a CPU. 6. A bus master control device for controlling an operation of a bus master performing data transfer via a bus, comprising: a bus occupation requesting means for outputting a signal requesting occupation of the bus in response to a data transfer request. Data transfer means for transferring a first predetermined number of data to be transferred in a state where the bus master occupies the bus; and after the transfer of the first predetermined number of data, A bus release instructing unit for outputting a signal instructing release of the bus. 7. The bus occupation requesting means, after the bus release instruction means outputs the bus release instruction signal, outputs again a signal requesting occupation of the bus. 7. The bus master control device according to claim 6, wherein a second predetermined number of data subsequent to the transferred first predetermined number of data is transferred while the bus is occupied again. 8. The bus master control device according to claim 6, wherein said bus release instruction means outputs a signal instructing release of said bus after transfer of all data to be transferred is completed. 9. The data transfer means includes: a first counter for counting the number of transferred data among the first predetermined number of data; and a first predetermined counter based on an output of the first counter. 7. The bus master control device according to claim 6, further comprising: a first determination unit configured to determine whether the transfer of the number of data is completed. 10. The data transfer means includes: a second counter for counting the number of transferred data out of all the data to be transferred; and transferring the data to be transferred based on an output of the second counter. 10. The bus master control device according to claim 9, further comprising: a second determination unit configured to determine whether or not all the processes have been completed.