JPH10189619A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent instability of the operation of an element which is caused by the exposure of the surface of a GaAs layer, and the deterioration of the element. SOLUTION: A GaAs operating layer 2 is provided on a semi-insulating GaAs substrate 1 and an insulating film 3 having an opening in a gate part is formed on the layer 2. The GaAs operating layer is etched using the film 3 as a mask to form a recess 4. A WSi layer 5 for forming a Schttky gate is formed. As the coverage of the WSi layer, which is formed by sputtering, is bad, gaps are generated in the bent part of the layer 5. These gaps are filled with each SOG film 6. An Au later 7 for reducing a gate resistance is deposited on the layer 5 and the layers 7 and 5 are patterned to form a gate electrode 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a gate electrode structure of a high-power field-effect transistor having a recess using a compound semiconductor layer such as GaAs as an operation layer, and a method of manufacturing the same. is there.

[0002]

2. Description of the Related Art In a high-output field effect transistor (hereinafter referred to as an FET) using GaAs as an operation layer, a refractory metal silicide such as WSi is used as a gate metal for improving thermal stability or reliability. Used. In addition, since there is a problem that the gate resistance increases only with the high melting point metal silicide, a structure in which a low resistance metal such as Au is formed in the upper layer is used. Further, a one-stage or two-stage recess structure is adopted for the purpose of reducing the parasitic resistance and improving the drain withstand voltage.

FIG. 6A is a sectional view showing the structure of a conventional semiconductor device of this kind. As shown in the figure, 1 is a semi-insulating GaAs substrate, 2 is a semi-insulating GaAs substrate 1
A GaAs operation layer formed thereon by an ion implantation method or an epitaxial growth method, 3 is an insulating film made of a CVD SiO ₂ film or the like and having an opening in a gate portion, 4 is an insulating film 3
Recesses formed by etching using
Is a WSi layer formed by sputtering or the like, and 7 is Au
Layer 8 is a gate electrode. In this structure, since the Schottky junction is formed of WSi, it has excellent thermal stability and has sufficient reliability as a gate of a high-output FET. Further, since Au is formed in the upper layer, the gate resistance is small and good high-frequency characteristics can be obtained. An FET having a gate electrode including a WSi layer and an Au layer is known, for example, from JP-A-8-97236.

[0004]

The above-mentioned conventional FETs
In FIG. 6B, the recess portion is formed by undercutting the insulating film 3 and the WSi layer is formed by a sputtering method having poor surface coverage, so that the recess in the recess is formed as shown in FIG. The gap 12 is likely to be formed at the bent portion of the WSi layer. In GaAs FETs, the GaAs surface is usually SiO
_{Although the} surface is not exposed because it is covered with a protective film such as ₂ or SiN or an electrode metal, the GaAs surface is partially exposed in the gap formed at the bent portion of WSi as described above. Although a large amount of surface levels are formed on the exposed GaAs surface, many of them are deep levels, and when they act as electron traps or hole traps,
Since the trap is charged and discharged by the input signal of the FET, the characteristics of the FET fluctuate. Particularly noticeable phenomena are the occurrence of hysteresis in the drain current-voltage characteristics or the temporal variation of the gate-drain breakdown voltage, and the high-frequency characteristics of the device become unstable.

In order to reduce the gate resistance, Au is formed on the upper layer.
In the case of forming a low-resistance metal such as Au, after reaching a high temperature for a long time, Au reaching the GaAs surface through the gap of WSi diffuses into the GaAs, thereby deteriorating Schottky characteristics and fluctuation of threshold voltage. In addition, undesired phenomena such as deterioration of the gate-drain breakdown voltage occur, which hinders stable operation of the device. Therefore, the problem to be solved by the present invention is that even if a gap is formed in the metal film forming the Schottky gate, it is possible to prevent characteristic deterioration and characteristic fluctuation due to the gap, and An object of the present invention is to provide a reliable FET.

[0006]

According to the present invention, an insulating film is formed on a semiconductor operating layer, and a recess is formed on the semiconductor operating layer in an opening of the insulating film. In a semiconductor device in which a gate electrode made of a Schottky junction forming material and a low resistance metal material is formed on the recess, a gap formed in a bent portion of the Schottky junction forming material layer is filled with an SOG film. A semiconductor device characterized by being provided.

Further, according to the present invention, (1) an insulating film is formed on a semiconductor operating layer, and the insulating film is selectively etched to expose the surface of the semiconductor operating layer to the insulating film. Forming a recess on the surface of the semiconductor operation layer by selectively etching the semiconductor operation layer using the insulating film as a mask; and (3) forming a Schottky on the entire surface including the inside of the recess. A step of applying a bonding forming material layer, and (4) applying and firing an SOG film forming material to form an SOG film.
After forming the film, the film is etched back to bury a gap formed in the bent portion of the Schottky junction forming material layer with an SOG film; and (5) a low-resistance metal film is deposited on the entire surface, Patterning a resistive metal film and a Schottky junction forming material layer to form a gate electrode on the recess, thereby providing a method of manufacturing a semiconductor device.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view of a semiconductor device for explaining an embodiment of the present invention. As shown in FIG. 1, a GaAs active layer 2 is formed on a semi-insulating GaAs substrate 1 by an ion implantation method or an epitaxial growth method such as MBE (molecular beam epitaxial growth) or MOCVD (metal organic chemical vapor deposition). An insulating film 3 such as a CVD SiO ₂ film is formed on the operation layer 2. The insulating film 3 on the gate portion is selectively etched away, and a recess 4 is formed on the surface of the GaAs operation layer 2 below the opening. On this recess, WSi forming a Schottky junction with GaAs is formed.
A layer 5 is formed, and an Au layer 7 is formed on the WSi layer 5 by sputtering to reduce gate resistance. Here, a silicon oxide film formed by spin coating and baking of a silicon compound solution, that is, an SOG film 6 is buried in a gap generated in the bent portion of the WSi layer 5 in the recess portion.

According to the present invention, the WS of the recessed portion is
The gap formed in the bent portion of the i-layer is filled with the SOG film. Therefore, the surface of GaAs is protected by the SiO ₂ film, and the surface is stabilized.
This suppresses fluctuations in FET characteristics due to charging and discharging of the interface trap. Also, S between Au and GaAs
Even if the OG film intervenes, Au may be exposed to the high-temperature atmosphere for a long time.
It does not diffuse into As, and the degradation of the Schottky characteristic or the fluctuation of the threshold voltage is suppressed, so that the operation can be stabilized and the reliability of the device can be improved.

FIG. 2 shows that the FET according to the present invention is heated at a high temperature (30
6 is a graph showing a change with time of a threshold voltage Vt when left in an atmosphere (0 ° C.) in comparison with a conventional example. While the threshold value of the FET of the conventional structure fluctuates in several tens of hours, the FET of the present invention hardly fluctuates, and stable characteristics are obtained.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIGS. 3A to 3D and FIG. 4E
FIGS. 2G to 2G are cross-sectional views in the order of steps for explaining the manufacturing method according to the first embodiment of the present invention. First, as shown in FIG. 3A, a GaAs operation layer 2 is provided on a semi-insulating GaAs substrate 1 by MOCVD, and a photoresist film 9 having an opening in a gate formation portion is formed thereon. GaAs is selectively etched using an etchant such as a mixture of sulfuric acid and hydrogen peroxide to form a first recess 4 a on the surface of the GaAs operation layer 2. Here, an appropriate range is selected for the recess depth and the recess width so as to satisfy the required characteristics of the FET. Next, as shown in FIG. 3B, after removing the photoresist film 9, SiO ₂ is deposited to a thickness of 500 nm on the entire surface by thermal CVD to form an insulating film 3. Next, the insulating film 3 is selectively etched by a photolithography method and reactive dry etching using CF ₄ gas to form an opening 10 as shown in FIG.

After the photoresist is removed, the insulating film 3 is used as a mask to form GaAs using a mixed solution of sulfuric acid and hydrogen peroxide.
The GaAs active layer 2 is etched using an s etching solution, and a depth of 70 nm to 150 nm is formed in the first recess 4a.
The second recess 4b is formed. Next, as shown in FIG.
A WSi layer 5 of 00 nm is formed. Next, as shown in FIG. 4E, a silicon compound solution is spin-coated on the entire surface to form an SOG film 6. Here, the thickness of the SOG film 6 is W
The thickness is adjusted so that the gap formed in the bent portion of the Si layer 5 is filled.
It is formed to have a thickness of about 0 nm. After the formation of the SOG film 6, it is baked at 400 to 500 degrees and baked. Next, the SOG film in the flat portion is removed by performing etch back using a reactive dry etching method. Here, the etching time is adjusted so that the SOG film embedded in the gap of WSi is not etched. Next, as shown in FIG. 4F, an Au layer 7 is formed on the entire surface by a sputtering method. Here, the thickness of the Au layer is set to 4 in order to sufficiently reduce the gate resistance.
00 nm to 700 nm. Next, as shown in FIG.
Photoresist film (not shown) so that it becomes wider by ~ 1 μm
Then, using this as a mask, the Au layer 7 and the WSi layer 5 are patterned by, for example, an ion milling method to form a “T” -shaped gate electrode 8. Thereafter, an ohmic electrode is formed in the source electrode and drain electrode formation regions to complete the FET. This ohmic electrode may be formed prior to the step of FIG.

[Second Embodiment] Next, a second embodiment of the present invention will be described with reference to FIG. FIG.
(C) is a step-by-step cross-sectional view for describing the second example. Also in the second embodiment, the same steps as in the first embodiment are performed up to the steps shown in FIGS. After processing to the state shown in FIG. 3D, as shown in FIG. 5A, SiO ₂ is deposited using a thermal CVD method to form a film having a thickness of 3 nm.
A CVD SiO ₂ film 11 having a thickness of 0 nm to 50 nm is formed.
Next, as shown in FIG. 5B, an SOG film forming material is applied to the entire surface and baked to form an SOG film 6. Where SO
The film forming conditions for G are the same as those used in the first embodiment. Thereafter, the SOG film 6 and the CVD SiO ₂ film 11 are etched back, the Au layer 7 is deposited, and the Au layer 7 and the WS
Through the patterning step of the i-layer 5, the FE of the second embodiment
The manufacturing process of T is completed. According to this embodiment, since the film for protecting the GaAs surface in the gap of the WSi layer is a film formed by ordinary CVD, a better interface can be obtained than in the first embodiment, and a stable device can be obtained. Characteristics are obtained.

[0014]

As described above, in the semiconductor device according to the present invention, the gap formed at the bent portion of the WSi layer in the recess is formed by S.
Since it is embedded by OG, Ga in the gap
The surface of the As layer will be protected by the SiO ₂ film,
Characteristic fluctuations such as hysteresis in drain current / voltage characteristics and fluctuations in gate-drain breakdown voltage, which are caused by exposing the surface of the GaAs operation layer, are suppressed, and stable element characteristics can be obtained. In addition, since the SiO ₂ film is interposed between the upper metal such as the Au layer and the GaAs operation layer in the gap between the WSi portions, the diffusion of the upper metal material into the GaAs operation layer is suppressed, and the time is longer. Even when exposed to high-temperature conditions, FET characteristics do not fluctuate and stable characteristics can be obtained for a long period of time.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an embodiment of the present invention.

FIG. 2 is a graph showing a change in threshold voltage between an FET according to the present invention and a conventional example due to high-temperature storage.

FIG. 3 is a part of a process order sectional view for explaining the manufacturing method of the first embodiment of the present invention.

FIG. 4 is a step-by-step sectional view in a step that follows the step of FIG. 3 for explaining the manufacturing method of the first embodiment of the present invention.

FIG. 5 is a cross-sectional view in a process order for describing a manufacturing method according to a second embodiment of the present invention.

FIG. 6 is a sectional view of a conventional example.

[Explanation of symbols]

Reference Signs List 1 semi-insulating GaAs substrate 2 GaAs operation layer 3 insulating film 4 recess 4a first recess 4b second recess 5 WSi layer 6 SOG film 7 Au layer 8 gate electrode 9 photoresist film 10 opening 11 CVD SiO ₂ film 12 gap

Claims (5)

[Claims] An insulating film is formed on a semiconductor operating layer, a recess is formed on the semiconductor operating layer in an opening of the insulating film, and a Schottky junction forming material and a low-resistance metal material are provided on the recess. A semiconductor device having a gate electrode formed therein, wherein a gap formed at a bent portion of a Schottky junction forming material layer is filled with an SOG film. 2. The method according to claim 1, wherein the Schottky junction forming material is WSi.
2. The semiconductor device according to claim 1, wherein said low-resistance metal material is Au. 3. The method according to claim 1, wherein the lower layer of the SOG film is CVD SiO _2.
2. The semiconductor device according to claim 1, wherein a film is formed. 4. The semiconductor device according to claim 1, wherein said recess is a short bottom length recess formed in a long bottom length recess. 5. A step of: (1) forming an insulating film on a semiconductor operating layer, and selectively etching the insulating film to form an opening in the insulating film to expose a surface of the semiconductor operating layer; (2) selectively etching the semiconductor operation layer using the insulating film as a mask to form a recess on the surface of the semiconductor operation layer; and (3) covering the entire surface including the inside of the recess with a Schottky junction forming material layer. And (4) applying and firing an SOG film forming material to form an SOG film, and then etching back the SOG film to fill a gap formed in a bent portion of the Schottky junction forming material layer with the SOG film. And (5) forming a gate electrode on the recess by depositing a low-resistance metal film on the entire surface and patterning the low-resistance metal film and the Schottky junction forming material layer. Characteristic semi Method of manufacturing a body apparatus.