JPH10189597A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate excess polishing in CMP and residues of material by a method wherein a non-pattern region whose area ratio to a buried region is set at a specific value or above is provided to the outer edges of connection holes or wiring grooves respectively when the adjacent connection holes or adjacent wiring grooves are filled with metal. SOLUTION: The sides a and b of a connection hole 103 are 1.0μm long respectively, and gaps d and c between the adjacent connection holes 103 are 0.5μm long respectively. As mentioned above, in a connection hole pattern, letting the area ratio of the outer edge of a blanked pattern to the blanked pattern be represented by Th , Th is expressed by a formula, Th = (a+c)(b+ d)-ab}/ab, and set at a certain value or above. Th is set at 70% in a case where connection holes are used and at 60% in a case where wiring grooves are used in place of connection holes. After filling wiring material 105 is filled into the connection holes 103, filling wiring material 105 except in the connections holes 103 is removed with CMP to planarize the surface. By this setup, a semiconductor device of this constitution can be protected against dishing which occurs when CMP is carried out, and residues of abrasive material used for CMP can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a technique for embedding in a wiring groove and a connection hole.

[0002]

2. Description of the Related Art In a conventional multi-layer wiring forming process, a refractory metal or an Al alloy is formed on an insulating film to form a wiring thereon, and then an interlayer insulating film is formed and then, for example, by an etch-back method. Steps of flattening, opening a connection hole in an interlayer insulating film, coating a high melting point metal or an Al alloy by sputtering, and forming a wiring were repeated. The wiring and the connection hole are formed by lithography and etching. However, the aspect ratio (ratio of height to width) of the connection hole has become very large with the miniaturization of the integrated circuit. Incomplete filling of metal into the interior. Therefore, after the metal film is formed in the connection hole by sputtering, reflow is performed, and the metal film other than the connection hole is subjected to CMP.
(Chemical Mechanical Polishing)
In this method, a metal film is buried in a connection hole by removing the metal film by a method. In recent years, with respect to wiring formation, multilayer wiring has been promoted along with miniaturization of integrated circuits. As in the case of connection holes, the wiring aspect ratio (ratio of height to width) has been increased, and product stability has been increased. Stricter flatness has been required to secure the yield and reliability. Therefore, instead of the multilayer wiring forming step, an embedded wiring method in which a wiring groove is formed on an interlayer insulating film and a wiring material is embedded therein has been studied. As a future wiring material, because of its low resistance and high reliability characteristics, Cu wiring is one of the candidates instead of Al wiring, but it is difficult to process Cu wiring by conventional RIE. From the above, the embedded wiring method also has the effect of reducing costs by reducing the number of steps (reduction in the number of steps for processing the wiring, flattening of the wiring and interlayer insulating film, etc.). The study of embedded wiring is becoming active. In the case of buried wiring, a method is used in which the metal film is buried in the wiring groove by removing the metal film other than the wiring groove by CMP after forming the metal film in the wiring groove by sputtering and removing the metal film other than the wiring groove by CMP.

[0003] A conventional example will be described below with an example of embedding in the connection hole. FIG. 5 shows an example of a manufacturing process in a connection hole of a semiconductor device according to a conventional technique. In the figure, 50
1 is a semiconductor substrate, 502 is an insulating film, 503 is a connection hole,
Reference numeral 05 denotes a connection hole filling material. FIG. 5A shows a top view of the connection hole pattern. The connection holes are 1.0 μm square, and the interval between adjacent connection holes is 0.3 μm. FIG.
FIG. 5B is a sectional view taken along line AB in FIG.
In the step of burying the connection holes, as shown in FIG. 5B, first, the insulating film 502 is coated, and the connection holes 503 are formed by lithography and etching. Next, as shown in FIG. 5C, a filling material 505 is formed in the connection hole 503 by sputtering. Thereafter, as shown in FIG.
Embedding is performed by heating by laser irradiation of 5 J / cm ² and flowing the embedding material into the connection holes. Thereafter, as shown in FIG. 5 (e), the connection hole filling material 505 other than the connection holes 503 is polished and removed by CMP to planarize the surface, thereby burying the connection holes 503. After such a step, even if the reflow of FIG. 5D is performed, the surface undulation of the burying material is large. In this state, if CMP is performed as shown in FIG. Excessive polishing of the embedding material by CMP) or residual CMP (residue on the insulating film) occurs. The dishing causes an increase in wiring resistance and a deterioration in wiring reliability such as an operation failure or a decrease in yield due to a variation in wiring resistance within or between wafer surfaces, or a reduction in life due to electromigration. As described above, the connection hole has been described, but the wiring groove shown in FIG. 6 also has a common problem. The present invention provides a method of manufacturing a semiconductor device which solves this problem.

[0004]

As described above, in embedding a filling material into a connection hole or a wiring groove,
During polishing by CMP, excessive polishing at the buried portion and residue of the buried material at the outer edge of the buried portion occur, resulting in disconnection failure, increase in wiring resistance, and wiring resistance in the wafer surface and between surfaces. However, there has been a problem that the wiring reliability is deteriorated such as an operation failure due to variations in the device or a shortened life due to electromigration.

[0005]

When a metal film is buried in an adjacent connection hole or an adjacent wiring groove, an outer edge of each connection hole or the wiring groove has a predetermined ratio or more with respect to the area of each buried portion. A non-pattern region having an area is provided. The constant ratio is 70% for connection holes and 60% for wiring grooves.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to FIGS. FIG. 1 is a cross-sectional view illustrating an example of a manufacturing process of a semiconductor device according to the present invention. In the figure, 101 is a semiconductor substrate, 102 is an insulating film, 103 is a connection hole, and 105 is a filling material. FIG. 1A shows a top view of the connection hole. a and b are each 1.0 μm, that is, the connection hole is 1.0 μm square, and the intervals b and c between adjacent connection holes are each 0.5 μm. In such a via hole pattern, the ratio of open pattern area of opening pattern edge portion area is taken as _{T h, T h = {(} a + c)
(B + d) -ab} / ab is set to a certain value or more. FIG.
FIG. 2B is a cross-sectional view taken along line CD in FIG. When filling the connection holes, first, as shown in FIG. 1B, an insulating film is coated, and the connection holes are formed by lithography and etching. Next, as shown in FIG. 1C, 15 nm of Ti, 60 nm of TiN, and 1.0 μm of C
u film is sequentially formed by sputtering. After a while, FIG.
As shown in (d), for example, heating is performed by laser irradiation of 1.5 J / cm ² , and the embedding material is caused to flow so as to be embedded in the connection holes. Thereafter, as shown in FIG. 1E, planarization is performed by removing the material for filling the connection holes other than the connection holes by CMP, and the filling of the connection holes is performed. As described above, when there is a non-pattern region having a fixed ratio or more with respect to the area of each connection hole around each adjacent connection hole, the insulating film between the adjacent connection holes is formed at the stage of FIG. The film formation amount above can supply the necessary filling material to fill the volume of the connection hole,
As a result, at the time of reflow in FIG. 1D, the supply amount of the connection hole material to the connection hole becomes necessary and sufficient, and the surface unevenness of the filling material in the connection hole portion is reduced. Here, the non-pattern region refers to a planarized insulating film. The connection hole pattern has been described above.
FIG. 2 shows the case of the wiring groove pattern. The process is the same as that of the connection hole pattern, in which the filling material 205 is buried in the wiring groove 204 of FIG. 2B, but the above-mentioned area ratio is different in the wiring groove pattern as shown in FIG. Assuming that the ratio of the area of the outer edge portion of the cut pattern to the area of the cut pattern is T _s , T _s = f / e is set to a certain ratio or more. FIG. 3 compares the film thickness difference of the burying material between the punched pattern portion and the remaining pattern portion at this stage, that is, before the CMP. As described above, in both the connection hole pattern and the wiring groove pattern, the above film thickness difference can be reduced by setting the area of the outer edge of the pattern to a certain ratio or more with respect to the area of each pattern. In such a state, if CMP is performed as shown in FIG. 1D, dishing and remaining CMP do not occur. FIG. 4 shows the results of CMP yield when the ratio of the area of the outer edge of the cut pattern to the area of the cut pattern is changed. Where C
MP yield refers to the above-mentioned dishing or CMP after CMP.
It is a ratio that does not generate the remainder. Thus, 70% in the connection hole pattern and 60% in the wiring groove pattern.
It can be seen that a high CMP yield of 98% or more is obtained in the above region.

[0007]

As described above, according to the present invention, dishing and residual CMP which occur when performing CMP can be suppressed. Accordingly, the surface of the buried material or the insulating film becomes a flat surface, and as a result, a disconnection failure, an increase in wiring resistance, a malfunction due to a variation in wiring resistance within or between wafer surfaces, or a reduction in life due to electromigration. Deterioration of wiring reliability can be avoided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an example of a manufacturing process for a connection hole of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view illustrating an example of a manufacturing process in a wiring groove of the semiconductor device according to the present invention.

FIG. 3 is a graph comparing the film thickness difference between the buried pattern portion and the buried material portion of the remaining pattern portion before the CMP when the ratio of the area of the outer edge portion of the pierced pattern to the area of the pierced pattern is changed.

FIG. 4 is a graph showing the results of CMP yield when the ratio of the area of the outer edge portion of the cut pattern to the area of the cut pattern is changed.

FIG. 5 is a cross-sectional view illustrating an example of a manufacturing process for a connection hole of a semiconductor device according to a conventional example.

FIG. 6 is a cross-sectional view illustrating an example of a manufacturing process in a wiring groove of a semiconductor device according to a conventional example.

[Explanation of symbols]

 101 201 501 601: semiconductor substrate 102 202 502 602: insulating film 103 503: connection hole 204 604: wiring groove 105 205 505 605: embedded wiring material

Claims (4)

[Claims] A step of depositing an insulating film on a semiconductor substrate;
Forming a plurality of connection holes adjacent to the insulating film;
A step of coating a metal by sputtering, a step of reflowing the metal by heat treatment, and a step of removing a connection hole filling material other than the connection hole by chemical mechanical polishing after the reflow, wherein the connection of the insulating film is performed. A method of manufacturing a semiconductor device, comprising: forming each connection hole at an outer edge portion of the hole so as to form a non-patterned area of 70% or more of the area of each connection hole. Wherein the ratio of the area of each connection hole of the area of the non-pattern area is taken as _{T h, T h = {(} a
+ C) (b + d) -ab} / ab (where a and b are the lengths of one side of the connection hole, c and d are the distances between adjacent connection holes, and a and c are in the same direction). 2. The method for manufacturing a semiconductor device according to claim 1, wherein A step of depositing an insulating film on the semiconductor substrate;
Forming a plurality of wiring grooves adjacent to the insulating film;
A step of coating a metal by sputtering, a step of reflowing the metal by heat treatment, and a step of removing a wiring groove filling material existing in areas other than the wiring grooves by chemical mechanical polishing after the reflow, wherein the wiring of the insulating film is removed. A method of manufacturing a semiconductor device, comprising: forming each wiring groove apart at each outer edge of the groove so as to form a non-pattern area of 60% or more of the area of each wiring groove. 4. When the ratio of the area of the non-pattern region to the area of each wiring groove is T _s , T _s = f / e
(However, e is the width of the wiring groove, f is the distance between adjacent wiring grooves)
4. The method for manufacturing a semiconductor device according to claim 3, wherein