JP2005109138A - Manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device wherein a short circuit failure margin is enhanced by removing a bowing portion generated in a groove in a wiring process. <P>SOLUTION: This method comprises the steps of forming a protective film 54 on a semiconductor substrate 51 having a plurality of lower layer wiring lines 53 thereon, forming an insulating film 55 on the protective film 54, and forming via-holes 56 reaching the lower layer wiring lines 53 in the insulating film 55 by using a resist mask 59. Further, the method comprises the step of removing a taper shape formed in the upper portions of adjacent via-holes 56. Further, it comprises the steps of removing the protective film 54 exposed at the bottom of the via-holes 56, and forming wiring lines by filling the via-holes 56 with a barrier film 57 and a conductive film consisting of a metal film 58. Thus, the short circuit between the wiring lines can be prevented and yield is enhanced. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and relates to a method for manufacturing a semiconductor device having a multilayer wiring structure.

  In recent years, due to the high integration and miniaturization of semiconductor devices accompanying the advancement of semiconductor technology, multilayering and miniaturization of wiring have been advanced in the wiring process of semiconductor devices. Therefore, the wiring pitch is narrowed, and the performance of the semiconductor device is deteriorated due to an increase in inter-wiring capacitance and wiring delay. In order to prevent the performance degradation of the semiconductor device caused by such miniaturization of wiring, it is necessary to use a low resistivity wiring material and an interlayer insulating film having a low dielectric constant (hereinafter referred to as a low-k film). ing. For example, there is an active movement to use Cu having a lower resistance value (higher electromigration resistance) than Al instead of a conventional Al alloy as a wiring material.

  In a wiring formation method using Cu, a damascene method has been developed in which a metal film is embedded in a hole formed in an insulating film, and a metal film protruding from the hole is removed by planarization to form a via hole or a wiring. Yes. As the damascene method, there are a single damascene method and a dual damascene method, but the dual damascene method in which a via hole and a trench overlapping therewith are formed, and then a wiring material is embedded in the via hole and the trench so that the via and the wiring are simultaneously formed. It is.

  A wiring process in a conventional method for manufacturing a semiconductor device will be described below with reference to the drawings. 1A to 1J are cross-sectional views of a conventional wiring process.

  Insulating layer 2 formed on semiconductor substrate 1 and lower layer wiring 3 made of metal, protective film 4 formed on insulating layer 2 and lower layer wiring 3, and Low formed on protective film 4 As shown in FIG. 1A, a resist mask 6 for forming a via hole is formed on the upper surface of the interlayer structure composed of the −k film interlayer insulating film 5 by photolithography.

  Next, using this resist mask 6 as a mask, the interlayer insulating film 5 is etched up to the upper surface of the protective film 4 located above the lower layer wiring 3, and a via hole is formed above the lower layer wiring 3 as shown in FIG. 7 is formed. Thereafter, as shown in FIG. 1C, the resist mask 6 is removed by ashing.

  Subsequently, as illustrated in FIG. 1D, a resist 8 is applied over the entire interlayer insulating film 5 so as to fill the via hole 7.

  Thereafter, as shown in FIG. 1E, a resist mask 9 for forming a trench and a resist plug 10 for protecting the protective film 4 are formed in the via hole 7. Next, using this resist mask 9 as a mask, the interlayer insulating film 5 is etched to a predetermined depth so that the upper surface of the protective film 4 is not exposed, and a trench 11 for wiring is formed as shown in FIG. To do.

  Thereafter, as shown in FIG. 1G, the resist mask 9 is removed by ashing.

  Next, as shown in FIG. 1H, the protective film 4 exposed at the bottom of the via hole 7 is removed by etching for joining the metal film 13 and the lower layer wiring 3 to be formed later.

  Subsequently, as shown in FIG. 1I, a barrier film 12 made of a metal is formed so as to cover the inner walls of the via hole 7 and the trench 11 so as not to completely fill the via hole 7 and the trench 11. A metal film 13 is deposited so as to fill the trench 11.

Then, as shown in FIG. 1J, the barrier film 12 and the metal film 13 protruding from the surface of the interlayer insulating film 5 are removed by CMP, and the metal film 13 and the barrier film 12 are planarized ( For example, see Patent Document 1).
JP 2003-174085 A (page 4, FIG. 1)

  In order to form a resist mask having a finer pattern in the lithography process due to the recent demand for miniaturization of semiconductor devices, the light source has been changed from a KrF excimer laser to an ArF excimer laser having a short wavelength. However, in order to use an ArF excimer laser in the conventional method for manufacturing a semiconductor device, it is necessary to change the resist material in accordance with the wavelength of the laser. However, along with this, there is a problem that the resist becomes fragile. This is because the resist material used in the case of the ArF excimer laser is an acrylic material that does not have a benzene ring or the like. Therefore, the resist material used in the case of ArF excimer laser is vulnerable to oxygen plasma, and the resist mask may be scraped when the interlayer insulating film 5 is etched. On the other hand, since the interlayer insulating film 5 made of a low-k film also has poor dry etching resistance, the interlayer insulating film 5 may also be etched during etching as the resist mask 6 is etched.

  As a result, there is a problem that the upper opening diameter of the via hole 7 or the trench 11 is formed so as to be widened, and the interlayer insulating film 5 (hereinafter referred to as a shoulder drop portion) is formed on the via hole 7 and the trench 11 in a tapered shape. there were.

  As a result, since the width of the opening of the wiring is widened, there is a problem that a short circuit failure occurs at a portion where the wiring pitch is narrow.

  Hereinafter, it explains in detail using a drawing. FIG. 2A is an explanatory view of the shoulder drop portion at the time of via formation in FIG. 1C, and FIG. 2B is an explanatory view of the shoulder drop portion at the time of trench formation in FIG. is there.

  As shown in FIG. 2A, if a desired short defect margin in via formation is W1, and the distance between the upper end of one shoulder drop A and the upper end of the other shoulder drop A ′ is W2. The margin of short-circuit failure at a narrow via pitch is reduced by W1-W2 due to the shoulder drop portions A and A 'generated during via formation.

  Similarly, when the trench is formed, a shoulder drop A is generated, and as shown in FIG. 2B, a desired short defect margin in the trench formation is W3, and the upper end of one shoulder drop A and the other shoulder are formed. Assuming that the distance from the upper end of the drop A ′ is W4, the margin of short-circuit failure at a narrow wiring pitch is reduced by W3−W4.

  Therefore, there is a problem in that short-circuit defects are likely to occur, in which adjacent wirings are connected particularly at a location where the wiring pitch is narrow.

  In view of the above-described conventional problems, the present invention improves the margin between wirings, reduces shorts between wirings, and has high reliability by removing shoulder drop portions using a CMP method before forming a metal film. An object is to provide a semiconductor device.

  In order to solve the above-described conventional problems, the present invention includes a step of forming an adjacent groove in an insulating film using a resist mask, a step of removing a tapered shape formed on an upper portion of the adjacent groove, and an electrically conductive groove. And a step of forming a wiring by embedding with a film.

  As described above, the insulating film (hereinafter referred to as the shoulder drop portion) having a wide opening diameter generated in the upper portion of the groove when the groove is formed in the insulating film is scraped by the CMP method, thereby removing the gap between the grooves. Margin reduction can be prevented. Therefore, short-circuit defects between adjacent wirings can be reduced and electrical characteristics can be stabilized.

  The present invention also includes a step of forming an adjacent groove on an upper portion of a via hole formed in an insulating film using a resist mask, a step of removing a tapered shape formed on an upper portion of the adjacent groove, and an electrically conductive groove. And a step of forming a wiring by embedding with a film.

  In this way, by removing the insulating film and forming the groove by forming the groove on the upper portion of the via hole without removing the shoulder portion generated at the time of forming the via hole, the shoulder dropping portion generated at the time of forming the via hole is formed. Can be removed. Therefore, it is possible to reduce the step of removing the shoulder drop portion generated when the via hole is formed.

  Further, the present invention removes the step of forming a groove adjacent to the insulating film using a resist mask, the step of forming a resist plug below the taper shape, and the taper shape formed above the adjacent groove. The method includes a step, a step of removing a resist plug, and a step of filling a groove with a conductive film to form a wiring.

  Thus, the resist plug is formed so as to fill the groove from the groove bottom to the lower end of the shoulder drop portion at most. Therefore, the presence of the resist plug in the groove makes it possible to prevent the slurry used when the shoulder drop portion is scraped off by the CMP method from entering the groove and collecting the slurry.

  Further, since only the insulating film above the formed resist plug is scraped by CMP, it can be polished more uniformly than when two or more kinds of materials are scraped, and a good groove can be formed.

  Further, the present invention is formed on the upper part of the adjacent groove, the step of forming the adjacent groove in the insulating film using the resist mask, the step of applying the resist so as to fill the groove, the step of exposing the resist. It is characterized by having a step of removing the taper shape, a step of removing the resist in the groove, and a step of filling the groove with a conductive film to form a wiring.

  As described above, after forming the groove, a resist is applied in the groove, the resist is subjected to an exposure process, and then the shoulder drop portion is scraped off by a CMP method. Therefore, since the resist is changed to alkali-soluble by performing the exposure treatment, the resist and the insulating film can be removed from the upper surface of the insulating film to at least the lower end of the shoulder drop portion using an alkaline slurry. Therefore, since the resist and the insulating film can be polished using the same kind of slurry, the insulating film is flattened more uniformly than the case where the resist and the insulating film are polished without exposing the resist. be able to.

  Further, since the resist plug is formed in the groove simultaneously with the planarization of the insulating film, it is possible to prevent the slurry from entering the groove when CMP is performed using the resist plug.

  The present invention also includes a step of forming a via hole adjacent to an insulating film using a resist mask, a step of removing a tapered shape formed above the adjacent via hole, and a step formed in the insulating film using a resist mask. The method includes a step of forming a groove above the via hole, a step of removing a tapered shape formed above the adjacent groove, and a step of filling the groove with a conductive film to form a wiring.

  In this way, after removing the shoulder drop generated in the formation of the via hole, the shoulder drop generated in the upper part of the groove in the groove formation is scraped again by the CMP method to prevent a reduction in the margin between adjacent grooves. Therefore, it is possible to reduce short-circuit defects between wirings and stabilize electrical characteristics.

  The present invention also includes a step of forming a via hole adjacent to the insulating film using a resist mask, a step of applying a resist so as to fill the via hole, and a step of forming a resist plug below the tapered shape. Removing the tapered shape formed on the upper portion of the via hole; forming a groove adjacent to the upper portion of the via hole using a resist mask; removing the tapered shape formed on the upper portion of the adjacent groove; And a step of filling the groove with a conductive film to form a wiring.

  Thus, a groove is formed in the upper portion of the via hole while leaving the resist plug formed so as to fill the via hole from the bottom of the via to the lower end of the shoulder drop portion at most. Accordingly, the presence of the resist plug in the via hole makes it possible to prevent the slurry used when the shoulder drop portion is scraped off by the CMP method from entering the groove and collecting the slurry.

  In addition, since only the insulating film protruding from the resist plug is removed by CMP, polishing can be performed more uniformly than when two or more kinds of materials are removed, and a good groove can be formed.

  In addition, by forming a resist plug in the via hole, the resist plug can prevent damage to the protective film due to etching used in the subsequent step of forming a groove. Furthermore, by preventing damage to the protective film, it is possible to prevent the lower layer wiring formed under the protective film from being etched. Thus, it is not necessary to remove the resist plug and apply a resist for protecting the protective film again, so that the steps of removing the resist and applying the resist can be reduced.

  The present invention also includes a step of forming a via hole adjacent to an insulating film using a resist mask, a step of applying a resist so as to fill the via hole, a step of exposing the resist, and a resist plug below the tapered shape. A step of forming, a step of removing a tapered shape formed on the upper portion of the adjacent via hole, a step of forming an adjacent groove on the upper portion of the via hole using a resist mask, and a taper formed on the upper portion of the adjacent groove. It is characterized by having a step of removing the shape and a step of filling the groove with a conductive film to form a wiring.

  As described above, after the via hole is formed, a resist is applied in the via, and the resist is subjected to an exposure process, and then the shoulder drop portion is removed by CMP. Therefore, since the resist is changed to alkali-soluble by performing the exposure treatment, the resist and the insulating film can be removed from the upper surface of the insulating film to at least the lower end of the shoulder drop portion using an alkaline slurry. As a result, the resist and insulating film can be polished using a single type of slurry, and the insulating film is flattened more consistently than when the resist and insulating film are polished without exposing the resist. can do.

  Further, since the resist plug is formed in the via hole simultaneously with the planarization of the insulating film, it is possible to prevent the slurry from entering the via when CMP is performed by the resist plug.

  As described above, according to the present invention, the shoulder drop that occurs when forming a via or a trench in a wiring process is removed by using the CMP method, so that a reduction in a margin between wirings can be prevented and a short circuit failure between wirings can be reduced. Can do.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 3 is a cross-sectional view of a main part of the semiconductor device according to the present embodiment.

  As shown in FIG. 3, the semiconductor device according to the present embodiment is insulated from a semiconductor substrate 51 on which an insulating layer 52 is formed, a plurality of lower layer wirings 53 formed on the semiconductor substrate 51, and a plurality of lower layer wirings 53. A protective film 54 formed on the layer 52, an insulating film 55 made of a low dielectric constant insulating film formed on the protective film 54, and the insulating film 55 so as to reach the lower wiring 53. A via hole 56, a barrier film 57 formed so as to cover the inner wall of the via hole 56, and a metal film 58 embedded in the via hole 56 via the barrier film 57 are configured.

  Below, the manufacturing method of the semiconductor device mentioned above is demonstrated. 4A to 4J are process cross-sectional views of via formation in the present embodiment.

  First, SiCN is deposited on the insulating layer 52 formed on the semiconductor substrate 51 and the lower wiring 53 made of Cu, and SiCO is deposited on the SiCN. Thus, the protective film 54 is formed by depositing a laminated film of SiCN and SiCO on the lower wiring 53 to a thickness of 50 nm. The protective film 54 is a protective film for preventing the lower layer wiring 53 from being damaged by an etching gas or the like during various etching processes in the subsequent processes.

  Here, the SiCN film has good adhesion, and the SiCO film has a poisoning effect.

  In the present embodiment, the lower layer wiring 53 may be configured using Al or an Al alloy.

  In the present embodiment, the protective film 54 is not limited to a laminated film made of SiCN and SiCO, but may be a single layer film made of SiN or SiC.

  Thereafter, TEOS having a thickness of 150 nm to 250 nm is deposited on the protective film 54 by CVD, and SiOC having a thickness of 200 nm to 300 nm is further deposited on the TEOS film. As a result, a laminated insulating film 55 composed of the TEOS film and the SiOC film is formed.

  In the present embodiment, the insulating film 55 is not limited to the TEOS film and the SiOC film, but may be formed of an insulating film having a low dielectric constant. For example, it may be composed of a single layer film made of SiOC. When an insulating film having a low dielectric constant is used, parasitic capacitance between wirings can be reduced, and deterioration in performance of the semiconductor device can be reduced.

  Next, a resist is applied to the entire surface of the insulating film 55, and a resist mask for forming a via hole having an opening above the lower layer wiring 53 is formed on the insulating film 55 by photolithography as shown in FIG. 4A. 59 is formed. Here, the resist material used is, for example, a resist for ArF excimer laser, and is composed of a substance that does not contain a benzene ring.

  Next, as shown in FIG. 4B, using the resist mask 59 as a mask, the insulating film 55 is etched until the surface of the protective film 54 is exposed, and a via hole 56 is formed. At this time, since the resist has insufficient resistance to plasma and etching resistance is not good, the resist as a mask is partially removed by etching. In addition, the insulating film 55 is also removed along with the reduction of the mask, and the insulating film 55 above the via hole 56 is removed to form a tapered via hole 56. That is, as shown in FIG. 4B, the opening diameter of the via hole 56 is widened, and the shoulder dropping portion X is formed.

  Next, as shown in FIG. 4C, the resist mask 59 is removed by ashing. Note that the ashing step shown in FIG. 4C may be omitted. This is because, in the subsequent process, a resist is applied over the entire surface of the insulating film 55 so as to fill the via hole 56. Therefore, the resist of the same kind as before is applied without removing the resist mask 59. This is because the ashing process can be reduced.

  Subsequently, as shown in FIG. 4D, a resist 60 is applied over the entire insulating film 55 so as to fill the via hole 56, and as shown in FIG. By adjusting the etching time in the gas, the resist 60 is left to the vicinity of the lower end of the shoulder drop portion X to form a resist plug 61. That is, the resist on the insulating film 55 is removed.

  It should be noted that the upper surface of the resist plug 61 may be located below the lower end of the shoulder drop portion X so that the surface of the protective film 54 is not exposed. That is, the protective film 54 may be covered with the resist plug 61.

  Next, as shown in FIG. 4F, by removing the insulating film 55 protruding from the via hole 56 and above the lower end of the shoulder dropping portion X, the shoulder dropping portion X is removed and insulated. The upper surface of the film 55 is planarized. In this manner, by removing the shoulder drop portion X, the spread of the opening of the via hole 56 is removed, so that adjacent vias can be prevented from approaching and the vias can be separated. Therefore, occurrence of a short circuit between vias can be reduced. At this time, since the resist plug 61 is formed in the via hole 56, it is possible to prevent the slurry used at the time of CMP from accumulating at the bottom of the via when the shoulder drop portion X is removed by CMP. In the present embodiment, the means for removing the shoulder drop portion X is not limited to the CMP method, and any other known technique can be used as long as the insulating film can be removed.

  Thereafter, as shown in FIG. 4G, the resist plug 61 is removed by ashing, and a well-shaped via hole 56 is formed.

  Subsequently, as shown in FIG. 4H, the protective film 54 exposed at the bottom of the via hole 56 is removed by etching for bonding the lower wiring 53 and the metal film 58. At this time, since the etching is performed over the entire surface of the semiconductor substrate 51, the surface layer of the insulating film 55 whose crystal structure has changed due to the reaction between the slurry used when removing the shoulder drop X and the insulating film 55 is etched. The protective film 54 can be removed at the same time. Therefore, an increase in the dielectric constant of the insulating film 55 caused by a change in the structure of the insulating film 55 can be reduced.

  Note that the protective film 54 protecting the lower wiring 53 may be removed simultaneously with the etching of the insulating film 55 shown in FIG. In this way, since the via hole 56 can be formed and the protective film 54 can be removed at a time, the removal process of the protective film 54 can be reduced.

  Next, the inner wall of the via hole 56 is covered, TaN is deposited to a thickness of 10 nm to 15 nm so as not to completely fill the via hole 56, and Ta is deposited to a thickness of 10 nm to 15 nm on the TaN film. 57 is formed. The Ta film prevents the metal film 58 formed later from diffusing into the insulating film 55, and the TaN film can improve the adhesion with the insulating film 55. Further, as shown in FIG. 4I, a metal film 58 made of Cu is formed so as to fill the via hole 56 by sputtering.

  Thereafter, the barrier film 57 and the metal film 58 are polished by CMP until the upper surface of the insulating film 55 is exposed. As shown in FIG. 4J, the barrier film 57 that is a conductive film only in the via hole 56. And the metal film 58 remain. Thereby, a via connected to the lower layer wiring 53 is formed.

  Here, when the distance between adjacent vias, that is, as shown in FIG. 4 (j), the distance between the peripheral edge m of one via and the peripheral edge n of the other via is 90 nm or less, By removing the drop portion, it is possible to effectively prevent a short-circuit failure between vias. Further, the same effect can be obtained even when the distance between vias is not limited to 90 nm or less and the distance between vias is 130 nm, such as a distance that can cause a short circuit between wirings. In addition, by removing the shoulder drop portion between vias having a minimum line width that is formed for burn-in testing, it is possible to perform a burn-in test by preventing short-circuit defects that are likely to occur due to the minimum line width. .

  At this time, the shoulder drop X that has already occurred at the time of forming the via hole in the step of FIG. 4F has been removed, and the upper surface of the insulating film 55 is planarized before the formation of the conductive film. Therefore, when the conductive film is buried in the via hole 56 to complete the wiring, only the conductive film protruding from the surface of the insulating film 55 may be removed by the CMP method. Therefore, it is not necessary to polish different material films, and wiring can be formed without variation in flatness between wirings. Further, since the insulating film 55 has already been planarized, it is only necessary to polish the metal that is the conductive film, so that a slurry that reacts with the metal can be used. Therefore, the barrier film 57 and the metal film 58 can be polished using the same slurry. Furthermore, as compared with the case where the metal and the insulating film are polished using a slurry having a large abrasive grain, it is only necessary to polish the metal, so a slurry having a small abrasive grain can be used, and it can be polished more chemically. The occurrence of mechanical damage such as scratches can be reduced.

  In the present embodiment, the protective film 54 that protects the lower wiring 53 is not necessary. In this case, any material may be used as long as the lower layer wiring 53 is difficult to diffuse into the insulating film 55.

  Further, in the present invention, as in the case of the via described in the present embodiment, not only when the bottom of the via reaches the lower layer wiring, but also when the metal is buried in a simple groove that is not connected to the lower layer wiring. An effect is obtained. That is, since the taper shape of the groove opening is removed, it is possible to prevent a margin between adjacent wirings from being reduced and to reduce the occurrence of a short circuit between the wirings.

(Embodiment 2)
A second embodiment of the present invention will be described with reference to FIG. A difference of the present embodiment from the first embodiment is that after removing the resist mask 59 for forming the via hole by ashing, the shoulder drop portion X is removed by CMP without applying the resist. This will be described in detail below. However, common points with the first embodiment are omitted.

  First, as shown in FIG. 4A, a via hole 56 is formed as shown in FIG. 4B by using a resist mask 59 for forming a via hole.

  Subsequently, as shown in FIG. 4C, after removing the resist mask 59, as shown in FIG. 4G, from the upper surface of the insulating film 55 to at least the lower end of the shoulder drop portion X by CMP. The insulating film 55 is scraped off.

  Thereafter, as shown in FIG. 4H, the protective film 54 is removed, and as shown in FIG. 4I, a barrier film 57 and a metal film 58, which are conductive films, are formed. Subsequently, as shown in FIG. 4J, vias are formed by removing the barrier film 57 and the metal film 58 protruding from the via hole 56 by CMP.

  As described above, since the shoulder drop portion X is immediately removed by CMP after the shoulder drop portion X is formed in the opening of the via hole 56, the via hole shown in FIG. It is possible to reduce the step of applying a resist inside 56, the step of forming a resist plug shown in FIGS. 4 (e) and 4 (f), and the ashing step after removing the shoulder drop portion X. .

(Embodiment 3)
Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 5 is a fragmentary cross-sectional view of the semiconductor device according to the present embodiment. As shown in FIG. 5, the present embodiment is different from the first embodiment in that a trench 62 communicating with the via hole 56 is provided above the via hole 56, and a conductive film is formed inside the via hole 56 and the trench 62. That is, the barrier film 57 and the metal film 58 are embedded. The common points with Embodiment 1 are omitted.

  A method for manufacturing a semiconductor device using the dual damascene method in the present embodiment will be described below. 6A to 6J are process cross-sectional views of trench formation in the present embodiment. Since the via hole is formed by the same method as in the first embodiment, the description is omitted. Also, the same components as those in FIG.

  First, after the via hole shown in FIG. 4G is formed, a resist is applied over the entire surface of the insulating film 55 so as to fill the via hole 56. Thereafter, as shown in FIG. 6A, a resist mask 63 for forming a trench having an opening diameter larger than that of the via hole 56 is formed by photolithography. At this time, simultaneously with the formation of the resist mask 63, the resist is left in the via hole 56 to a desired depth to form a resist plug 64 that protects the protective film 54.

  In addition, the resist is applied over the entire surface of the insulating film 55 in the state of FIG. 4F in which the resist plug 61 remains in the via hole 56, not after FIG. After that, the resist mask 63 and the resist plug 64 may be formed. In this case, the ashing process shown in FIG. 4G can be reduced, and the resist plug 61 can be used as a resist plug for protecting the protective film 54 from etching during trench formation.

  Next, as shown in FIG. 6B, using the resist mask 63 as a resist mask for trench formation, the insulating film 55 is etched to a desired depth so that the surface of the protective film 54 is not exposed.

  Thereafter, as shown in FIG. 6C, the resist is removed by ashing, and a trench 62 communicating with the via hole 56 is formed. At this time, since the resist does not have sufficient etching resistance, the resist as a mask is partially removed by etching. Further, as the mask is reduced, the insulating film 55 is also partially removed, and the insulating film 55 above the trench 62 is removed to form a tapered trench 62. That is, the upper opening of the trench 62 is expanded, and the shoulder drop portion Y is formed.

  Note that the ashing step shown in FIG. 6C may be omitted. This is because, in the subsequent process, since the resist is applied over the entire surface of the insulating film 55 so as to fill the trench 62, even if the resist is applied without removing the resist mask 63, the resist is applied in the subsequent process. This is because the resist can be removed. Therefore, the ashing process for removing the resist mask 63 can be reduced.

  Subsequently, as shown in FIG. 6D, a resist 65 is applied over the entire insulating film 55 so as to fill the via hole 56 and the trench 62, and as shown in FIG. Thus, the resist plug 66 is formed by leaving the resist to the vicinity of the lower end of the shoulder drop portion Y. That is, the resist on the upper surface of the insulating film 55 is removed.

  Next, as shown in FIG. 6F, the insulating film 55 protruding from the trench 62 and above the lower end of the shoulder drop Y is removed by the CMP method, and the shoulder drop Y is removed to remove the insulation film 55. Flatten the top surface. Thus, by removing the shoulder drop portion Y, the spread of the opening of the trench 62 is removed, so that the adjacent trenches 62 can be prevented from approaching and the trenches can be separated. At this time, since the resist plug 66 is formed in the trench 62, when the shoulder drop portion Y is scraped off by CMP, it is possible to prevent the slurry used at the time of CMP from accumulating at the bottom of the via.

  Thereafter, as shown in FIG. 6G, the resist plug 66 is removed by ashing to form a trench 62 having a good shape.

  Subsequently, as shown in FIG. 6H, the protective film 54 exposed at the bottom of the via hole 56 is removed by etching for bonding the lower layer wiring 53 and the metal film 58.

  Next, a barrier film 57 is formed so as to cover the inner wall of the via hole 56. Further, as shown in FIG. 6I, a metal film 58 made of Cu is formed so as to fill the via hole 56 by sputtering.

  Thereafter, the barrier film 57 and the metal film 58 protruding from the via hole 56 and the trench 62 are removed by CMP until the upper surface of the insulating film 55 is exposed. As shown in FIG. The barrier film 57 and the metal film 58 are left in 62. Thereby, an upper layer wiring connected to the lower layer wiring 53 through the via is formed.

  Here, as shown in FIG. 6 (j), the distance between the wirings between adjacent trenches, that is, the distance between the peripheral portion o of one trench and the peripheral portion p of the other trench is 90 nm or less. In some cases, short-circuit defects between wirings can be effectively prevented by removing the shoulder drop portions. Further, the same effect can be obtained even when the distance between the wirings is not limited to 90 nm or less and the distance between the wirings is 130 nm.

  In the present invention, the same effect can be obtained even if the trench 62 is formed without performing the step of removing the shoulder drop portion X formed in the upper portion of the via hole 56. This will be described in detail below with reference to FIGS. FIG. 7 is a cross-sectional view of a main part of trench formation when a resist mask and a resist plug for trench formation are used.

  In this case, using a resist mask 59 for forming a via hole, a via hole 56 is formed as shown in FIG. 4B, and after removing the resist mask 59 as shown in FIG. As shown in d), a resist 60 is applied over the entire insulating film 55 so as to fill the via hole 56.

  Thereafter, as shown in FIG. 7A, a resist mask 63 for forming trenches and a resist plug 64 are formed, and the insulating film 55 is etched.

  As a result, as shown in FIG. 7B, the shoulder drop portion X generated at the upper portion of the via hole 56 can be removed together with the removal of the insulating film 55 by the formation of the trench 62. Therefore, since the shoulder drop X generated in the via hole 56 can be removed simultaneously with the formation of the trench 62, a resist is applied to the via hole 56, a resist plug is formed by an etch back method, and then the shoulder drop X is removed. Processes can be reduced.

  By removing the shoulder drop portion as described above, occurrence of a short circuit between adjacent wirings can be reduced, so that a dual damascene method having a good wiring shape can be realized.

(Embodiment 4)
An embodiment of the present invention will be described with reference to FIG. The difference from the third embodiment of the present embodiment is that a step of removing the shoulder drop portion Y without applying a resist is provided after the step of removing the resist mask 63 for trench formation. This will be described in detail below. However, common points with Embodiment 3 are omitted.

  After forming the trench 62 using the resist mask 63 for forming the trench as shown in FIG. 6B, the resist mask 63 is removed by ashing as shown in FIG. 6C.

  Subsequently, the insulating film 55 is scraped by the CMP method from the upper surface of the insulating film 55 to the lower end of the shoulder drop portion Y generated above the trench 62.

  Thereafter, as shown in FIG. 6H, the protective film 54 is removed, and as shown in FIG. 6I, a barrier film 57 and a metal film 58 are formed. Subsequently, as shown in FIG. 6J, the barrier film 57 and the metal film 58 protruding from the trench 62 are removed by CMP to form a wiring.

  As described above, since the shoulder drop portion Y is removed by CMP immediately after the shoulder drop portion Y is formed in the opening portion of the trench 62, a resist is formed inside the via hole 56 and the trench 62 as compared with the third embodiment. The step of applying 65, the step of forming the resist plug 66 by the etch back method, and the ashing step after removing the shoulder drop portion Y can be reduced.

(Embodiment 5)
An embodiment of the present invention will be described with reference to FIGS. The difference between the first embodiment and the third embodiment is that the resist 65 and the shoulder drop portion Y are formed by performing an exposure process on the resist instead of performing the CMP process after forming the resist plug by the etch back method. At the same time, it is scraped off by the CMP method. A common point with Embodiment 1 and Embodiment 3 is abbreviate | omitted.

  Below, the manufacturing method of the semiconductor device in this embodiment is demonstrated. 8A to 8C are process cross-sectional views of trench formation in the present embodiment. The same components as those in FIG.

  First, a trench formation resist mask 63 is used to form a trench 62 as shown in FIG. 6B, and after removing the resist mask 63 as shown in FIG. 6C, FIG. ), A resist 65 is applied over the entire insulating film 55 so as to fill the trench 62.

  Thereafter, as shown in FIG. 8A, the entire surface of the semiconductor substrate 51 is irradiated with the exposure light R, thereby rendering the resist 65 alkali-soluble. At this time, it is desirable that the exposure amount is an exposure amount that can be exposed to the vicinity of the lower end of the shoulder drop portion Y. That is, the exposure amount is adjusted so as not to reach the resist in the trench.

  Here, the resist 65 is made of an alkali-insoluble positive resist material. For example, 2-diazo-1-naphthol-5-sulfonic acid ester (o-naphthoquinonediazide compound). When such a positive resist material is irradiated with light, it changes from alkali-insoluble to alkali-soluble.

  Next, as shown in FIG. 8B, the upper surface of the insulating film 55 is planarized by removing the resist 65 and the insulating film 55 at the shoulder drop portion Y at a time by CMP.

  At this time, in the exposure step shown in FIG. 8A, the resist 65 is changed to have alkali solubility by exposing the entire surface of the resist 65. Therefore, by using an alkaline slurry, the alkali-soluble slurry is used. The resist 65 can be removed by CMP by reacting the resist 65 with the slurry. Therefore, the resist 65 can be removed by CMP instead of the step of removing the resist 65 by the etch back performed in the third embodiment.

  In the etch-back method, the etching time from the surface is controlled by controlling the etching time. Therefore, when the surface is not flattened with respect to the substrate at the start of etching, it is difficult to obtain high flatness by controlling variation between patterns by an etch back method.

  However, according to the present embodiment, since the resist can be removed by CMP for controlling the polishing amount for the substrate, there is no variation in flatness between patterns, and the shoulder drop portion is easily removed by adjusting the exposure amount. be able to.

  Next, as shown in FIG. 8C, the resist plug 66 is removed by ashing, and a good trench 62 can be formed.

  The present invention also has the same effect in forming via holes. A brief description will be given below with reference to FIGS. 9A to 9C are cross-sectional views of via formation.

  First, using a resist mask 59 for forming via holes, via holes 56 are formed as shown in FIG. 4B, and after removing the resist mask 59 as shown in FIG. 4C, FIG. ), A resist 60 is applied over the entire insulating film 55 so as to fill the via hole 56.

  Thereafter, as shown in FIG. 9A, the entire surface of the semiconductor substrate 51 is exposed to make the resist 60 alkali-soluble. Then, by the CMP method, the resist 60 and the shoulder drop portion X can be removed at once using an alkaline slurry as shown in FIG. Subsequently, as shown in FIG. 9C, the via hole 56 is formed by removing the resist 60.

  In the via formation when the dual damascene method is used, as shown in FIG. 9B, the resist mask 61 for forming the trench is formed without removing the resist plug 61 formed by removing the shoulder drop X. The trench 62 may be formed on the via hole 56 using the above. In this way, the resist plug 61 can be used as a resist plug for protecting the protective film 54 from trench etching. Therefore, it is not necessary to form a resist plug for protecting the protective film 54 after the resist plug 61 is removed. That is, the process of removing the resist plug 61 can be reduced.

  The method for manufacturing a semiconductor device according to the present invention is useful for a semiconductor device or the like that prevents a short circuit between wirings.

Cross-sectional view of wiring formation process in a conventional semiconductor device Cross-sectional process diagram of via and trench formation in a conventional semiconductor device Sectional drawing of the principal part of the semiconductor device in Embodiment 1 of this invention Sectional drawing of process of via formation of semiconductor device in Embodiment 1 of the present invention Sectional drawing of the principal part of the semiconductor device in Embodiment 3 of this invention Process sectional drawing of the trench formation of the semiconductor device in Embodiment 3 of this invention Sectional drawing of the principal part of the improved manufacturing method of Embodiment 3 of this invention Process sectional drawing of the trench formation of the semiconductor device in Embodiment 5 of this invention Process sectional drawing of the via formation of the semiconductor device in Embodiment 5 of this invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating layer 3 Lower layer wiring 4 Protective film 5 Interlayer insulating film 6 Via formation resist mask 7 Via hole 8 Resist 9 Trench formation resist mask 10 Resist plug 11 Trench 12 Barrier film 13 Metal film A, A 'Shoulder drop part 51 Semiconductor substrate 52 Insulating layer 53 Lower layer wiring 54 Protective film 55 Insulating film 56 Via hole 57 Barrier film 58 Metal film 59 Resist mask 60 Resist 61 Resist plug 62 Trench 63 Resist mask 64 Resist plug 65 Resist 66 Resist plug X, Y Shoulder drop m, n, o, p

Claims (15)

Forming a groove adjacent to the insulating film using a resist mask (a);
Removing the tapered shape formed in the upper part of the adjacent groove (b);
A step (c) of filling the groove with a conductive film to form a wiring;
A method for manufacturing a semiconductor device comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the groove is formed in an upper portion of a via hole formed in the insulating film. The insulating film is on a lower layer wiring, and at least one of the grooves is formed to communicate with the lower layer wiring.
A method for manufacturing a semiconductor memory device according to claim 1. Under the insulating film, there is a protective film on the lower layer wiring,
Between the step (b) and the step (c),
The method of manufacturing a semiconductor device according to claim 3, further comprising a step (d) of removing the protective film on the groove bottom. Between the step (a) and the step (b),
Forming a resist plug below the tapered shape (e),
Between the step (b) and the step (c),
The method for manufacturing a semiconductor device according to claim 1, further comprising a step (f) of removing the resist plug. Between the step (a) and the step (b),
Applying a resist so as to fill the groove (g);
Exposure to the resist (h),
Between the step (b) and the step (c),
The method of manufacturing a semiconductor device according to claim 1, further comprising a step (i) of removing the resist in the groove. The via hole is
Forming the via hole adjacent to the insulating film using a resist mask (j);
A step (k) of removing a tapered shape formed on the upper part of the adjacent via hole,
A method for manufacturing a semiconductor device according to claim 2. Between the step (j) and the step (k),
Applying a resist so as to fill the via hole (g);
Forming a resist plug below the tapered shape (e);
The manufacturing method of the semiconductor device as described in any one of Claims 5-7 containing this. Between the step (j) and the step (k),
Applying a resist so as to fill the via hole (g);
Exposing the resist (h);
The manufacturing method of the semiconductor device as described in any one of Claims 5-7 containing this. The resist is
The method for manufacturing a semiconductor device according to claim 1, wherein the method is an ArF laser resist. The insulating film is
The method for manufacturing a semiconductor device according to claim 1, comprising an insulating film having a low dielectric constant. The insulating film is
The method of manufacturing a semiconductor device according to claim 11, comprising SiOC. The conductive film
2. The method of manufacturing a semiconductor device according to claim 1, comprising a multilayer film including a barrier film. The barrier film is
14. The method of manufacturing a semiconductor device according to claim 13, comprising TaN and Ta. The protective film is
5. The method of manufacturing a semiconductor device according to claim 4, comprising SiCO and SiCN.