JPH10178068A - Substrate for connecting semiconductor integrated circuit, and part and semiconductor device for constituting the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reflow resistance and thermal cycle property by using an epoxy resin, a thermoplastic resin, and a thermosetting type adhesive containing silica powder as an adhesive composition for constituting an adhesive layer. SOLUTION: In a substrate for connecting semiconductor integrated circuit with at least one layer of each of a wiring substrate layer 4 that consists of an insulator layer 3 and a conductor pattern, a layer 7 where no conductor patterns are formed, and an adhesive layer 6, an adhesive composition for constituting the adhesive layer 6 is an epoxy resin, a thermoplastic resin, and a thermosetting adhesive containing silica powder. Any epoxy resin with at least two epoxy groups in one molecule may be used. A copolymer with butadiene as an essential copolymerization constituent is preferable for the thermoplastic resin in terms of adhesion property, flexibility, and thermal stress relaxation property. The silica powder is not limited particularly in terms of grain diameter, crystallizablity, and shape but a melted silica that has a large reduction effect of thermal coefficient of expansion and is effective for reducing stress is preferable.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate (interposer) for connecting a semiconductor integrated circuit (IC) for mounting and packaging the semiconductor integrated circuit, a component constituting the substrate, and a semiconductor device. More specifically, a wiring board layer composed of an insulating layer and a conductor pattern constituting a substrate for connecting a semiconductor integrated circuit used in a ball grid array (BGA) and land grid array (LGA) type surface mounting package, and a metal reinforcing plate, for example. (Stiffeners, heat spreaders) for connecting semiconductor integrated circuits with a structure in which layers without conductor patterns are bonded and laminated with an adhesive composition having excellent reliability such as solder heat resistance and thermal cycling properties. The present invention relates to a substrate and a semiconductor device using the same.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor integrated circuit (IC) package, a dual in-line package (DIP),
Package forms such as a small outline package (SOP) and a quad flat package (QFP) have been used. However, with the increase in the number of pins of the IC and the miniaturization of the package, the limit of the QFP having the largest number of pins is approaching its limit. This is due to the difficulty in handling due to the narrow pitch between external terminals (leads) and the difficulty in obtaining solder printing accuracy on the printed board, particularly when mounting on a printed board. Therefore, in recent years, a BGA method, an LGA method, a PGA method and the like have been put to practical use as means for increasing the number of pins and reducing the size. Above all, the BGA method has attracted a great deal of attention not only because it can be reduced in cost, weight and thickness by using a plastic material, but also because it can be surface-mounted.

FIG. 1 shows an example of the BGA system. The BGA method is characterized in that solder balls almost corresponding to the number of pins of an IC are provided in a grid (area array) as external connection terminals of a semiconductor integrated circuit connection board to which the IC is connected.
The connection to the printed board is performed by batch reflow in which the solder ball surface is placed so as to match the conductor pattern of the printed board on which the solder is already printed, and the solder is melted by reflow. The feature of the package is that the connection terminals are arranged on the back surface of the package, compared to the conventional IC package in which the connection terminals are arranged around the QFP.
The reason is that more connection terminals can be arranged in a small space at a wide interval. For this reason, on the mounting surface, it is possible to reduce the mounting area and increase the mounting efficiency.

[0004] A chip scale package (CSP) is one that has further advanced this function, and is called a micro BGA because of its similarity. The present invention relates to these BGs.
The present invention can be applied to a CSP having an A structure.

On the other hand, the BGA package has the following problems. (A) Flatness of the solder ball surface, (b) reflow resistance, (c) heat dissipation, and (c) thermal cycle properties.

As a method of improving these, a method of laminating a material such as a metal plate for reinforcement (maintaining flatness), heat radiation, and electromagnetic shielding on a substrate for connecting a semiconductor integrated circuit is generally used. . In particular, it becomes important when a TAB tape or a flexible substrate is used for a wiring board layer composed of an insulating layer and a conductor pattern for connecting an IC.

Therefore, the substrate for connecting a semiconductor integrated circuit is
As illustrated in FIG. 2, a wiring board layer including an insulator layer 11 and a conductor pattern 13 for connecting an IC, a reinforcing plate (stiffener), a heat sink (heat spreader),
Layer 1 on which no conductor pattern such as a shield plate is formed
5, and at least one adhesive layer 14 for laminating them. For these semiconductor integrated circuit connection substrates, a part as an intermediate product is prepared in advance by laminating or applying and drying the adhesive composition in a semi-cured state on either the wiring substrate layer or the layer where no conductor is formed. It is created by bonding and heat curing in a package assembly process.

Finally, the adhesive layer 14 remains inside the package. From the above points, the properties required for the adhesive layer 14 include (a) reflow resistance, and (b) stress absorption occurring between different materials such as a wiring board layer and a reinforcing plate during a temperature cycle or reflow. Low stress), (c) easy workability,
(D) Insulation when laminated on wirings, and the like.

Among them, important requirements are reflow resistance and thermal cycle resistance.

[0010] The reflow resistance is determined by a mounting method in which the entire package is heated to a high temperature of 210 to 270 ° C, such as immersion in a solder bath, heating with a saturated vapor of an inert gas (a vapor phase method), or infrared reflow. It peels off and reduces the reliability of the package. It is said that the peeling in the reflow process is caused by the explosion of water that has been absorbed between the curing of the adhesive layer and the mounting process explosively turning into steam during heating. A method has been used in which a package that has been completely dried and stored in a sealed container is shipped.

The thermal cycle resistance is a characteristic required for a package having a large number of pins, such as a BGA, because the temperature of the package is higher than 100 ° C. during operation. In order to alleviate this, a low elastic modulus is required.

For these reasons, various improvements in adhesives have been studied. For example, as an adhesive layer having excellent thermal cycle resistance, a thermoplastic resin or a silicone elastomer having a low elastic modulus (Japanese Patent Publication No. 6-50448).
And so on.

[0013]

However, the method of enclosing a dry package in a container has disadvantages in that the manufacturing process and the handling of the product are complicated, and the product price is extremely high.

Further, although the adhesives proposed variously have excellent thermal cycle resistance, they do not satisfy the reflow resistance.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems arising in the reflow process, and to provide a semiconductor integrated circuit connection substrate having high reliability, excellent reflow resistance, and excellent thermal cycling properties, components constituting the same, and a semiconductor device. Is to provide.

[0016]

That is, the present invention relates to a semiconductor integrated circuit connection having at least one wiring board layer comprising an insulator layer and a conductor pattern, at least one layer having no conductor pattern, and at least one adhesive layer. A substrate, wherein the adhesive composition constituting the adhesive layer is a thermosetting adhesive containing an epoxy resin (A), a thermoplastic resin (B) and a silica powder (C). And a component constituting the same and a semiconductor device.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the present invention will be described below in detail.

The substrate for connecting a semiconductor integrated circuit in the present invention is for connecting a semiconductor element, and includes a wiring board layer composed of an insulator layer and a conductor pattern, a layer on which no conductor pattern is formed, and an adhesive layer. The shape, material, and manufacturing method are not particularly limited as long as it has at least one layer. Therefore, the most basic one is 3
Although it has a layer structure, a multi-layer structure of more layers is also included in this.

The wiring board layer is a layer having a conductor pattern for connecting the electrode pads of the semiconductor element and the outside of the package (such as a printed board), and has a conductor pattern formed on one or both sides of the insulator layer. Things.

The insulator layer referred to here is made of a plastic such as polyimide, polyester, polyphenylene sulfide, polyether sulfone, polyether ether ketone, aramid, polycarbonate, polyarylate or a composite material such as epoxy resin impregnated glass cloth. A flexible insulating film having a thickness of 10 to 125 μm, a ceramic substrate made of alumina, zirconia, soda glass, quartz glass, or the like is suitable, and a plurality of layers selected therefrom may be used by lamination. If necessary, hydrolysis, corona discharge, low-temperature plasma,
Surface treatment such as physical roughening and easy adhesion coating treatment can be performed.

The formation of the conductor pattern is generally performed by either the subtractive method or the additive method, but any of them may be used in the present invention.

In the subtractive method, a metal plate such as a copper foil is bonded to the insulator layer with an insulating adhesive, or a precursor of the insulator layer is laminated on the metal plate, and the insulator layer is formed by heat treatment or the like. A pattern is formed by etching the material prepared by the forming method by chemical treatment. Specific examples of the material include a rigid or flexible printed circuit board copper bonding material and a TAB tape. Among them, a copper paste material for flexible printed circuit boards or a TAB tape using at least one or more polyimide films as an insulator layer and a copper foil as a conductor pattern is preferably used.

In the additive method, a conductor pattern is directly formed on an insulator layer by electroless plating, electrolytic plating, sputtering, or the like.

In any case, the formed conductor may be plated with a metal having high corrosion resistance to prevent corrosion.
Also, via holes may be formed in the wiring board layer as necessary, and conductive patterns formed on both sides may be connected by plating.

The layer on which the conductor pattern is not formed is used to reinforce the substrate for connecting the semiconductor integrated circuit and stabilize the dimensions (referred to as a reinforcing plate or a stiffener), to provide electromagnetic shielding between the outside and the IC, and to radiate the IC (heat). The substrate has functions such as imparting flame retardancy to the semiconductor integrated circuit connection substrate and imparting discriminability based on the shape of the semiconductor integrated circuit connection substrate. Accordingly, the shape may be not only a layer shape but also a fin structure for heat dissipation, for example. Any insulator or conductor as long as it has the above functions may be used.
The material is not particularly limited. Metals include copper, iron, aluminum, gold, silver, nickel, titanium, and the like; inorganic materials include alumina, zirconia, soda glass, quartz glass, and carbon; and organic materials include polyimide, polyamide, polyester, and vinyl. System, phenol system,
A polymer material such as an epoxy-based material may be used. Further, a composite material obtained by combining these can also be used. For example,
Examples include a shape in which thin metal plating is performed on a polyimide film, a material in which carbon is kneaded into a polymer to impart conductivity, and a metal plate in which an organic insulating polymer is coated. In addition, if necessary, hydrolysis, corona discharge, low-temperature plasma, physical roughening,
Surface treatment such as easy adhesion coating treatment can be performed.

It is important that the adhesive layer in the present invention is a thermosetting adhesive containing an epoxy resin (A), a thermoplastic resin (B) and a silica powder (C).

The epoxy resin (A) contained in the adhesive layer of the present invention is not particularly limited as long as it has two or more epoxy groups in one molecule, and specific examples thereof include cresol novolac type. Epoxy resin, phenol novolak type epoxy resin, the following formulas (I) and (II),
Epoxy resins represented by (III), (IV) and (V),

Embedded image (Wherein, R ₁ to R ₁₀ each show a hydrogen atom, C1 -C4 lower alkyl group or a halogen atom.)

Embedded image (However, R _{1 to} R ₈ each represent a hydrogen atom, a C1 to C4 lower alkyl group or a halogen atom.)

Embedded image (However, two of R _{1 to} R ₈ are 2,3-epoxypropoxy groups, and the rest each represent a hydrogen atom, a C1 to C4 lower alkyl group or a halogen atom.)

Embedded image (Wherein, R ₁ to R ₄ each show a hydrogen atom, C1 -C4 lower alkyl group or a halogen atom.)

Embedded image (However, R _{1 to} R ₄ each represent a hydrogen atom, a C1 to C4 lower alkyl group or a halogen atom.) Linear aliphatic epoxy resin, alicyclic epoxy resin, heterocyclic epoxy resin, spiro ring-containing epoxy Resins and halogenated epoxy resins.

Among these epoxy resins (A), those which are preferably used in the present invention are those having the above formulas (I), (II) and (II), which have high adhesion and excellent electrical properties and reflow resistance.
An epoxy resin represented by (III), (IV) or (V). And, the epoxy resin (A) is prepared by using the above formula (I), (II), (III), (IV) or (V)
The epoxy resin (A) preferably contains at least one of the epoxy resins represented by the formula (1) in an amount of 20% by weight or more, more preferably 50% by weight or more.

In the epoxy resin represented by the above formula (I), preferred examples of R _{1 to} R ₁₀ include a hydrogen atom, a methyl group, an ethyl group, a sec-butyl group, a t-butyl group, a chlorine atom, a bromine atom. Atoms. Preferred specific examples of the epoxy resin represented by the above formula (I) include bisphenol A epoxy resin, bisphenol F epoxy resin, brominated bisphenol A epoxy resin, and brominated bisphenol F epoxy resin.

In the epoxy resin represented by the formula (II), preferred examples of R _{1 to} R ₈ include a hydrogen atom, a methyl group, an ethyl group, a sec-butyl group, a t-butyl group, a chlorine atom, and a bromine. Atoms. Preferred specific examples of the epoxy resin represented by the above formula (II) include 4,4′-bis (2,3-epoxypropoxy).
Biphenyl, 4,4'-bis (2,3-epoxypropoxy) -3,3 ', 5,5'-tetramethylbiphenyl, 4,4'-bis (2,3-epoxypropoxy) -3,3' , 5,5'-Tetramethyl-2-chlorobiphenyl, 4,4'-bis (2,3-epoxypropoxy)
-3,3 ', 5,5'-tetramethyl-2-bromobiphenyl, 4,4'-bis (2,3-epoxypropoxy) -3,3', 5,5'-tetraethylbiphenyl,
4,4′-bis (2,3-epoxypropoxy) -3,
3 ', 5,5'-tetrabutylbiphenyl and the like.

In the epoxy resin represented by the formula (III), preferred examples of R _{1 to} R ₈ include a hydrogen atom, a methyl group, an ethyl group, a sec-butyl group, a t-butyl group, a chlorine atom, And a bromine atom. Preferred specific examples of the epoxy resin represented by the above formula (III) include 1,5-bis (2,3-epoxypropoxy)
Naphthalene, 1,5-bis (2,3-epoxypropoxy) -7-methylnaphthalene, 1,6-bis (2,3-
Epoxypropoxy) naphthalene, 1,6-bis (2,
3-epoxypropoxy) -2-methylnaphthalene,
1,6-bis (2,3-epoxypropoxy) -8-methylnaphthalene, 1,6-bis (2,3-epoxypropoxy) -4,8-dimethylnaphthalene, 1,6-bis (2,3- Epoxypropoxy) -2-bromonaphthalene, 1,6-bis (2,3-epoxypropoxy) -8
-Bromonaphthalene and the like.

In the epoxy resin represented by the above formula (IV), preferred examples of R _{1 to} R ₄ include a hydrogen atom, a methyl group, an ethyl group, a sec-butyl group, a t-butyl group, a chlorine atom, And a bromine atom. A preferred specific example of the epoxy resin represented by the above formula (IV) is EXA-7200 (Dainippon Ink Chemical Industry Co., Ltd.)
And ZX-1257 (manufactured by Toto Kasei Co., Ltd.).

In the epoxy resin represented by the formula (V), preferred specific examples of R _{1 to} R ₄ include a hydrogen atom,
Examples include a methyl group, an ethyl group, a sec-butyl group, a t-butyl group, a chlorine atom and a bromine atom. Preferred specific examples of the epoxy resin represented by the above formula (V) include terpene diphenol diglycidyl ether (manufactured by Yuka Shell Epoxy Co., Ltd.).

In the present invention, the amount of the epoxy resin (A) is 5 to 90% by weight, preferably 10 to 90% by weight in the adhesive composition.
７０70% by weight, more preferably 20-60% by weight.

The thermoplastic resin (B) contained in the adhesive layer of the present invention is not particularly limited as long as it gives flexibility to the adhesive layer. Specific examples thereof include acrylonitrile-butadiene copolymer. Coal (NBR), acrylonitrile-butadiene rubber-styrene resin (ABS), polybutadiene, styrene-butadiene-ethylene resin (SE
BS), acrylic, polyvinyl butyral, polyamide, polyethylene, polyester, polyimide, polyamideimide, polyurethane and the like. Further, these thermoplastic resins preferably have a functional group capable of reacting with the epoxy resin (A) in order to improve heat resistance. Specific examples include an amino group, a carboxyl group, an epoxy group, a hydroxyl group, a methylol group, an isocyanate group, a vinyl group, and a silanol group.

Among them, a copolymer containing butadiene as an essential copolymer component is preferably used in view of adhesiveness, flexibility and thermal stress relaxation. Particularly, acrylonitrile-butadiene copolymer (N
BR), styrene-butadiene-ethylene resin (SEB)
S), styrene-butadiene resin (SBS) and the like are preferred. Further, a copolymer having butadiene as an essential copolymer component and having a carboxyl group is preferably used, and specific examples thereof include NBR having a carboxyl group (NBR-C).
And SEBS having a carboxyl group (SEBS-
C).

The silica powder (C) contained in the adhesive layer of the present invention is not particularly limited in terms of particle size, crystallinity, shape and the like. Silica (C ') is preferably used.

The fused silica herein means a true specific gravity of 2.3.
The following amorphous silica is meant, and the production of this fused silica does not necessarily have to go through a molten state, and any production method can be used. For example, a method of melting crystalline silica and a method of synthesizing from various raw materials are exemplified.

The average particle size of the silica powder (C) is usually 20 μm or less, preferably 10 μm or less, more preferably 2 μm or less.

Further, the silica powder (C) is preferably a fused silica powder (C ′), and more preferably a spherical fused silica powder (C ″).

The amount of the silica powder (C) is 5 to 80% by weight, preferably 5 to 60% by weight, more preferably 10 to 50% by weight in the adhesive composition.

In the present invention, reflow resistance and insulation reliability can be further improved by adding a phenol resin (D) to the adhesive layer. Specific examples of the phenol resin (D) include, for example, a phenol novolak resin, a cresol novolak resin, a bisphenol A type resin, various resole resins, and the like.

The mixing ratio of the phenol resin is usually 0.5 to 1 phenolic hydroxyl group per equivalent of epoxy resin.
It is desirably in the range of 0.0 equivalent, preferably 0.7 to 7.0 equivalent.

The adhesive layer of the present invention contains a curing accelerator which promotes a single reaction of the epoxy resin (A) or a reaction between the epoxy resin (A) and the thermoplastic resin (B) or the phenol resin (D). Can be. The curing accelerator is not particularly limited as long as it accelerates the curing reaction, and specific examples thereof include:
For example, 2-methylimidazole, 2,4-dimethylimidazole, 2-ethyl-4-methylimidazole,
Imidazole compounds such as 2-phenylimidazole, 2-phenyl-4-methylimidazole and 2-heptadecylimidazole, triethylamine, benzyldimethylamine, α-methylbenzyldimethylamine,
-(Dimethylaminomethyl) phenol, 2,4,6-
Tris (dimethylaminomethyl) phenol and 1,
Tertiary amine compounds such as 8-diazabicyclo (5,4,0) undecene-7, zirconium tetramethoxide,
Organometallic compounds such as zirconium tetrapropoxide, tetrakis (acetylacetonato) zirconium and tri (acetylacetonato) aluminum; and triphenylphosphine, trimethylphosphine, triethylphosphine, tributylphosphine, tri (p-methylphenyl) phosphine and tri Organic phosphine compounds such as (nonylphenyl) phosphine are exemplified.

Two or more of these curing accelerators may be used in combination depending on the use. The amount of the curing accelerator ranges from 0.1 to 10 parts by weight based on 100 parts by weight of the epoxy resin (A). preferable.

The components (hereinafter, referred to as components) of the substrate for connecting a semiconductor integrated circuit of the present invention are materials in an intermediate processing stage used for producing a substrate for connecting a semiconductor integrated circuit and a semiconductor device. The component has a configuration in which at least one or more layers each include a wiring board layer formed of an insulator layer and a conductor pattern and / or a layer on which no conductor pattern is formed, and an adhesive layer having a protective layer. For example, a wiring board with an adhesive in which a flexible printed board or a TAB tape is used as a wiring board layer composed of an insulator layer and a conductor pattern, and a B-stage adhesive layer having a silicone-protected polyester protective film on one or both sides thereof is laminated. Metal plate with an adhesive layer in which a B-stage adhesive layer having a protective film on one side or both sides is used in the same manner as described above, using a metal plate of copper, stainless steel, 42 alloy or the like as a layer on which no conductor pattern is formed. (Stiffener with adhesive, etc.) corresponds to the component of the present invention. A so-called adhesive in which a B-stage adhesive layer having a protective film is laminated on the outermost layer, even when there is at least one wiring board layer composed of an insulator layer and a conductor pattern and at least one layer on which no conductor pattern is formed. A substrate for connecting a semiconductor integrated circuit is also included in the component of the present invention.

The protective layer referred to here is usually composed of a protective film, and is not particularly limited as long as it can be peeled off without impairing its form and function before bonding the adhesive layer. Specific examples thereof include polyester, polyolefin, and the like. Plastic films of polyphenylene sulfide, polyvinyl chloride, polytetrafluoroethylene, polyvinyl fluoride, polyvinyl butyral, polyvinyl acetate, polyvinyl alcohol, polycarbonate, polyamide, polyimide, polymethyl methacrylate, etc. Examples include films coated with a mold agent, paper laminated with these films, and paper impregnated or coated with a releasable resin. The thickness of the protective film is 20 μm or more, preferably 25 μm from the viewpoint of heat resistance.
The thickness is more preferably 35 μm or more.

The peel strength of the protective layer from the adhesive layer is preferably from 1 to 200 N / m, more preferably from 3 to 100 N / m.
N / m. If it is lower than 1 N / m, the protective film tends to fall off, and if it exceeds 200 N / m, peeling becomes difficult, which is not preferable.

The semiconductor device according to the present invention means a device using the substrate for connecting a semiconductor integrated circuit according to the present invention.
The shape and structure are not particularly limited as long as the package is a GA type or LGA type package. Substrate for connecting semiconductor integrated circuit and I
The connection method of C may be any of TAB gang bonding and single point bonding, wire bonding used for a lead frame, resin sealing by flip chip mounting, anisotropic conductive film connection, and the like. Further, a package called a CSP is also included in the semiconductor device of the present invention.

Next, a description will be given of an example of a semiconductor integrated circuit connecting substrate, components constituting the same, and a method of manufacturing a semiconductor device according to the present invention.

(1) Preparation of a wiring board composed of an insulator layer and a conductor pattern: A three-layer TAB tape in which an adhesive layer and a protective layer are laminated on a polyimide film is subjected to the following steps (a) to (d). Processing by (A) perforation of sprocket and device holes; (b) thermal lamination with copper foil; (c) pattern formation (resist coating, etching, resist removal); (d) tin or gold plating.
FIG. 3 illustrates the shape of the obtained TAB tape (pattern tape).

(2) Formation of a layer on which no conductor pattern is formed: A metal plate such as a copper plate or a stainless plate having a thickness of 0.05 to 0.5 mm is degreased with acetone.

(3) Preparation of adhesive layer: A coating solution in which the adhesive composition is dissolved in a solvent is applied to a polyester film having releasability and dried. The thickness of the adhesive layer is 10 to 10
It is preferable to apply so as to have a thickness of 0 μm. Drying conditions are 100 to 200 ° C. for 1 to 5 minutes. Solvents are not particularly limited, but aromatic solvents such as toluene, xylene, and chlorobenzene; ketones such as methyl ethyl ketone and methyl ethyl isobutyl ketone; aprotic polar solvents such as dimethylformamide, dimethylacetamide, and N-methylpyrrolidine alone or as a mixture; Is preferred. An adhesive sheet is obtained by further laminating a polyester or polyolefin-based protective film having a weak release force and releasability on the coated and dried adhesive layer. When the thickness of the adhesive is further increased, the adhesive sheet may be laminated a plurality of times.
The degree of curing may be adjusted by aging at 0 ° C. for about 1 to 200 hours.

(4) Preparation of a component (wiring board with adhesive) of a substrate for connecting a semiconductor integrated circuit: A protective film on one side of the adhesive sheet prepared in (3) is applied to the wiring board layer of (1). Laminate after peeling. The laminate surface may be either a surface with or without a conductor pattern. Laminating temperature 20 ~ 200 ℃, pressure 0.1 ~ 3M
Pa is preferred. Finally, depending on the shape of the semiconductor device,
Punching and cutting are performed as appropriate. FIG. 4 illustrates the component of the present invention.

(5) Preparation of a component (stiffener with adhesive) of the substrate for connecting a semiconductor integrated circuit: after peeling off the protective film on one side of the adhesive sheet prepared in (3) above on the metal plate (2). Laminate. A lamination temperature of 20 to 200 ° C. and a pressure of 0.1 to 3 MPa are preferred.
Alternatively, the coating of (3) may be directly applied to (B) and dried, and a protective film may be laminated. Finally, punching and cutting are performed as appropriate depending on the shape of the semiconductor device. FIG. 5 shows an example of the component of the present invention.

(6) Preparation of Substrate for Connecting Semiconductor Integrated Circuit: (a) Method Using Wiring Board with Adhesive The protective film of the adhesive layer is peeled off from the component (4) (wiring board with adhesive), and an appropriate method is used. Glue to a metal plate punched into shape. As the metal plate, for example, a metal plate having a square shape and punched into a shape having a square hole in accordance with the device hole of the wiring board in the center can be exemplified. The bonding conditions are preferably a temperature of 20 to 200 ° C. and a pressure of 0.1 to 3 MPa. Finally, post-curing is performed in a hot-air oven at 80 to 200 ° C. for about 15 to 180 minutes for heat curing of the adhesive.

(B) Method using a stiffener with an adhesive The component (5) (stiffener with an adhesive) is punched out with a metal mold, and is, for example, a square stiffener with a square hole having a square hole at the center. And The protective film was peeled off from the stiffener with the adhesive, and a hole at the center of the stiffener with the adhesive was formed on the conductor pattern surface of the wiring board layer or the polyimide film on the back surface in the above (1).
It is aligned with the device hole of the wiring board and bonded. The bonding conditions are a temperature of 20 to 200 ° C and a pressure of 0.1 to 3 MPa.
Is preferred. Finally, post-curing is performed in a hot-air oven at 80 to 200 ° C. for about 15 to 180 minutes for heat curing of the adhesive.

FIG. 2 shows an example of the substrate for connecting a semiconductor integrated circuit described above.

(7) Fabrication of a semiconductor device: The inner lead portion of the substrate for connecting a semiconductor integrated circuit of (6) is thermocompression-bonded (inner lead bonding) to a gold bump of the IC, and
With. Next, a semiconductor device is manufactured through a resin sealing step using a sealing resin. The obtained semiconductor device is connected to a printed circuit board or the like on which other components are mounted via solder balls, and mounted on an electronic device. Further, a so-called TCP type semiconductor device in which an IC is connected to the wiring board in the above (1) in advance and sealed with a resin can be used. FIG. 1 is a cross-sectional view of one embodiment of a semiconductor device of the present invention.

[0060]

The present invention will be described more specifically with reference to the following examples.

Examples 1 to 6 and Comparative Examples 1 and 2 The following thermoplastic resins, epoxy resins and other additives were blended so as to have the composition ratios shown in Table 1, respectively.
The mixture was stirred and dissolved in a DMF / monochlorobenzene / MIBK mixed solvent at 40 ° C. so as to have a concentration of 28% by weight to prepare an adhesive solution.

A. Epoxy resin I. Bisphenol A type epoxy resin (epoxy equivalent:
186) II. 4,4'-bis (2,3-epoxypropoxy)
-3,3 ', 5,5'-Tetramethylbiphenyl (epoxy equivalent: 195) C. Thermoplastic resin SEBS-C (MX-073, manufactured by Asahi Kasei Corporation) Silica powder I. Average particle size: crushed fused silica powder of 18 μm II. Average particle size: crushed fused silica powder of 6 μm III. Average particle size: 5 μm spherical fused silica powder IV. A. Average spherical particle diameter: 2 μm spherical fused silica powder Additive 4,4'-diaminodiphenyl sulfone

These adhesive solutions were applied to a 25 μm-thick silicated polyethylene terephthalate film I with a bar coater to a dry thickness of about 50 μm, and dried at 100 ° C., 1 minute and 150 ° C. for 5 minutes. Then, an adhesive sheet was prepared. On the other hand, an adhesive solution was similarly applied to a polyethylene terephthalate film II having a lower peeling force than polyethylene terephthalate I so as to have a thickness of about 50 μm, and then dried. A 100 μm adhesive sheet was prepared. The adhesive strength of this sheet was measured, and the sheet was attached to a semiconductor connection board to produce a component of the semiconductor connection board, and the reflow resistance and thermal cycle resistance were measured. The measuring method was as follows. Table 1 shows the results.

[Adhesion] Polyimide film (75 μm)
m: Ube Industries, Ltd. “UPILEX 75S”)
An adhesive sheet was laminated thereon at 40 ° C. and 1 MPa. Then, 1 μm of SUS304 having a thickness of 25 μm was applied to the surface of the adhesive sheet laminated on the polyimide film.
After further laminating under the conditions of 30 ° C. and 1 MPa, heat treatment was sequentially performed in an air oven at 100 ° C. for 1 hour, 150 ° C. for 1 hour, and an evaluation sample was prepared. After slitting polyimide film to 5mm width, 5mm
50mm / mi in 90 ° direction with polyimide film of width
Peeling was performed at a speed of n, and the adhesive force at that time was measured.

[Reflow Resistance] A 50 μm thick adhesive sheet was formed on a 30 mm square semiconductor connection substrate on which a simulated pattern having a conductor width of 100 μm and a distance between conductors of 100 μm was formed.
After laminating under the conditions of 0 ° C. and 1 MPa, 30 mm × 0.25 mm thick SUS304 was placed on the adhesive sheet for 15 minutes.
Crimping was performed under the conditions of 0 ° C. and 75 MPa. Then 150
The composition was cured at 2 ° C. for 2 hours to prepare a sample for evaluating reflow resistance. 85 ° C / 85 for 30mm □ samples
% RH, and then absorbed for 48 hours. 24
The sample was subjected to an IR reflow at 5 ° C. for 10 seconds, and the peeled state was observed with an ultrasonic short wound machine.

[Thermal cycling property] Ten 30 mm square samples prepared by the same method as the sample for evaluating reflow resistance were subjected to cycle processing under the conditions of -65 ° C to 150 ° C, minimum and maximum temperatures of 30 minutes each. Internal peeling was observed using an ultrasonic flaw detector.

[0067]

[Table 1]

As is clear from the results shown in Table 1, the components of the substrate for connecting a semiconductor integrated circuit obtained by the present invention have high adhesive strength and excellent reflow resistance and thermal cycle properties. On the other hand, Comparative Example 1, in which the component of the substrate for connecting a semiconductor integrated circuit of the present invention was not used, not only has low adhesiveness but also inferior reflow resistance.

[0069]

According to the present invention, it is possible to obtain a thermosetting type connection substrate for a semiconductor integrated circuit having excellent reflow properties and thermal cycling properties, a component constituting the connection board, and a semiconductor device so as to be industrially practical. did it. Further, the reliability of the semiconductor device for surface mounting could be improved.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of one embodiment of a BGA type semiconductor device using a semiconductor device adhesive composition and a semiconductor adhesive sheet used in the present invention.

FIG. 2 is a schematic sectional view of one embodiment of a substrate for connecting a semiconductor integrated circuit before connecting the semiconductor integrated circuit using the adhesive composition for a semiconductor device used in the present invention.

FIG. 3 is a schematic perspective view of one embodiment of a pattern tape (TAB tape) constituting a substrate for connecting a semiconductor integrated circuit.

FIG. 4 is a schematic cross-sectional view of one embodiment of a component (wiring substrate with an adhesive) of a substrate for connecting a semiconductor integrated circuit according to the present invention.

FIG. 5 is a schematic cross-sectional view of one embodiment of a component (a stiffener with an adhesive) of the substrate for connecting a semiconductor integrated circuit of the present invention.

[Explanation of symbols]

1. 1. Semiconductor integrated circuit Gold bumps 3,11,17. Flexible insulating film 4,12,18. Adhesive layer constituting wiring board layer 5, 13, 21. Conductors for connecting semiconductor integrated circuits 6, 14, 23. Adhesive layer composed of adhesive composition of the present invention 7,15. Layer in which no conductor pattern is formed 8,16. Solder resist 9. Solder ball 10. Sealing resin 19. Sprocket hole 20. Device hole 22. Conductor part for solder ball connection 24. Protective film layer constituting the adhesive sheet of the present invention

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI C09J 201/00 C09J 201/00 H01L 23/12 H01L 23/12 L

Claims (23)

[Claims] 1. A semiconductor integrated circuit connecting substrate having at least one or more wiring board layers each including an insulator layer and a conductor pattern, a layer on which no conductor pattern is formed, and an adhesive layer. Wherein the adhesive composition is a thermosetting adhesive containing an epoxy resin (A), a thermoplastic resin (B) and a silica powder (C). 2. The semiconductor integrated circuit connecting substrate according to claim 1, wherein the silica powder (C) has an average particle size of 20 μm or less. 3. The substrate for connecting a semiconductor integrated circuit according to claim 1, wherein the average particle diameter of the silica powder (C) is 10 μm or less. 4. The substrate for connecting a semiconductor integrated circuit according to claim 1, wherein the silica powder (C) has an average particle size of 2 μm or less. 5. The substrate for connecting a semiconductor integrated circuit according to claim 1, wherein the content of the silica powder (C) is 5 to 80% by weight. 6. The semiconductor integrated circuit connection according to claim 1, wherein the silica powder (C) is a fused silica powder (C ′). 7. The substrate for connecting a semiconductor integrated circuit according to claim 6, wherein the silica powder (C) is a spherical fused silica powder (C ″). 8. The substrate for connecting a semiconductor integrated circuit according to claim 1, wherein the thermoplastic resin (B) contains a thermoplastic resin (B ′) containing butadiene as an essential copolymerization component. 9. The substrate for connecting a semiconductor integrated circuit according to claim 1, wherein the thermoplastic resin (B) is a thermoplastic resin (B ″) containing butadiene as an essential copolymer component and having a carboxyl group. . 10. A semiconductor device using the substrate for connecting a semiconductor integrated circuit according to claim 1. 11. A component of a substrate for connecting a semiconductor integrated circuit having at least one adhesive layer having at least one wiring board layer comprising an insulating layer and a conductor pattern and at least one adhesive layer having a protective layer, wherein said adhesive layer is formed. A component for a substrate for connecting a semiconductor integrated circuit, wherein the adhesive composition is a thermosetting adhesive containing an epoxy resin (A), a thermoplastic resin (B) and a silica powder (C). 12. A component of a substrate for connecting a semiconductor integrated circuit having at least one or more adhesive layers each having a layer on which no conductor pattern is formed and a protective layer, wherein the adhesive composition constituting the adhesive layer A component of a substrate for connecting a semiconductor integrated circuit, wherein the object is a thermosetting adhesive containing an epoxy resin (A), a thermoplastic resin (B) and a silica powder (C). 13. The silica powder (C) has an average particle size of 20 μm.
The component of the substrate for connecting a semiconductor integrated circuit according to claim 11, wherein: 14. The maximum particle size of the silica powder (C) is 10 μm.
The component of the substrate for connecting a semiconductor integrated circuit according to claim 11, wherein: 15. The component for a substrate for connecting a semiconductor integrated circuit according to claim 11, wherein the maximum particle size of the silica powder (C) is 2 μm or less. 16. The component for a substrate for connecting a semiconductor integrated circuit according to claim 11, wherein the content of the silica powder (C) is 5 to 80% by weight. 17. The method according to claim 11, wherein the silica powder (C) is a fused silica powder (C ′).
A component for connecting a semiconductor integrated circuit according to the above. 18. The method according to claim 11, wherein the silica powder (C) is a spherical fused silica powder (C ″).
Parts of the substrate for connecting a semiconductor integrated circuit according to the above. 19. The component for a substrate for connecting a semiconductor integrated circuit according to claim 11, wherein the thermoplastic resin (B) contains a thermoplastic resin (B ′) containing butadiene as an essential copolymerization component. . 20. The semiconductor integrated circuit connection according to claim 11, wherein the thermoplastic resin (B) is a thermoplastic resin (B ″) containing butadiene as an essential copolymer component and having a carboxyl group. Board parts. 21. An insulating layer constituting a wiring board layer comprising an insulator layer and a conductor pattern, wherein at least one or more polyimide films are formed, and the conductor pattern contains copper. 12. The component of the substrate for connecting a semiconductor integrated circuit according to item 11. 22. A layer where no conductor pattern is formed,
The component of the substrate for connecting a semiconductor integrated circuit according to claim 12, wherein the component is a metal plate. 23. The component of the substrate for connecting a semiconductor integrated circuit according to claim 11, wherein the protective layer is an organic film subjected to a release treatment.