JPH10178060A - Board for connecting semiconductor integrated circuit and part and semiconductor device constituting the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reflow resistance property and thermal cycle property by using a thermosetting type that is made of epoxy resin and thermoplastic resin as an adhesive composition used for a board for connecting a semiconductor integrated circuit. SOLUTION: A board for connecting semiconductor integrated circuit includes at least one layer of each of a wiring substrate layer that consists of an insulator layer and a conductor pattern, a layer where no conductor pattern is formed, and an adhesive layer. Phenolnovolac-type epoxy resin or epoxy resin that is expressed by an equation is preferable as epoxy resin contained in the adhesive layer and R1-R10 in the expression indicates hydrogen atom, low-class alkyl group of C1-F4, or halogen atom. The epoxy resin is preferably blended by 20-60wt.% in the adhesive composition. A thermoplastic resin preferably has, for example, amino group, carboxyl group, epoxy group, hydroxyl group, and methylol group as a functional group that can react with the epoxy resin.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate (interposer) for connecting a semiconductor integrated circuit (IC) for mounting and packaging the semiconductor integrated circuit, a component constituting the substrate, and a semiconductor device. More specifically, a wiring board layer composed of an insulating layer and a conductor pattern constituting a substrate for connecting a semiconductor integrated circuit used in a ball grid array (BGA) and land grid array (LGA) type surface mounting package, and a metal reinforcing plate, for example. (Stiffeners, heat spreaders) for connecting semiconductor integrated circuits with a structure in which layers without conductor patterns are bonded and laminated with an adhesive composition having excellent reliability such as solder heat resistance and thermal cycling properties. The present invention relates to a substrate and a semiconductor device using the same.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor integrated circuit (IC) package, a dual in-line package (DIP),
Package forms such as a small outline package (SOP) and a quad flat package (QFP) have been used. However, with the increase in the number of pins of the IC and the miniaturization of the package, the limit of the QFP having the largest number of pins is approaching its limit. This is due to the difficulty in handling due to the narrow pitch between external terminals (leads) and the difficulty in obtaining solder printing accuracy on the printed board, particularly when mounting on a printed board. Therefore, in recent years, a BGA method, an LGA method, a PGA method and the like have been put to practical use as means for increasing the number of pins and reducing the size. Above all, the BGA method has attracted a great deal of attention not only because it can be reduced in cost, weight and thickness by using a plastic material, but also because it can be surface-mounted.

FIG. 1 shows an example of the BGA system. The BGA method is characterized in that solder balls almost corresponding to the number of pins of an IC are provided in a grid (area array) as external connection terminals of a semiconductor integrated circuit connection board to which the IC is connected.
The connection to the printed board is performed by batch reflow in which the solder ball surface is placed so as to match the conductor pattern of the printed board on which the solder is already printed, and the solder is melted by reflow. The feature of the package is that the connection terminals are arranged on the back surface of the package, compared to the conventional IC package in which the connection terminals are arranged around the QFP.
The reason is that more connection terminals can be arranged in a small space at a wide interval. For this reason, on the mounting surface, it is possible to reduce the mounting area and increase the mounting efficiency.

[0004] A chip scale package (CSP) is one that has further advanced this function, and is called a micro BGA because of its similarity. The present invention relates to these BGs.
The present invention can be applied to a CSP having an A structure.

On the other hand, the BGA package has the following problems. (A) Flatness of the solder ball surface, (b) reflow resistance, (c) heat dissipation, and (c) thermal cycle properties.

As a method of improving these, a method of laminating a material such as a metal plate for reinforcement (maintaining flatness), heat radiation, and electromagnetic shielding on a substrate for connecting a semiconductor integrated circuit is generally used. . In particular, it becomes important when a TAB tape or a flexible substrate is used for a wiring board layer composed of an insulating layer and a conductor pattern for connecting an IC.

Therefore, the substrate for connecting a semiconductor integrated circuit is
As illustrated in FIG. 2, a wiring board layer including an insulator layer 11 and a conductor pattern 13 for connecting an IC, a reinforcing plate (stiffener), a heat sink (heat spreader),
Layer 1 on which no conductor pattern such as a shield plate is formed
5, and at least one adhesive layer 14 for laminating them. For these semiconductor integrated circuit connection substrates, a part as an intermediate product is prepared in advance by laminating or applying and drying the adhesive composition in a semi-cured state on either the wiring substrate layer or the layer where no conductor is formed. It is created by bonding and heat curing in a package assembly process.

Finally, the adhesive layer 14 remains inside the package. From the above points, the properties required for the adhesive layer 14 include (a) reflow resistance, and (b) stress absorption occurring between different materials such as a wiring board layer and a reinforcing plate during a temperature cycle or reflow. Low stress), (c) easy workability,
(D) Insulation when laminated on wirings, and the like.

Among them, important requirements are reflow resistance and thermal cycle resistance.

[0010] The reflow resistance is determined by a mounting method in which the entire package is heated to a high temperature of 210 to 270 ° C, such as immersion in a solder bath, heating with a saturated vapor of an inert gas (a vapor phase method), or infrared reflow. It peels off and reduces the reliability of the package. It is said that the peeling in the reflow process is caused by the explosion of water that has been absorbed between the curing of the adhesive layer and the mounting process explosively turning into steam during heating. A method has been used in which a package that has been completely dried and stored in a sealed container is shipped.

The thermal cycle resistance is a characteristic required for a package having a large number of pins, such as a BGA, because the temperature of the package is higher than 100 ° C. during operation. In order to alleviate this, a low elastic modulus is required.

[0012] For these reasons, various improvements in adhesives have been studied. For example, as an adhesive layer having excellent thermal cycle resistance, a thermoplastic resin or a silicone elastomer having a low elastic modulus (Japanese Patent Publication No. 6-50448).
And so on.

[0013]

However, the method of enclosing a dry package in a container has disadvantages in that the manufacturing process and the handling of the product are complicated, and the product price is extremely high.

Further, although the adhesives proposed variously have excellent thermal cycle resistance, they do not satisfy the reflow resistance.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems arising in the reflow process, and to provide a semiconductor integrated circuit connection substrate having high reliability, excellent reflow resistance, and excellent thermal cycling properties, components constituting the same, and a semiconductor device. Is to provide.

[0016]

That is, the present invention provides a semiconductor integrated circuit connecting substrate having at least one wiring board layer comprising an insulator layer and a conductor pattern, at least one layer on which no conductor pattern is formed, and at least one adhesive layer. The adhesive composition constituting the adhesive layer is an epoxy resin (A)
And a thermosetting adhesive composition comprising a thermoplastic resin (B) and a substrate for connecting a semiconductor integrated circuit, components constituting the same, and a semiconductor device.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the present invention will be described below in detail.

The substrate for connecting a semiconductor integrated circuit in the present invention is for connecting a semiconductor element, and includes a wiring board layer composed of an insulator layer and a conductor pattern, a layer on which no conductor pattern is formed, and an adhesive layer. The shape, material, and manufacturing method are not particularly limited as long as it has at least one layer. Therefore, the most basic one is 3
Although it has a layer structure, a multi-layer structure of more layers is also included in this.

The wiring board layer is a layer having a conductor pattern for connecting the electrode pads of the semiconductor element and the outside of the package (such as a printed board), and has a conductor pattern formed on one or both sides of the insulator layer. Things.

The insulator layer referred to here is made of a plastic such as polyimide, polyester, polyphenylene sulfide, polyether sulfone, polyether ether ketone, aramid, polycarbonate, polyarylate or a composite material such as epoxy resin impregnated glass cloth. A flexible insulating film having a thickness of 10 to 125 μm, a ceramic substrate made of alumina, zirconia, soda glass, quartz glass, or the like is suitable, and a plurality of layers selected therefrom may be used by lamination. If necessary, hydrolysis, corona discharge, low-temperature plasma,
Surface treatment such as physical roughening and easy adhesion coating treatment can be performed.

The formation of the conductor pattern is generally performed by either the subtractive method or the additive method, but any of them may be used in the present invention.

In the subtractive method, a metal plate such as a copper foil is bonded to the insulator layer with an insulating adhesive, or a precursor of the insulator layer is laminated on the metal plate, and the insulator layer is heated and the like. Is formed by etching the material prepared by the method of forming by a chemical treatment. Specific examples of the material include a rigid or flexible printed circuit board copper bonding material and a TAB tape.
Among them, a copper paste material for flexible printed circuit boards or a TAB tape using at least one or more polyimide films as an insulator layer and a copper foil as a conductor pattern is preferably used.

In the additive method, a conductor pattern is directly formed on an insulator layer by electroless plating, electrolytic plating, sputtering, or the like.

In any case, the formed conductor may be plated with a metal having high corrosion resistance to prevent corrosion.
Also, via holes may be formed in the wiring board layer as necessary, and conductive patterns formed on both sides may be connected by plating.

The layer on which the conductor pattern is not formed is used to reinforce the substrate for connecting the semiconductor integrated circuit and stabilize the dimensions (referred to as a reinforcing plate or a stiffener), to provide electromagnetic shielding between the outside and the IC, and to radiate the IC (heat). The substrate has functions such as imparting flame retardancy to the semiconductor integrated circuit connection substrate and imparting discriminability based on the shape of the semiconductor integrated circuit connection substrate. Accordingly, the shape may be not only a layer shape but also a fin structure for heat dissipation, for example. Any insulator or conductor as long as it has the above functions may be used.
The material is not particularly limited. Metals include copper, iron, aluminum, gold, silver, nickel, titanium, and the like; inorganic materials include alumina, zirconia, soda glass, quartz glass, and carbon; and organic materials include polyimide, polyamide, polyester, and vinyl. System, phenol system,
A polymer material such as an epoxy-based material may be used. Further, a composite material obtained by combining these can also be used. For example,
Examples include a shape in which thin metal plating is performed on a polyimide film, a material in which carbon is kneaded into a polymer to impart conductivity, and a metal plate in which an organic insulating polymer is coated. If necessary, the insulator layer may be subjected to a surface treatment such as hydrolysis, corona discharge, low-temperature plasma, physical roughening, and easy adhesion coating treatment. It is important that the adhesive layer in the present invention is a thermosetting adhesive containing an epoxy resin (A) and a thermoplastic resin (B).

The epoxy resin (A) contained in the adhesive layer of the present invention is not particularly limited as long as it has two or more epoxy groups in one molecule, and specific examples thereof include, for example, a cresol novolac type. Epoxy resin, phenol novolak type epoxy resin, epoxy resin represented by the following formula (1),

Embedded image (However, R1 to R10 each represent a hydrogen atom, a C1 to C4 lower alkyl group or a halogen atom.) Linear aliphatic epoxy resin, alicyclic epoxy resin, heterocyclic epoxy resin, spiro ring-containing epoxy resin and Halogenated epoxy resins are exemplified.

Among these epoxy resins (A), those which are particularly preferably used in the present invention are phenol novolak type epoxy resins having high adhesion and excellent electrical properties and reflow resistance or epoxy resins having a skeleton of the above formula (1). Resin. The epoxy resin (A) contains at least one of a phenol novolak type epoxy resin and an epoxy resin having a skeleton represented by the above formula (1) in the epoxy resin (A) in an amount of 20% by weight or more, and more preferably 50% by weight. %
It is preferable to contain the above.

In the epoxy resin having a skeleton represented by the above formula (1), preferred specific examples of R1 to R10 include a hydrogen atom, a methyl group, an ethyl group, a sec-butyl group, a t-butyl group and a chlorine atom. And a bromine atom.

Preferred specific examples of the epoxy resin represented by the above formula (1) include bisphenol A epoxy resin, bisphenol F epoxy resin, brominated bisphenol A epoxy resin, and brominated bisphenol F epoxy resin. No.

In the present invention, the amount of the epoxy resin (A) is 5 to 90% by weight, preferably 10 to 90% by weight in the adhesive composition.
７０70% by weight, more preferably 20-60% by weight.

The thermoplastic resin (B) contained in the adhesive layer of the present invention is not particularly limited as long as it gives flexibility to the adhesive layer. Specific examples thereof include acrylonitrile butadiene copolymer. Coal (NBR), acrylonitrile-butadiene rubber-styrene resin (ABS), polybutadiene, styrene-butadiene-ethylene resin (SE
BS), acrylic, polyvinyl butyral, polyamide, polyethylene, polyester, polyimide, polyamideimide, polyurethane and the like. Further, these thermoplastic resins preferably have a functional group capable of reacting with the epoxy resin (A) in order to improve heat resistance. Specific examples include an amino group, a carboxyl group, an epoxy group, a hydroxyl group, a methylol group, an isocyanate group, a vinyl group, and a silanol group.

Among them, a copolymer containing butadiene as an essential copolymer component is preferably used in terms of adhesiveness, flexibility and thermal stress relaxation. Particularly, acrylonitrile-butadiene copolymer (N
BR), styrene-butadiene-ethylene resin (SEB)
S), styrene-butadiene resin (SBS) and the like are preferred. Further, a copolymer containing butadiene as an essential copolymer component and having a carboxyl group is preferable, and specific examples thereof include NBR (NBR-C) and SEBS (SEBS-C).
Is mentioned.

In the adhesive layer of the present invention, reflow resistance and thermal cycle resistance can be further improved by adding an inorganic filler (C) to the adhesive layer. Specific examples of the inorganic filler (C) include aluminum hydroxide, alumina, magnesium hydroxide, calcium aluminate hydrate, silica, zirconium oxide, zinc oxide, antimony trioxide, antimony pentoxide, magnesium oxide, and oxide. Examples include titanium, iron oxide, cobalt oxide, chromium oxide, talc, aluminum, gold, silver, nickel, and iron. Among them, aluminum hydroxide, alumina and silica are preferable from the viewpoint of dispersibility, and those having an average particle size of 0.1 to 20 μm are preferably used.

The amount of the inorganic filler (C) is 1 to 90% by weight, preferably 5 to 70% by weight, more preferably 10 to 50% by weight in the adhesive composition.

In the adhesive layer of the present invention, reflow resistance and insulation reliability can be further improved by adding a phenol resin (D) to the adhesive layer. Specific examples of the phenol resin (D) include, for example, a phenol novolak resin, a cresol novolak resin, a bisphenol A type resin, various resole resins, and the like.

The mixing ratio of the phenolic resin is usually from 0.5 to 1 phenolic hydroxyl group per equivalent of epoxy resin.
It is desirably in the range of 0.0 equivalent, preferably 0.7 to 7.0 equivalent.

The adhesive layer of the present invention contains a curing accelerator which promotes a single reaction of the epoxy resin (A) or a reaction between the epoxy resin (A) and the thermoplastic resin (B) or the phenol resin (D). Can be. The curing accelerator is not particularly limited as long as it accelerates the curing reaction, and specific examples thereof include:
For example, 2-methylimidazole, 2,4-dimethylimidazole, 2-ethyl-4-methylimidazole,
Imidazole compounds such as 2-phenylimidazole, 2-phenyl-4-methylimidazole and 2-heptadecylimidazole, triethylamine, benzyldimethylamine, α-methylbenzyldimethylamine,
-(Dimethylaminomethyl) phenol, 2,4,6-
Tris (dimethylaminomethyl) phenol and 1,
Tertiary amine compounds such as 8-diazabicyclo (5,4,0) undecene-7, zirconium tetramethoxide,
Organometallic compounds such as zirconium tetrapropoxide, tetrakis (acetylacetonato) zirconium and tri (acetylacetonato) aluminum; and triphenylphosphine, trimethylphosphine, triethylphosphine, tributylphosphine, tri (p-methylphenyl) phosphine and tri Organic phosphine compounds such as (nonylphenyl) phosphine are exemplified.

Two or more of these curing accelerators may be used in combination depending on the application. The amount of the curing accelerator ranges from 0.1 to 10 parts by weight based on 100 parts by weight of the epoxy resin (A). preferable.

The components (hereinafter, referred to as components) of the substrate for connecting a semiconductor integrated circuit of the present invention are materials in an intermediate processing stage used for producing a substrate for connecting a semiconductor integrated circuit and a semiconductor device. The component has a configuration having at least one or more adhesive layers having a protective film layer and a wiring board layer formed of an insulator layer and a conductor pattern and / or a layer having no conductor pattern. For example, a flexible printed board or TA as a wiring board layer composed of an insulator layer and a conductor pattern
Using a B tape, a wiring board with an adhesive in which an adhesive layer of a B stage having a polyester protective film subjected to silicone treatment on one or both sides thereof is laminated, and a layer in which a conductor pattern is not formed, such as copper, stainless steel, 42 alloy, etc. A metal plate with an adhesive (such as a stiffener with an adhesive) in which a B-stage adhesive layer having a protective film layer on one or both sides thereof is laminated in the same manner as described above using a metal plate.
Corresponds to the component of the present invention. Even when there is at least one wiring board layer composed of an insulator layer and a conductor pattern and at least one layer on which the conductor pattern is not formed, a B-stage adhesive layer having a protective film layer on its outermost layer is laminated. A substrate for connecting a semiconductor integrated circuit with an agent is also included in the component of the present invention.

The protective film layer mentioned here is not particularly limited as long as it can be peeled off without damaging its form and function before bonding the adhesive layer, and specific examples thereof include polyester, polyolefin, polyphenylene sulfide, and the like.
Plastic films such as polyvinyl chloride, polytetrafluoroethylene, polyvinyl fluoride, polyvinyl butyral, polyvinyl acetate, polyvinyl alcohol, polycarbonate, polyamide, polyimide, polymethyl methacrylate, and release agents such as silicone or fluorine compounds Coated films, paper laminated with these films, paper impregnated or coated with a releasable resin and the like can be mentioned. The thickness of the protective film layer is 2 in terms of heat resistance.
It is at least 0 μm, preferably at least 25 μm, more preferably at least 35 μm.

The peel strength of the protective film layer from the adhesive layer is preferably 1 to 200 N / m, more preferably 3 N / m.
１００100 N / m. If it is lower than 1 N / m, the protective film is liable to fall off.

The semiconductor device according to the present invention is a device using the substrate for connecting a semiconductor integrated circuit according to the present invention.
The shape and structure are not particularly limited as long as the package is a GA type or LGA type package. Substrate for connecting semiconductor integrated circuit and I
The connection method of C may be any of TAB gang bonding and single point bonding, wire bonding used for a lead frame, resin sealing by flip chip mounting, anisotropic conductive film connection, and the like. Further, a package called a CSP is also included in the semiconductor device of the present invention.

Next, a description will be given of an example of a semiconductor integrated circuit connecting substrate of the present invention, components constituting the same, and a method of manufacturing a semiconductor device.

(1) Preparation of a wiring board composed of an insulator layer and a conductor pattern: A three-layer TAB tape in which an adhesive layer and a protective film layer are laminated on a polyimide film is prepared by the following (a) to (d). Process according to the process. (A)
Perforation of sprocket and device holes, (b) thermal lamination with copper foil, (c) pattern formation (resist coating, etching, resist removal), (d) tin or gold plating. FIG. 3 illustrates the shape of the obtained TAB tape (pattern tape).

(2) Preparation of a layer on which no conductor pattern is formed: A copper plate or a stainless plate having a thickness of 0.05 to 0.5 mm is degreased with acetone.

(3) Preparation of adhesive layer: A coating solution in which the adhesive composition is dissolved in a solvent is applied on a polyester film having releasability and dried. The thickness of the adhesive layer is 10 to 10
It is preferable to apply so as to have a thickness of 0 μm. Drying conditions are 100 to 200 ° C. for 1 to 5 minutes. Solvents are not particularly limited, but aromatic solvents such as toluene, xylene, and chlorobenzene; ketones such as methyl ethyl ketone and methyl ethyl isobutyl ketone; aprotic polar solvents such as dimethylformamide, dimethylacetamide, and N-methylpyrrolidine alone or as a mixture; Is preferred. An adhesive sheet is obtained by further laminating a polyester or polyolefin-based protective film having a weak release force and releasability on the coated and dried adhesive layer. When the thickness of the adhesive is further increased, the adhesive sheet may be laminated a plurality of times.
The degree of curing may be adjusted by aging at 0 ° C. for about 1 to 200 hours.

(4) Preparation of a component (wiring board with adhesive) of a substrate for connecting a semiconductor integrated circuit: a protective film layer on one side of the adhesive sheet prepared in (3) above, on the wiring board layer of (1). After peeling off, laminate. The laminate surface may be either a surface with or without a conductor pattern. Laminating temperature 20 ~ 200 ℃, pressure 0.1 ~ 3
MPa is preferred. Finally, punching and cutting are performed as appropriate depending on the shape of the semiconductor device. FIG. 4 illustrates the component of the present invention.

(5) Preparation of a component (stiffener with an adhesive) of a substrate for connecting a semiconductor integrated circuit: The protective film layer on one side of the adhesive sheet prepared in the above (3) was peeled off from the above (2) metal plate. Laminated later. A lamination temperature of 20 to 200 ° C. and a pressure of 0.1 to 3 MPa are preferred. Alternatively, the coating of (3) may be directly applied to (B) and dried, and a protective film may be laminated. Finally, punching and cutting are performed as appropriate depending on the shape of the semiconductor device. FIG. 5 shows an example of the component of the present invention.

(6) Preparation of a substrate for connecting a semiconductor integrated circuit: (a) Method using a wiring board with an adhesive A protective film of an adhesive layer is peeled off from the component (wiring board with an adhesive) in (4), and an appropriate method is used. Glue it to a punched metal plate. As the metal plate, for example, a metal plate having a square shape and punched into a shape having a square hole in accordance with the device hole of the wiring board in the center can be exemplified. The bonding conditions are preferably a temperature of 20 to 200 ° C. and a pressure of 0.1 to 3 MPa. Finally, post-curing is performed in a hot-air oven at 80 to 200 ° C. for about 15 to 180 minutes for heat curing of the adhesive.

(B) Method of using a stiffener with an adhesive The part (5) (stiffener with an adhesive) is punched out with a metal mold, and for example, a stiffener with an adhesive having a square shape and also having a square hole at the center. And The protective film layer is peeled off from the stiffener with the adhesive, and the center hole of the stiffener with the adhesive is aligned with the device hole of the wiring board on the conductor pattern surface of the wiring substrate layer or the polyimide film surface on the back surface of (1). And stick them together. The bonding conditions are preferably a temperature of 20 to 200 ° C. and a pressure of 0.1 to 3 MPa. Finally, post-curing is performed in a hot-air oven at 80 to 200 ° C. for about 15 to 180 minutes for heat curing of the adhesive.

FIG. 2 shows an example of the substrate for connecting a semiconductor integrated circuit described above.

(7) Fabrication of a semiconductor device: The inner lead portion of the substrate for connecting a semiconductor integrated circuit of (6) is thermocompression-bonded (inner lead bonding) to a gold bump of the IC, and
With. Next, a semiconductor device is manufactured through a resin sealing step using a sealing resin. The obtained semiconductor device is connected to a printed circuit board or the like on which other components are mounted via solder balls, and mounted on an electronic device. Further, a so-called TCP type semiconductor device in which an IC is connected to the wiring board in the above (1) in advance and sealed with a resin can be used. FIG. 1 is a cross-sectional view of one embodiment of a semiconductor device of the present invention.

[0053]

The present invention will be described more specifically with reference to the following examples.

Examples 1-3, Comparative Example 1 The following thermoplastic resin, epoxy resin and other additives were blended so as to have the composition ratios shown in Table 1, respectively, and the concentration was 28% by weight.
Then, the mixture was stirred and dissolved in a DMF / monochlorobenzene / MIBK mixed solvent at 40 ° C. so as to obtain an adhesive solution.

A. Epoxy resin 1. o-cresol novolak type epoxy resin (epoxy equivalent: 200) Bisphenol A type epoxy resin (epoxy equivalent:
186) B.I. C. Thermoplastic resin SEBS-C (MX-073, manufactured by Asahi Kasei Corporation) D. Inorganic filler Aluminum hydroxide (average particle size: 2 μm) P. phenol resin phenol novolak resin (hydroxyl equivalent: 107) Additives 1,4,4'-diaminodiphenylsulfone 2.2-heptadecylimidazole These adhesive solutions were applied to a 25 μm thick silicated polyethylene terephthalate film 1 with a bar coater to a dry thickness of about 50 μm. Apply to 1
It was dried at 00 ° C., 1 minute and 150 ° C. for 5 minutes to prepare an adhesive sheet. On the other hand, a polyethylene terephthalate film 2 having a lower release force than polyethylene terephthalate 1
Then, apply the adhesive solution to about 50 μm
After drying, the adhesive sheet and the adhesive surface were laminated to form an adhesive sheet having a thickness of 100 μm.

[Adhesion] Polyimide film (75 μm)
m: An adhesive sheet was laminated on “Upilex 75S” manufactured by Ube Industries, Ltd. at 40 ° C. and 1 MPa. Then, 130 μm of SUS304 having a thickness of 25 μm was applied to the surface of the adhesive sheet laminated on the polyimide film.
After further laminating under the conditions of 1 ° C. and 1 MPa, a heat treatment was sequentially performed in an air oven at 100 ° C. for 1 hour, at 150 ° C. for 1 hour, and an evaluation sample was prepared.

After slitting the polyimide film to a width of 5 mm, the polyimide film having a width of 5 mm was peeled off at a speed of 50 mm / min in the direction of 90 °, and the adhesive force at that time was measured.

[Reflow resistance] 0.25 m of 30 mm square
After the single-sided protective film of the adhesive sheet was peeled off on a SUS304 m-thick substrate, the adhesive sheet was laminated at 40 ° C. and 1 MPa to form a stiffener with an adhesive. Next, the protective film of the stiffener with an adhesive was peeled off on a 30 mm square semiconductor connection substrate on which a simulation pattern having a conductor width of 100 μm and a distance between conductors of 100 μm was formed.
Crimping was carried out at 75 ° C. for 5 seconds. Then 15
The composition was cured at 0 ° C. for 2 hours to prepare a sample for evaluating reflow resistance.

[0059] Twenty 30mm □ samples were prepared at 85 ° C / 85
% RH for 12 hours. 23
The film was subjected to IR reflow at 0 ° C. for 10 seconds, and the peeled state was observed with an ultrasonic short wound machine.

[Thermal cycling property] Ten 30 mm square samples prepared by the same method as the sample for evaluating reflow resistance were subjected to a cycle treatment at -20 ° C to 100 ° C, and at the minimum and maximum temperatures for 1 hour each. Internal peeling was observed using an ultrasonic flaw detector.

[0061]

[Table 1]

As is clear from the results shown in Table 1, the components of the substrate for connecting a semiconductor integrated circuit obtained by the present invention have high adhesive strength and excellent reflow resistance and thermal cycle properties. On the other hand, Comparative Example 1, in which the component of the substrate for connecting a semiconductor integrated circuit of the present invention was not used, not only has low adhesiveness but also inferior reflow resistance.

[0063]

Industrial Applicability The present invention is to provide a thermosetting type connection board for semiconductor integrated circuits having excellent reflow resistance and thermal cycling properties, a component constituting the connection board and a semiconductor device, and to provide a semiconductor device for industrial use. The reliability of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of one embodiment of a BGA type semiconductor device using a semiconductor device adhesive composition and a semiconductor adhesive sheet of the present invention.

FIG. 2 shows one embodiment of a substrate for connecting a semiconductor integrated circuit before connecting the semiconductor integrated circuit using the adhesive composition for a semiconductor device of the present invention.

FIG. 3 is a perspective view of one embodiment of a pattern tape (TAB tape) constituting a substrate for connecting a semiconductor integrated circuit.

FIG. 4 is a cross-sectional view of one embodiment of a component (wiring substrate with an adhesive) of the substrate for connecting a semiconductor integrated circuit according to the present invention.

FIG. 5 is a cross-sectional view of one embodiment of a component (a stiffener with an adhesive) of a substrate for connecting a semiconductor integrated circuit according to the present invention.

[Explanation of symbols]

1. 1. Semiconductor integrated circuit Gold bumps 3,11,17. Flexible insulating film 4,12,18. Adhesive layer constituting wiring board layer 5, 13, 21. Conductors for connecting semiconductor integrated circuits 6, 14, 23. Adhesive layer composed of adhesive composition of the present invention 7,15. Layer in which no conductor pattern is formed 8,16. Solder resist 9. Solder ball 10. Sealing resin 19. Sprocket hole 20. Device hole 22. Conductor for solder ball connection

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI C09J 201/00 C09J 201/00 H01L 23/12 H01L 23/12 L

Claims (17)

[Claims] 1. A semiconductor integrated circuit connecting substrate having at least one or more wiring board layers each including an insulator layer and a conductor pattern, a layer on which no conductor pattern is formed, and an adhesive layer. Wherein the adhesive composition is a thermosetting adhesive composition comprising an epoxy resin (A) and a thermoplastic resin (B). 2. The substrate for connecting a semiconductor integrated circuit according to claim 1, wherein the epoxy resin (A) contains an epoxy resin represented by the following formula (1) as an essential component. Embedded image (However, R1 to R10 each represent a hydrogen atom, a C1 to C4 lower alkyl group or a halogen atom.) 3. The connection substrate for a semiconductor integrated circuit according to claim 1, wherein the thermoplastic resin (B) contains a thermoplastic resin (B ′) containing butadiene as an essential copolymer component. 4. The thermoplastic resin (B) is a thermoplastic resin (B ′) containing butadiene as an essential copolymerization component, and is a thermoplastic resin (B ″) having a carboxyl group. The substrate for connecting a semiconductor integrated circuit according to claim 1. 5. The substrate according to claim 1, wherein the adhesive layer contains an inorganic filler (C). 6. The substrate for connecting a semiconductor integrated circuit according to claim 5, wherein the inorganic filler (C) contains an aluminum hydroxide powder (C ′). 7. A semiconductor device using the substrate for connecting a semiconductor integrated circuit according to claim 1. 8. A component of a substrate for connecting a semiconductor integrated circuit having at least one or more adhesive layers each having a wiring board layer composed of an insulator layer and a conductor pattern and a protective film layer, wherein the adhesive layer is formed. Wherein the adhesive composition to be formed is a thermosetting adhesive composition comprising an epoxy resin (A) and a thermoplastic resin (B). 9. A component of a substrate for connecting a semiconductor integrated circuit having at least one or more adhesive layers each having a layer on which no conductor pattern is formed and a protective film layer, wherein the adhesive constituting the adhesive layer is provided. A component for a substrate for connecting a semiconductor integrated circuit, wherein the composition is a thermosetting adhesive composition comprising an epoxy resin (A) and a thermoplastic resin (B). 10. The component of the substrate for connecting a semiconductor integrated circuit according to claim 8, wherein the epoxy resin (A) contains an epoxy resin represented by the following formula (1) as an essential component. Embedded image (However, R1 to R10 each represent a hydrogen atom, a C1 to C4 lower alkyl group or a halogen atom.) 11. The connecting substrate for a semiconductor integrated circuit according to claim 8, wherein the thermoplastic resin (B) contains a thermoplastic resin (B ′) containing butadiene as an essential copolymerization component. parts. 12. The thermoplastic resin (B) is a thermoplastic resin (B ′) containing butadiene as an essential copolymerization component, and is a thermoplastic resin (B ″) having a carboxyl group. A component of the substrate for connecting a semiconductor integrated circuit according to claim 8. 13. The component of the substrate for connecting a semiconductor integrated circuit according to claim 8, wherein the adhesive layer contains an inorganic filler (C). 14. The method according to claim 13, wherein the inorganic filler (C) contains an aluminum hydroxide powder (C ′).
Parts of the substrate for connecting a semiconductor integrated circuit according to the above. 15. An insulator layer constituting a wiring board layer comprising an insulator layer and a conductor pattern, wherein the insulator layer comprises at least one polyimide film, and the conductor pattern contains copper. 9. The component of the substrate for connecting a semiconductor integrated circuit according to item 8. 16. A layer on which no conductor pattern is formed,
The component of the substrate for connecting a semiconductor integrated circuit according to claim 9, wherein the component is a metal plate. 17. The component for a substrate for connecting a semiconductor integrated circuit according to claim 8, wherein the protective film layer of the adhesive layer is an organic film subjected to a release treatment.