JPH10177369A - Active matrix display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active matrix display device capable of reducing driving frequency and dropping power consumption. SOLUTION: A horizontal switch group 2 is connected to one end of a signal line S and supplies an external video signal, to the signal line S. Plural horizontal scanning circuits 3a, 3b to 3m control the opening/closing operation of the switch group 2 after receiving start signals so that a video signal of one frame is divided into plural sub-fields and written in respective pixels. A start control circuit 4 outputs start signals for controlling the start of the circuits 3a, 3b to 3m.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix display device, and more particularly, to a row-shaped gate line, a column-shaped signal line, a matrix-shaped pixel arranged at each intersection of the two, and a line connecting the gate line. A vertical scanning circuit for sequentially scanning and selecting one row of the pixels every one horizontal period.

[0002]

2. Description of the Related Art A liquid crystal display can be easily thinned.
It has the feature of being easily colored, and is widely used as a display screen. In recent years, polysilicon TF
An active matrix liquid crystal display of T (Thin Film Transistor) has been put to practical use. This means that a switch such as a thin film transistor provided in a pixel portion is turned on for each pixel at a frequency of several tens KHz to several MHz from a horizontal scanner (H scanner) and a vertical scanner (V scanner) built in the outer edge of the panel. It is driven in a dot-sequential manner, and is excellent in contrast, response speed, color purity, and the like.

FIG. 17 shows a point-sequential drive type polysilicon T. As shown in FIG.
It is a block diagram of an FT active matrix liquid crystal display. The dot-sequential drive type polysilicon TFT active matrix liquid crystal display has row-shaped gate lines G1 and G1.
, And column-like signal lines S1, S2,... And a matrix of pixels LC arranged at the intersections of the two. Further, an H scanner 301 including an H shift register 301a and a bidirectional scan circuit 301b, and a V scanner 101 including a V shift register 101a are provided.

[0004] Each pixel LC has a thin film transistor Tr.
And the like. The gate electrode of the thin film transistor Tr is connected to the corresponding gate line G, the source electrode is connected to the corresponding signal line S, and the drain electrode is connected to the corresponding storage capacitor Cs and pixel LC.

The H scanner 301 converts AC video signals R, G, and B from a video line to each signal line S within one horizontal period.
1, S2,... Are sequentially sampled, and a video signal is written to the selected one line of pixels LC in dot sequence. The H scanner 301 includes an H shift register 301a in which flip-flops are connected in multiple stages, and a bidirectional scan circuit 301b that outputs positive and negative drive signals.

[0006] Further, the V scanner 101
Are line-sequentially scanned to select one line of pixels LC every horizontal period. That is, a sampling pulse is output to each gate line G every one horizontal period, and the thin film transistors Tr on the same line are made conductive.

The H shift register 301a includes a pair of externally supplied horizontal clocks HCK1 and HC
It operates according to K2, sequentially transfers a horizontal start signal HST also supplied from the outside, and outputs a sampling pulse for each stage. The waveform of the sampling pulse is shaped by the bidirectional scan circuit 301b to obtain a final sampling pulse.

Each of the signal lines S1, S2,... Is connected to a plurality of horizontal switches (H switches) 201, and receives a video signal from the outside via a common video line RGB. Then, each H switch 201 sequentially opens and closes with a corresponding sampling pulse, and sequentially samples video signals to corresponding signal lines S1, S2, S3,.

FIG. 18 is a diagram showing how pixel voltages are written by dot sequential driving. Each grid corresponds to a dot, RG
One pixel is composed of three dots B. The portion where the pixel voltage can be written at a time by the dot sequential driving is one RGB portion of a certain column. For example, in the drawing, the pixel voltage can be written in the hatched RGB portions of the n-th column. Then, the writing portion moves in the direction of the arrow.

The point-sequential drive type polysilicon T
The FT active matrix liquid crystal display is expected to be put to practical use as a display for a portable terminal in combination with, for example, a reflective liquid crystal that does not require a backlight. For this purpose, low power consumption is an issue.

Also, a dot sequential drive type polysilicon TFT
The power consumption of the driving circuit of the active matrix liquid crystal display is determined by how many pixels the driving frequency of the H scanner 301 writes in one horizontal period. Therefore, the power consumption of the drive circuit is proportional to the drive frequency and is usually on the order of several MHz.

On the other hand, the power consumption of the drive circuit of the active matrix liquid crystal display using the line-sequential drive type amorphous silicon TFT is as follows.
Hz, which is generally lower than that of the dot sequential driving type. This description is described below.

FIG. 19 is a configuration diagram of a line-sequential drive type amorphous silicon TFT active matrix liquid crystal display. Line-sequential drive type amorphous silicon T
The FT active matrix liquid crystal display includes a pixel unit 501, an external V scanner 101, and an H driver 302.
have.

The H bidirectional shift register 302a includes an HC
K is received and HST is sequentially transferred to generate a sampling pulse. The sampling pulse is stored in the data register 3
The read control is performed in 02b, and the data is held in the line memory 302c for one horizontal period.

The decoder buffer 302d decodes drive voltage signals V0 to V7 input from the outside by using a sampling pulse, which is transfer data output from the line memory 302c, as a decode enable and decodes the signal line S
1, S1...

The pixels LC for one row scanned line-sequentially by the V-scanner 101 are stored in the line memory 3.
The pixel voltage is written at one time during one horizontal period with one line of transfer data accumulated by 02c.

FIG. 20 is a diagram showing how pixel voltages are written by line-sequential driving. Each grid corresponds to a dot, RG
One pixel is composed of three dots B. The portion where the pixel voltage can be written at a time by the line sequential driving is all the RGB portions of a certain column. For example, in the drawing, the pixel voltage can be written in the hatched RGB portions of the n-th column. Then, the writing portion moves in the direction of the arrow.

As described above, in the line-sequential driving type amorphous silicon TFT active matrix liquid crystal display, the line memory 302 in the driving IC external to the panel is provided.
After c transfers the transferred data for one line, the pixel voltage of the data is written at one time during one horizontal period, so that the substantial driving frequency is as low as several tens KHz which is the same as the horizontal frequency.

Therefore, even in a dot-sequential drive type polysilicon TFT active matrix liquid crystal display, power consumption can be reduced by using a line-sequential drive type, but it is difficult to form a line memory on a panel. , The driving frequency of the H scanner 301 must be reduced while the dot sequential driving is performed.

Conventional techniques for lowering the driving frequency include reducing the number of pixels, lowering the frame frequency, and writing a plurality of pixels at once from a plurality of H scanners.

[0021]

However, when the number of pixels is reduced as described above, there is a problem that the resolution is reduced.

Further, when the frame frequency is lowered, there is a problem that flicker occurs. Further, when writing a plurality of pixels at once from a plurality of H scanners, there is a problem that the number of H scanners is limited to two and there is also a problem of lowering the contrast.

The present invention has been made in view of such a point, and it is an object of the present invention to provide an active matrix display device in which a driving frequency is reduced to reduce power consumption.

[0024]

According to the present invention, in order to solve the above-mentioned problems, a row-like gate line, a column-like signal line, a matrix-like pixel disposed at each intersection of the two, A vertical scanning circuit for line-sequentially scanning lines to select one pixel in one row every one horizontal period, and an external video signal connected to one end of the signal line to output an external video signal. A plurality of horizontal switches for supplying a signal line, and a plurality of switches for controlling the opening and closing operation of the horizontal switches so that the video signal of one frame is divided into a plurality of subfields and written to the pixels after receiving a start signal. An active matrix display device comprising: a horizontal scanning circuit; and a startup control circuit that outputs the startup signal for performing startup control of the plurality of horizontal scanning circuits.

Here, the horizontal switch group is connected to one end of the signal line and supplies an external video signal to the signal line.
The plurality of horizontal scanning circuits perform opening / closing operation control of the horizontal switch group after receiving the start signal so that the video signal of one frame is divided into a plurality of subfields and written into the pixels. The activation control circuit outputs an activation signal for controlling activation of the plurality of horizontal scanning circuits.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a principle diagram of an active matrix display device of the present invention. The active matrix display includes a row-shaped gate line G, a column-shaped signal line S,
Pixels LC1 and LC arranged in a matrix at each intersection of the two.
2, LC3,... The vertical scanning circuit 1 scans the gate line G line-sequentially and selects one row of pixels LC1, LC2, LC3,... Every one horizontal period.

The horizontal switch group 2 is connected to one end of the signal line S and supplies an external video signal to the signal line S. The plurality of horizontal scanning circuits 3a, 3b to 3m divide a video signal of one frame into a plurality of
The opening and closing operation of the horizontal switch group 2 is controlled so as to be written in 1, LC2, LC3,. The activation control circuit 4
A start signal for controlling start of the plurality of horizontal scanning circuits 3a, 3b to 3m is output.

Next, the operation will be described. FIG. 2 is a flowchart illustrating an operation procedure of the active matrix display device. [S1] The activation control circuit 4 includes a plurality of horizontal scanning circuits 3a,
An activation signal for performing activation control of 3b to 3m is output. In this case, the cycle of the start signal is a cycle when a video signal of one frame is divided into a plurality of subfields and written into pixels. [S2] The horizontal scanning circuits 3a, 3b,.
3 m controls opening and closing operations of the corresponding horizontal switches of the horizontal switch group 2. [S3] The horizontal switches are the horizontal scanning circuits 3a, 3b to 3
An external video signal is supplied to the signal line S based on the opening / closing operation control from m.

Next, a detailed configuration of the active matrix display device of the present invention will be described. FIG. 3 is a detailed configuration diagram of the active matrix display device. The active matrix display device includes a pixel unit 50 including a plurality of row-shaped gate lines G, a plurality of column-shaped signal lines S, and a matrix of pixels LC arranged at each intersection of the two. . In each intersection, a thin film transistor Tr is formed as a switching element.

The gate electrode of each thin film transistor Tr is connected to the corresponding gate line G, the source electrode is connected to the corresponding signal line S, and the drain electrode is connected to the corresponding pixel LC. The storage capacitor C is adjacent to the pixel LC.
s connects.

Further, the active matrix display device has a vertical scanner 10 and a plurality of horizontal scanners 30a to 30a.
30 m. The vertical scanner 10 has a gate line G
Are line-sequentially scanned, and one row of pixels LC is selected every one horizontal period. More specifically, the vertical scanner 10 receives externally input vertical clock signals VCK1 and VCK2 having phases opposite to each other.
, And sequentially transfers an externally supplied vertical start signal VST, outputs a selection pulse to each gate line G every horizontal period, and turns on the thin film transistors Tr on the same line.

Each of the horizontal scanners 30a to 30m converts a video signal RGB from a video line into each signal line S within one horizontal period.
And video signals are written to the selected one line of pixels LC in dot sequence.

The horizontal scanners 30a to 30m are provided with corresponding horizontal switches 20a to 20m so that a video signal of one frame is divided into a plurality of subfields and written into pixels.
20m, 21a... Are controlled. Specifically, it operates according to a pair of mutually opposite horizontal clocks HCK1 and HCK2 supplied from a start control circuit (not shown), and outputs a horizontal start signal HS supplied from the start control circuit.
T1 to m are sequentially transferred. Then, each horizontal scanner 30
horizontal switches 20a to 20m, 21a,.
Are sequentially output, and scanning is performed every m pixels LC arranged in the horizontal direction.

A plurality of horizontal switches 20a to 20m, 21
are connected to one end of each signal line S, open and close in response to a sampling pulse, sequentially sample video signals RGB from a video line to each signal line S,
Write the video signal to

Next, the horizontal clocks HCK1 and HCK2 and the horizontal start signal HST according to the first embodiment of the present invention will be described.
The phase relationship of 1 to m will be described. FIG. 4 shows HCK1
FIG. 4 is a diagram showing phases of HCK2 and HST1 to HST1 to m. H
CK1 and HCK2 are rectangular waves having phases opposite to each other.
1 to m are rectangular waves in which one cycle is one horizontal period.

Next, the phase relationship between the horizontal start signals HST1 to HSTm will be described. FIG. 5 is a diagram showing the phases of HST1 to HST5. HST1 to HST5 are input to the horizontal scanners 30a to 30m with phases as shown in the figure. In the figure, when there are ten signal lines S, the scanning time corresponding to the number is one field, and one cycle of each of the HSTs 1 to 5 is m (= 5) fields, that is, one frame representing one display screen. Become.

Next, panel writing according to the first embodiment will be described. FIG. 6 is a diagram showing a state in which a video signal is written to the panel. Assuming that m = 5, ten signal lines S and five gate lines G are provided. The solid line in the drawing means that the video signal is written to the pixel, and the dotted line means that the video signal is not written. In addition, a + sign means that a video signal is written to a pixel with a positive polarity, and a-sign means that a video signal is written to a pixel with a negative polarity.

The writing scan of one field will be described. In the figure, a video signal is written to the pixels on the first and sixth columns. First, for the first and sixth columns, the video signal is written with the pixels in the first row having positive polarity. (The number of rows is not shown.) Next, a video signal is written to the pixels of the second row with negative polarity. This operation is performed alternately, and the video signal is written to the pixels in the fifth row with positive polarity. At this point, scanning of one field is completed.

For two-field write scanning,
Video signals are written to the pixels in the second and seventh columns. First, with respect to the second and seventh columns, a video signal is written with the pixels in the first row having negative polarity. Next, a video signal is written to the pixels in the second row with a positive polarity. Such scanning is performed alternately, and a video signal is written to the pixels in the fifth row with negative polarity.
At this point, scanning of the two fields is completed. Thereafter, the panel writing scan is performed in the same manner, and when five fields are completed, the panel writing for one frame is completed.

Next, the phase relationship between the horizontal start signals HST1 to HSTm according to the second embodiment of the present invention will be described.
The phase relationship between the horizontal clocks HCK1 and HCK2 and the horizontal start signals HST1 to HSTm is the same as in the first embodiment. FIG. 7 is a diagram showing the phases of HST1 to HST5. HST1 to HST5 are input to the horizontal scanners 30a to 30m with phases as shown in the figure. One cycle of each of the rectangular waves of HST1 to HST5 is an m (= 5) horizontal period.
The HSTs 1 to 5 are input to the horizontal scanners 30a to 30m every other horizontal period.

Next, panel writing according to the second embodiment will be described. FIG. 8 is a diagram illustrating a state in which a video signal is written to the panel. Assuming that m = 5, ten signal lines S and six gate lines G are provided. A + sign indicates that a video signal is written to a pixel with a positive polarity, and a − sign indicates that a video signal is written to a pixel with a negative polarity.

The writing scan of one field will be described. First, for the first and sixth columns, the video signal is written with the pixels in the first row having positive polarity. (The number of lines is not shown.)
Next, with respect to the second and seventh columns, video signals are written with the pixels in the second row having negative polarity. Such scanning is performed alternately, and a video signal is written to the pixels of the first row and the sixth row of the sixth column with negative polarity. At this point, scanning of one field is completed. Thereafter, the panel writing scan is performed in the same manner. As described above, in each of the first and second embodiments of the present invention, the interlace scan is performed and the first scan is performed.
In this embodiment, vertical writing is performed, and in the second embodiment, diagonal writing is performed to reduce the number of pixels to be written in one field without lowering the resolution. This makes it possible to reduce the power consumption by lowering the driving frequency of the horizontal scanner.

Next, the flicker compensation will be described with reference to FIGS.
This will be described with reference to FIG. FIG. 9 is a diagram illustrating an AC inversion phase of a video signal, and FIG. 10 is a diagram illustrating a flicker frequency.
FIG. 9 shows the phase of the video signal between 1 and 12 fields corresponding to the positive polarity write and the negative polarity write of each column. FIG. 10 shows the flicker frequency corresponding to each column.

As for the flicker caused by the extension of the frame period by the sub-field driving, the AC inversion period is 2 m fields as shown in the figure, but there are positive and negative phases, and the inversion phase is shifted by one field.
For this reason, flicker is spatially integrated and becomes equal to the field frequency (general 1 field = 1/60 second).
It becomes inconspicuous.

Next, the contrast will be described. The conventional horizontal scanner is divided into two parts, and a plurality of pixels are simultaneously written from each of them. The horizontal clock frequency is reduced to half while displaying one frame by one scan. When the (row) inversion driving is performed, the polarities of the pixel potentials adjacent to each other on the left and right are all the same, so that the gate line potential fluctuates and the contrast is reduced.

Therefore, in order to prevent a decrease in contrast in this case, it is necessary to perform a check in which dot inversion of a combination of column (column) inversion and row inversion is performed and all adjacent pixel potentials have opposite polarities. did. However, for column inversion, it is necessary to prepare two video signal voltages, a positive phase and a negative phase, and there is a problem that the circuit scale becomes large.

On the other hand, in the subfield display according to the first and second embodiments of the present invention, since a plurality of pixels are not written at the same time, the column inversion is not required and only the row inversion is required. Further, since the pixels adjacent to the left and right are written in one or more fields, the gate line potential hardly fluctuates even in the row inversion, and the contrast does not decrease. Therefore, the circuit scale can be reduced without requiring column inversion.

Next, the phase relationship between the horizontal start signals HST1 to HSTm according to the third embodiment of the present invention will be described.
The phase relationship between the horizontal clocks HCK1 and HCK2 and the horizontal start signals HST1 to HSTm is the same as in the first embodiment. FIG. 11 is a diagram showing the phases of HST1 to HST5. HST1 to HST5 are input to the horizontal scanners 30a to 30m with phases as shown in the figure.

Next, panel writing according to the third embodiment will be described. FIG. 12 is a diagram illustrating a state in which a video signal is written to the panel. The writing scan of one field will be described. First, the video signal is written with the pixel in the first row of the first column (the number of rows is not shown) having a positive polarity and the pixel in the first row of the sixth column having a negative polarity. Next, 2 in the first column
The video signal is written with the pixels in the row having a negative polarity and the pixels in the second row in the sixth column having a positive polarity. Such scanning is in the second row,
The process is performed up to the row that moves to the seventh column.

Next, the pixel in the first row in the second column has a negative polarity,
The video signal is written with the pixels in the first row of the column having positive polarity. Next, the video signal is written with the pixels in the second row of the second column being positive polarity and the pixels in the second row of the seventh column being negative polarity. Such scanning is performed up to the row that moves to the third and eighth columns. Thereafter, panel write scanning is performed in one field in the same manner. Next, the phase relationship between the horizontal start signals HST1 to HSTm according to the fourth embodiment of the present invention will be described. The phase relationship between the horizontal clocks HCK1 and HCK2 and the horizontal start signals HST1 to HSTm is the same as in the first embodiment. FIG. 13 is a diagram showing the phases of HST1 to HST5. HST1 to HST5 are input to the horizontal scanners 30a to 30m with phases as shown in the figure.

Next, panel writing according to the fourth embodiment will be described. FIG. 14 is a diagram showing a state in which a video signal is written to the panel. The writing scan of one field will be described. First, the video signal is written with the pixel in the first row of the first column (the number of rows is not shown) having a positive polarity and the pixel in the first row of the sixth column having a negative polarity. Next, 2 in the first column
The video signal is written with the pixels in the row having a negative polarity and the pixels in the second row in the sixth column having a positive polarity. Such scanning is in the second row,
The process is performed up to the row that moves to the seventh column.

Next, the pixel in the first row in the second column has a negative polarity.
The video signal is written with the pixels in the first row of the column having positive polarity. Next, the video signal is written with the pixels in the second row of the second column being positive polarity and the pixels in the second row of the seventh column being negative polarity. Such scanning is performed up to the row that moves to the third and eighth columns. Thereafter, panel writing scanning is performed in the same manner.

In the first embodiment, the columns adjacent to the column being written are written one or more fields earlier, and the latter is slightly lower in the potential immediately after writing and in the retained potential after several fields. Therefore, the contrast may be slightly different.

However, in the above-described third and fourth embodiments of the present invention, the configuration is such that the next horizontal scanner is switched within one field or several fields, so that it is possible to eliminate a subtle difference in contrast. Will be possible.

Next, the switching order of a plurality of horizontal scanners will be described. FIG. 15 is a diagram illustrating a switching order of a plurality of horizontal scanners. In the above description, the operation is sequentially shifted from the left end to the right side. However, in practice, arbitrary switching is possible.

For example, (A) sequentially from the left end to the right, (B)
Arbitrary switching is possible, such as sequentially from the right end to the left, (C) the left and right ends alternately and gradually toward the center, and (D) from the center to the left and right ends gradually.

Next, a case where the present invention is applied to a portable information terminal will be described. FIG. 16 is a diagram illustrating a case where the present invention is used for a portable information terminal. The dot sequential LCD of the present invention comprises a vertical scanner 100 and a horizontal switch 2.
00, the horizontal scanner 300, and the dot 5 which is a pixel portion
00.

The portable information terminal includes a CPU 603 for controlling each unit, a RAM 602 as a storage unit, a frame memory 605, an I / O port 601, and a D / D for converting a digital signal from the frame memory 605 into an analog signal. / A604 and LC for controlling the operation of dot sequential LCD
And a D controller 400.

Here, the frame memory 605 is stored in the CPU 6
Since still images such as characters and figures generated in 03 are mainly displayed, they are arranged in a form to be displayed on a display.
In addition, as the overall operation, first, the (m-1) frames are thinned out of the m frames on the writing side on the writing side, and the timing on the reading side is adjusted to the timing of the first or second embodiment described above. I just need.

As described above, the active matrix display device of the present invention reduces the dot clock frequency to 1 /
(The number of horizontal scanners). This reduces power consumption and makes it possible to make the flicker frequency inconspicuous while reducing the frame frequency to 1 / (the number of horizontal scanners).

The active matrix display device of the present invention has a configuration in which pixels adjacent to the left and right are written in one or more fields. This prevents a decrease in contrast due to fluctuations in the driving voltage during the row inversion driving, and allows the pixels to be driven only by the row inversion driving, so that the driving circuit can have a simple circuit configuration.

[0062]

As described above, the active matrix display device of the present invention has a configuration in which a video signal of one frame is divided into a plurality of subfields by a plurality of horizontal scanning circuits and written into pixels. As a result, the driving frequency is reduced, so that the power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a principle diagram of an active matrix display device of the present invention.

FIG. 2 is a flowchart illustrating an operation procedure of the active matrix display device.

FIG. 3 is a detailed configuration diagram of an active matrix display device.

FIG. 4 is a diagram illustrating phases of a horizontal clock and a horizontal start signal.

FIG. 5 is a diagram illustrating a phase of a horizontal start signal.

FIG. 6 is a diagram showing how a video signal is written to a panel.

FIG. 7 is a diagram illustrating a phase of a horizontal start signal.

FIG. 8 is a diagram illustrating a state in which a video signal is written to a panel.

FIG. 9 is a diagram illustrating an AC inversion phase of a video signal.

FIG. 10 is a diagram showing a flicker frequency.

FIG. 11 is a diagram showing the phase of a horizontal start signal.

FIG. 12 is a diagram illustrating a manner in which a video signal is written to a panel.

FIG. 13 is a diagram illustrating a phase of a horizontal start signal.

FIG. 14 is a diagram showing how a video signal is written to a panel.

FIG. 15 is a diagram illustrating a switching order of a plurality of horizontal scanners.

FIG. 16 is a diagram illustrating a case where the present invention is used for a portable information terminal.

FIG. 17 is a configuration diagram of a dot sequential drive type polysilicon TFT active matrix liquid crystal display.

FIG. 18 is a diagram showing how pixel voltages are written by dot sequential driving.

FIG. 19 is a line sequential drive type amorphous silicon TFT.
FIG. 2 is a configuration diagram of an active matrix liquid crystal display.

FIG. 20 is a diagram showing how pixel voltages are written by line-sequential driving.

[Explanation of symbols]

1 ... vertical scanning circuit, 2 ... horizontal switch group, 3a, 3
b, .about.3 m... horizontal scanning circuit, 4... startup control circuit.

Claims (4)

[Claims] 1. A row-shaped gate line, a column-shaped signal line, a matrix-shaped pixel arranged at each intersection of the two, and a line-sequential scanning of the gate line to scan one row every one horizontal period. A vertical scanning circuit for selecting the pixels, a horizontal switch group connected to one end of the signal line and supplying an external video signal to the signal line, and receiving a start signal. A plurality of horizontal scanning circuits for controlling the opening / closing operation of the horizontal switch group so that the video signal of one frame is divided into a plurality of subfields and written to the pixels later; and a start control of the plurality of horizontal scanning circuits. And an activation control circuit for outputting the activation signal for performing the activation. 2. The method according to claim 1, wherein the plurality of horizontal scanning circuits write the pixels in one horizontal scanning circuit for two or more horizontal periods.
2. The active matrix display device according to claim 1, wherein said upper and lower pixels are written with opposite polarities. 3. The activation control circuit according to claim 1, wherein the activation control circuit is configured to output one horizontal period to
2. The active matrix display device according to claim 1, wherein activation control of the plurality of horizontal scanning circuits is performed during an arbitrary period up to a frame. 4. The active matrix display device according to claim 1, wherein said activation control circuit performs activation control of said plurality of horizontal scanning circuits in an arbitrary order.