JPH10177357A - Manufacture of plane display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the device inexpensive by supplying a signal for inspection from a probe for inspection to a 1st and a 2nd electrode wire and performing inspection, and disconnecting a 1st and a 2nd display area. SOLUTION: Select pulses are applied in order from a probe for scanning line inspection to scanning lines 521 of 1st and 2nd array substrates 5005a and 500b and specific electric charges are written to a corresponding auxiliary capacitor from a probe for signal line inspection. The electric charges held by the auxiliary capacitor are read out and compared with reference electric charges to perform inspection including characteristics of respective TFTs 531. After the inspection, scanning line connection pads 525 and 529, a 2nd scanning line electrostatic protecting circuit 123, and a 2nd ring-shaped conductor 111 which are arranged on the left side of a seal area 601 are removed together with the substrates. Then a signal line connection pad 515, a 2nd signal line electrostatic protecting circuit 121, and a 2nd corresponding ring-shaped conductor 111 which are arranged above the seal area 601 are removed together with the substrate, and the 1st and 2nd array substrates 500a and 500b are separated between the seal area 601 and an oblique wiring part 511c.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a flat panel display, and more particularly to a method for inspecting the same.

[0002]

2. Description of the Related Art In recent years, flat display devices typified by liquid crystal display devices have been developed with a focus on small size, light weight, and low power consumption. The liquid crystal display device includes, for example, an array substrate in which a plurality of signal lines and scanning lines are arranged in a matrix on an insulating substrate, and pixel electrodes are arranged near switch points via switching elements, and a transparent substrate is provided on the insulating substrate. It includes a counter substrate on which a counter electrode made of an electrode material is arranged, and a liquid crystal material sandwiched between the substrates.

The signal lines and the scanning lines are respectively drawn out of the display area, and are connected to connection pads for making an electrical connection with an external circuit or the like. In such a display device, in particular, an array substrate which is a matrix wiring substrate has a problem that the signal line or the scanning line is disconnected or short-circuited due to the influence of static electricity generated during manufacturing or the influence of foreign matter such as dust, and furthermore, a switch is provided. The characteristics of the element may vary. It is desirable that such an array substrate with a defect be detected early and removed from the process, and it is known that the array substrate is inspected during manufacturing.

[0004]

However, in recent years,
Due to the demand for lowering the cost of flat panel display devices, it is necessary to reduce manufacturing costs and improve productivity. However, with the increase in the definition of the apparatus, the above-described inspection has required a great amount of time.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned technical problem, and a flat display in which the productivity is improved by shortening the inspection time and the cost of the apparatus is thereby reduced. It is an object of the present invention to provide a method for manufacturing a device.

[0006]

According to a first aspect of the present invention, there is provided a first display area and a second display area each including a plurality of pixel electrodes arranged on an insulating substrate; A plurality of first electrode lines electrically connected to a pixel electrode and both ends of which extend outside the first display region; and a second display region electrically connected to the pixel electrode in the second display region A plurality of second electrode wirings, both ends of which extend outward, and one end of each of the first electrode wiring and the second electrode wiring, which is disposed between the first display area and the second display area. Contacting a test probe with the first pad of the electrode substrate having a first pad electrically connected thereto; and transmitting a test signal from the test probe to the first electrode wiring and the second electrode wiring. Process of supplying and inspecting each of , In the manufacturing method of the flat display device, characterized in that in that it comprises a step of disconnecting the said first display area and the second display area.

According to a second aspect of the present invention, the first pad is a connection pad for obtaining an electrical connection with an external circuit corresponding to the first display area or the second display area. 2. The method for manufacturing a flat display device according to claim 1, wherein:

According to a third aspect of the present invention, a second pad corresponding to the first electrode wiring is disposed between the first pad and the first display area. Item 1. A method for manufacturing a flat panel display according to item 1.

According to a fourth aspect of the present invention, a third pad for obtaining an electrical connection with an external circuit is arranged at the other end of the first electrode wiring corresponding to the first display area. 4. The flat display device according to claim 3, wherein the first pad is a connection pad for obtaining an electrical connection with an external circuit corresponding to the second display area. In the way.

According to a fifth aspect of the present invention, the second pad is arranged at a pitch larger than a pad pitch of the first pad and the third pad. A method for manufacturing a display device.

According to a sixth aspect of the present invention, in the first display area, a third electrode wiring substantially orthogonal to the first electrode wiring and a vicinity of an intersection of the first electrode wiring and the third electrode wiring. A switching element electrically connected to the pixel electrode, a fourth electrode wiring substantially orthogonal to the second electrode wiring in the second display area, the second electrode wiring, and the fourth electrode wiring; 2. The method according to claim 1, further comprising a switch element electrically connected to the pixel electrode and disposed near the intersection of the pixel electrodes.

[0012] In the invention described in claim 7, the first electrode wiring and the second electrode wiring are signal lines, respectively.
7. The method according to claim 6, wherein the third electrode wiring and the fourth electrode wiring are scanning lines, respectively.

[0013] In the invention described in claim 8, the first electrode wiring and the second electrode wiring are scanning lines, respectively.
7. The method according to claim 6, wherein the third electrode wiring and the fourth electrode wiring are signal lines, respectively.

According to a ninth aspect of the present invention, the first display area and the second display area each including a plurality of pixel electrodes arranged on an insulating substrate, and the pixel electrodes of the first display area are electrically connected to each other. A plurality of first electrode wirings connected to each other and both ends of which extend outside the first display area; and both ends electrically connected to the pixel electrodes of the second display area and both ends of which extend outside the second display area. A plurality of second electrode wirings, one end of which is electrically connected to one end of the first electrode wiring;
Contacting an inspection probe with the first pad of the electrode substrate having a first pad electrically connected to the other end of the first electrode wiring; and A step of supplying a signal to the second electrode wiring via the first electrode wiring and the first electrode wiring to perform inspection, and a step of separating the first display area from the second display area. A method for manufacturing a flat panel display device characterized by the following.

The invention described in claim 10 is the first invention.
The method according to claim 9, wherein a second pad is disposed between the one end of the electrode wiring and the one end of the second electrode wiring.

The invention described in claim 11 is the first invention.
The pad is a connection pad for obtaining an electrical connection with an external circuit corresponding to the first display area, and the second pad is for establishing an electrical connection with an external circuit corresponding to the second display area. The method for manufacturing a flat display device according to claim 10, wherein the connection pad is a connection pad for obtaining the same.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing method according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic front view of a large-format array substrate (100). From the large-format array substrate (100), for example, a first array substrate (500a) and a second array substrate (500b) having substantially the same configuration are shown. ) Can be obtained.

The large-format array substrate (100) includes (800 × 3) signal lines (511) forming the first array substrate (500a).
600 scanning lines (521). One end of the signal line (511) is connected to a first signal line connection pad (513) via an oblique wiring portion (511a), and the other end is connected to a second signal line via an oblique wiring portion (511b). Connected to pad (515). One end of the scanning line (521) is connected to the first scanning line connection pad (523) via the oblique wiring portion (521a), and the other end is connected to the oblique wiring portion (5
21b) to the second scanning line connection pad (525).

Further, the large-format array substrate (100)
(800 × 3) signal lines (51) forming an array substrate (500b)
1) and 600 scanning lines (521). This signal line (51
1) is connected to the first side through the oblique wiring portion (511c).
The other end is connected to a third signal line connection pad (517) via an oblique wiring portion (511d). One end of the scanning line (521) is connected to the first scanning line connection pad (527) via an oblique wiring portion (521c), and the other end is connected to the first scanning line connection pad (527d) via an oblique wiring portion (521d). It is connected to two scan line connection pads (529).

In the vicinity of the intersection between the signal line (511) and the scanning line (521) in each of the seal areas (601) of the first array substrate (500a) and the second array substrate (500b),
A TFT (531) having a gate electrode connected to the scanning line (521) and a drain electrode connected to the signal line (521) is arranged. A pixel electrode (541) made of ITO is connected to the source electrode of each TFT (531), and a display area (551) is formed by these pixel electrodes (541). Here, each pixel electrode (54
1) has an auxiliary capacitor (not shown) formed between the adjacent scanning line (521) via an insulating film. The storage capacitor may be formed between independent storage capacitor lines. The TFT (531) uses an amorphous silicon (a-Si: H) thin film as a semiconductor layer. Even if the semiconductor layer uses polysilicon (p-Si), a compound semiconductor, or the like, I don't care.

Each of the seal area (601) and the display area (5
51), a ring-shaped first conductor ring (561) is arranged, and each signal line (511) and the first conductor ring (561) form a first signal line electrostatic protection circuit (563). Each scanning line (521) and the first conductor ring (561) are electrically connected via a first scanning line electrostatic protection circuit (565). The first signal line electrostatic protection circuit (563) and the first scanning line electrostatic protection circuit (565) are composed of a pair of two-terminal TFTs whose gates and sources are short-circuited and connected in parallel with each other, in a normal operating state. , That is, a potential difference of about several tens of volts, the wires (511) and (521) and the first conductor ring (56)
1) has a high resistance that does not conduct with, that is, a resistance of about 500 KΩ. TFTs constituting the first signal line electrostatic protection circuit (563) and the first scanning line electrostatic protection circuit (565) are as follows:
It is formed in the same step as the TFT (531) arranged in the display area (551). When a high potential difference occurs between one signal line (511) and one scanning line (521) due to the influence of static electricity generated during manufacturing, the first signal line electrostatic protection circuit (563) or the first scanning line The TFT constituting the line electrostatic protection circuit (565) is turned on. As a result, the charged electric charge is transferred from the first conductor ring (561) to the adjacent signal line (511) or scanning line (52).
1) to reduce the potential difference generated locally and prevent the occurrence of dielectric breakdown and the like.

The second signal line connection pad (515), the third signal line connection pad (517), the first scan line connection pads (523), (527) and the second scan line connection of the large format array substrate (100). pad
A ring-shaped second conductor ring (111) is arranged on the outer peripheral portion of (525), (529), and each connection pad (515), (517), (523),
(525), (527), (529) and the second conductor ring (111) are connected to the second signal line electrostatic protection circuit (121) or the second scanning line electrostatic protection circuit.
(123). Second signal line electrostatic protection circuit (121) and second scanning line electrostatic protection circuit (123)
The TFT (5) in the display area (551) is similar to the first signal line electrostatic protection circuit (563) and the first scanning line electrostatic protection circuit (565).
31) It is composed of a pair of two-terminal TFTs that are short-circuited between the gate and source and are connected in parallel with each other, which are manufactured in the same process as in 31). It has such a high resistance as not to conduct each wiring and the second conductor ring, that is, about 500 KΩ. Similarly to the first signal line electrostatic protection circuit (563) and the first scanning line electrostatic protection circuit (565), one signal line (511) and one scanning line (521) are connected to each other by the influence of static electricity generated during manufacturing. If a high potential difference occurs between the second signal line electrostatic protection circuit (12
1) Alternatively, the TFT constituting the second scanning line electrostatic protection circuit (123) is turned on. As a result, the charged electric charge is dispersed from the second conductor ring (111) to the adjacent signal line (511) or scanning line (521), thereby mitigating a locally generated potential difference and preventing the occurrence of dielectric breakdown or the like. I do.

In this embodiment, the first conductor ring (56
The second conductor ring (111) is provided together with the substrate (10).
This is because the arrangement of the conductor ring on the outer peripheral side of 1) is more effective in reducing the influence of static electricity.

After the above-described large-format array substrate (100) is formed, in this embodiment, the connection pads (52) corresponding to the scanning lines (521) of the first array substrate (500a) of the large-format array substrate (100) are used.
5) A scanning line inspection (not shown) for sequentially applying a selection pulse to each of the scanning lines (521) to each of the connection pads (529) corresponding to the scanning lines (521) of the second array substrate (500b). Contact the probe. At the same time, the first array substrate (500
a) A signal line inspection probe capable of applying a predetermined voltage is brought into contact with a connection pad (511) common to the signal line (521) of the second array substrate (500b) and the second array substrate (500b).

In such a state, the first array substrate
As shown in FIG. 3, selection pulses are sequentially applied to the scanning line (521) of the (500a) and the scanning line (521) of the second array substrate (500b) from the scanning line inspection probe, as shown in FIG. A predetermined charge is written from the probe to the storage capacitor corresponding to each pixel electrode (541).

After a lapse of a predetermined time, the first array substrate
Here, a selection pulse is sequentially applied from the scanning line inspection probe to the scanning line (521) of the (500a) and the scanning line (521) of the second array substrate (500b). 541) The charges held in the storage capacitors corresponding to (1) are sequentially read.

By comparing the read charge with a reference charge, an inspection including the characteristics of each TFT (531) is performed. The evaluation including the characteristics of the TFT (531) may be a charge amount, a voltage or a current. Also, here, the first array substrate (500a) and the second array substrate (500b) have different storage periods for the respective auxiliary capacitors, so that the inspection criteria of the first array substrate (500a) and the second array substrate (500a) are different. The inspection standard of the substrate (500b) is made different in consideration of the difference in the holding period.

Here, the defective TFT (531) may be separated from the signal line (511) or the scanning line (521) by irradiating a laser or the like, or the TFT (531) may be separated from the signal line (511) and the pixel electrode (51). 541) Repair processing such as short-circuiting may be performed.

After the inspection as described above, if the liquid crystal display device (1) shown in FIG. 2 is to be produced, for example, the liquid crystal display device (1) shown in FIG. 1 is prepared based on a pair of cut line marks (141a) and (141b) shown in FIG. The scanning line connection pads (525) and (529) arranged on the left side of each seal area (601), the second scanning line electrostatic protection circuit (1
23) and the second ring-shaped conductor (111) are removed together with the substrate. These cut line marks (141a) and (141b)
Since it is important to align the scanning line (521) and the scanning line connection pads (525), (529), etc., use the same material as the scanning line (521) and pattern it at the same time as patterning the scanning line (521). Is desirable. As in this embodiment, the cut position is determined by the oblique wiring portion (521) between the seal area (601) and the scanning line (521).
It is desirable that the area be a parallel wiring area between b) and (521d) in order to prevent a short circuit between the adjacent scanning lines (521). In addition, at least a protective film disposed on the scanning line (521) at the cut position reduces a short circuit between adjacent scanning lines (521) at the time of cutting. In addition, scan lines (5
21) has a multilayer structure of a plurality of metal layers for the purpose of lowering resistance and improving reliability, the scanning line (521) in the region corresponding to the cut position should be a single-layered structure. 52
1) It is desirable to prevent short circuit between them.

Thereafter, based on the pair of cut line marks (131a) and (131b) shown in FIG.
The signal line connection pad (515) disposed above, the second signal line electrostatic protection circuit (121) and the corresponding second ring-shaped conductor (1
11) is removed together with the substrate.

Subsequently, a pair of cut line marks (131
c) Based on (131d), seal area (601) and diagonal wiring
(511c) between the first array substrate (500a) and the second array substrate
(500b).

The cut line marks (131a), (131b),
(131c) and (131d) are signal lines (511) and signal line connection pads
(515) It is important to align with the signal line (51
It is desirable to use the same material as in 1) and pattern it at the same time as patterning the signal line (511). The cutting position is, as in this embodiment, the seal area (601) and the signal line (5).
A parallel wiring area between the oblique wiring portions (511b) and (511c) of (11) is desirable in order to prevent a short circuit between the adjacent signal lines (511). Further, at least a protective film such as an insulating film is disposed on the signal line (511) at the cut position, so that a short circuit between adjacent signal lines (511) at the time of cutting is reduced. Further, when the signal line (511) has a multilayer structure of a plurality of metal layers for lowering resistance and improving reliability, the signal line (511) in a region corresponding to the cut position may have a single-layer structure. It is desirable to prevent a short circuit between adjacent signal lines (511).

The edge (1) of the substrate thus taken out
The second signal line electrostatic protection circuit (121) and the second ring-shaped conductor (111) connected to the remaining signal line connection pads (517) are removed by chamfering the end faces along 01a) and (101b). Then, the second scanning line electrostatic protection circuit (123) and the second ring-shaped conductor (111) connected to the remaining scanning line connection pads (523) and (527) are removed, and the array substrates (500a) and ( Complete 500b). Here, the second signal line static electricity protection circuit (121), the second scanning line static electricity protection circuit (123), and the second ring-shaped conductor (111) which have been removed by chamfering have been removed. Irradiation and removal may be performed.

As described above, the array substrates (500a) and (500b) used in the liquid crystal display device (1) shown in FIG. 2 are prepared. Thereafter, according to a conventional method, as shown in FIG. 2, an array substrate (500a) ((500b)) and a counter substrate (800) are arranged to face each other via a liquid crystal layer (not shown), and a liquid crystal panel (3) is formed. Create Further, one end (501) of the array substrate (500a) ((500b))
a) Connect eight X-TABs (901-1), ..., (901-8) to the signal line (5
11) Electrically connect to each X-TAB (901)
A circuit board (not shown) connected to -1),..., (901-8) is arranged on the back side of the array board (500a) ((500b)). In addition, two Y-TABs (903-1) and (903-2) are connected to the other end (501b) of the array substrate (500a) ((500b)) by scanning lines (521) (see FIG. 1). To the Y-TAB (903-1), (903
-2) Connect the circuit board (not shown) connected to the array board (5
00a) ((500b)) The liquid crystal display device (1) shown in FIG.

As described in detail above, according to this embodiment, inspection charges are simultaneously written on the first array substrate (500a) and the second array substrate (500b) of the large-format array substrate (100), respectively. And will be inspected based on this,
Even if the number of pixels on the first array substrate (500a) and the second array substrate (500b) increases, the time required for the inspection is greatly reduced as compared with the related art.

In this embodiment, the signal line inspection probe is connected between the signal line (511) of the first array substrate (500a) and the signal line (511) of the second array substrate (500b). It has contacted the pad (513), but may contact the connection pad (515) or the connection pad (517). However,
As in this embodiment, a connection pad (513) is provided between the signal line (511) of the first array substrate (500a) and the signal line (511) of the second array substrate (500b). The first array substrate (500a) and the second array substrate (5
Since substantially the same electric charge is written to each of the auxiliary capacitors in 00b), there is no need to set a test standard in consideration of the time constant of the wiring and the like.

Further, according to the above-described embodiment, a pair of cut line marks (131a), (131b), (131c), (131d) and
Based on (141a) and (141b), unnecessary areas were removed and separated, and array substrates (500a) and (500b) suitable for the liquid crystal display device (1) shown in FIG. 2 were prepared. As shown, the cut line marks (131a), (131b), (131c), (131d) and (1
By arranging 41a) and (141b) and removing and separating unnecessary areas, it is possible to easily produce a liquid crystal display device of another specification having a different connection pad position from the above embodiment.

If there is no request to create a liquid crystal display device having different specifications, the liquid crystal display device can be configured as shown in FIG. 5, for example. Here, (519) in the figure is a test pad for contacting the test probe. This inspection probe (519)
Indicates that the signal line of the first array substrate (500a) is
11a) is electrically connected. Similarly, inspection probe
(519) designates a signal line of the second array substrate (500b) as an oblique wiring area (511c), a connection pad (513) and an oblique wiring area (511e).
Are electrically connected via This test pad (51
9) is formed larger than the pitch of the connection pads (513) and (515) so that the contact of the inspection probe is easy.
In addition, by using a common specification for each board that allows a common inspection probe specification even for boards with different pitches of the connection pads (513) and (515), It is possible to prepare an inspection probe and eliminate the need for replacement.

Next, another embodiment of the present invention will be described. This embodiment is different from the above embodiment in that a first array substrate (500a) and a second array substrate (500a) are mounted on a large-format array substrate (100) as shown in FIG.
The difference is that the array substrate (500b) is arranged and inspected. That is, the first array substrate (5) of the large-format array substrate (100)
A connection pad (523) corresponding to the scanning line (not shown) of the second array substrate (500b) and the scanning line (not shown) of the second array substrate (500b)
Then, although not shown, a scanning line inspection probe capable of sequentially applying a selection pulse to each scanning line (521) is abutted. At the same time, the connection pad (515) corresponding to the signal line (not shown) of the first array substrate (500a) and the connection pad (519) corresponding to the signal line (not shown) of the second array substrate (500b) are connected. The signal line inspection probes to which a predetermined voltage can be applied are brought into contact with each other.

In such a state, the first array substrate
As shown in FIG. 7, a selection pulse is sequentially applied to the scanning line (521) of the (500a) and the scanning line (521) of the second array substrate (500b) from the scanning line inspection probe as shown in FIG. A predetermined charge is written from the probe to the storage capacitor corresponding to each pixel electrode (541).

After a lapse of a predetermined time, the first array substrate
(500a) and a scanning pulse (521) of the second array substrate (500b) are sequentially applied with a selection pulse from a scanning line inspection probe to a storage capacitor corresponding to each pixel electrode (541) from the signal line inspection probe. The stored charges are read out in order.

By comparing the read charge with a reference charge, an inspection including the characteristics of each TFT (531) is performed. Then, a pair of cut line marks (1
Based on (31a), (131b), (141a), (141b) and (141c), (141d), unnecessary areas are removed and separated, and an array substrate suitable for the liquid crystal display device (1) shown in FIG. (500a), (500b)
Create

According to such a configuration, the period for reading out charges can be further shortened as compared with the above-described embodiment, so that the time required for inspection can be further reduced. Further, similarly to the above-described embodiment, the cut line mark (131
By changing the positions of (a), (131b), (141a), (141b) and (141c), (141d), liquid crystal display devices having different specifications can be easily produced.

Further, the scanning line inspection probe includes a scanning line (not shown) of the first array substrate (500a) and a second array substrate (5).
Although the contact pad (523) arranged between the scanning line (not shown) and the scanning line (00b) is contacted, it may contact the connection pad (525) or the connection pad (527). However,
As in this embodiment, the scanning line inspection probe is brought into contact with the connection pad (523) disposed between the scanning lines of the first array substrate (500a) and the second array substrate (500b), thereby making the first array substrate (500a) and the auxiliary capacitance of the second array substrate (500b) include:
Since the charges are written in each of them with substantially the same selection period, it is not necessary to set the inspection standard in consideration of the time constant of the wiring and the like.

In each of the above-described embodiments, the large-format array substrate (100) includes the first array substrate (500a) and the second array substrate (5).
Although the case where the third array substrate (500b) is included has been described, the configuration may further include a third array substrate (500c) and a fourth array substrate (500d) as shown in FIG. Also in this case, similarly to the above-described embodiment, the first array substrate (500a) of the large-format array substrate (100) is used.
The connection pad (523) corresponding to the scanning line (not shown) of the second array substrate (500b) and the scanning line (not shown) of the second array substrate (500b) is not shown, but a selection pulse is sequentially applied to each scanning line (521). Line inspection probe and third array substrate
(500c) scan line (not shown) and fourth array substrate (500d)
Connection pads (52) corresponding to the scanning lines (not shown)
Although not shown in 3 '), a scanning line inspection probe which enables the application of a selection pulse to each scanning line (521) is brought into contact with each scanning line (521). At the same time, connection pads corresponding to signal lines (not shown) of the first array substrate (500a) and the third array substrate (500c).
(513), the second array substrate (500b) and the fourth array substrate (500b).
A signal line inspection probe capable of applying a predetermined voltage is brought into contact with each of the connection pads (517) corresponding to the signal line (not shown) of d), and the inspection is performed in the same manner as described above.
Again, the time required for the inspection can be reduced.

Also in this case, by removing and separating the unnecessary area according to the demand, an array substrate suitable for a desired liquid crystal display device can be produced without performing a new design or the like.

[0047]

According to the present invention, the inspection time can be greatly reduced, and thereby the productivity of the flat panel display can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic front view of a large-format array substrate according to one embodiment of the present invention.

FIG. 2 is a schematic perspective view of a liquid crystal display device according to one embodiment of the present invention.

FIG. 3 is a diagram showing an inspection timing of the large-sized array substrate in FIG. 1;

FIG. 4 is a diagram illustrating another separation of the large-sized array substrate in FIG. 1;

FIG. 5 is a schematic front view of a large format array substrate according to another embodiment of the present invention.

FIG. 6 is a schematic front view of a large format array substrate according to another embodiment of the present invention.

FIG. 7 is a diagram showing an inspection timing of the large-sized array substrate in FIG. 6;

FIG. 8 is a schematic front view of a large-size array substrate according to another embodiment of the present invention.

[Explanation of symbols]

(1)… Liquid crystal display device (131a), (131b), (131c), (131d), (141a), (141b)… Cut line mark (500a), (500b)… Array substrate (511)… Signal line (513), (513 '), (515), (515'), (517), (517 ') ... Signal line connection pad (521) ... Scanning line (523), (523'), (525), (525 '), (527), (527')… Scan line connection pad

Claims (11)

[Claims] A first display area and a second display area each including a plurality of pixel electrodes arranged on an insulating substrate; and a first display area that is electrically connected to the pixel electrodes of the first display area and that is outside the first display area. A plurality of first electrode wirings, both ends of which are respectively extended; and a plurality of second electrodes electrically connected to the pixel electrodes of the second display region, and both ends of which extend outside the second display region, respectively. An electrode comprising: a wiring; and a first pad disposed between the first display area and the second display area and electrically connected to one end of each of the first electrode wiring and the second electrode wiring. Contacting an inspection probe with the first pad of the substrate, supplying an inspection signal from the inspection probe to each of the first electrode wiring and the second electrode wiring, and performing an inspection; A display area and the second display area Manufacturing method of a flat display device, characterized in that in that it comprises a step of disconnecting, the. 2. The device according to claim 1, wherein the first pad is a connection pad for obtaining an electrical connection with an external circuit corresponding to the first display area or the second display area. The manufacturing method of the flat panel display according to the above. 3. The flat display device according to claim 1, wherein a second pad corresponding to the first electrode wiring is disposed between the first pad and the first display area. Production method. 4. A third pad for obtaining an electrical connection with an external circuit corresponding to the first display region is provided at another end of the first electrode wiring, and the first pad is 4. The method according to claim 3, wherein reference numerals denote connection pads for obtaining an electrical connection with an external circuit corresponding to the second display area. 5. The method according to claim 4, wherein the second pads are arranged at a pitch larger than a pad pitch of the first pad and the third pad. 6. A third electrode wiring substantially orthogonal to the first electrode wiring in the first display area, and electrically connected to the pixel electrode near an intersection of the first electrode wiring and the third electrode wiring. A switching element arranged and arranged; a fourth electrode wiring substantially orthogonal to the second electrode wiring in the second display area; and a pixel electrode near an intersection of the second electrode wiring and the fourth electrode wiring. 2. The method for manufacturing a flat display device according to claim 1, further comprising a switch element electrically connected and arranged. 7. The device according to claim 6, wherein the first electrode wiring and the second electrode wiring are signal lines, respectively, and the third electrode wiring and the fourth electrode wiring are scanning lines, respectively. A method for manufacturing a flat display device. 8. The device according to claim 6, wherein the first electrode wiring and the second electrode wiring are scanning lines, respectively, and the third electrode wiring and the fourth electrode wiring are signal lines, respectively. A method for manufacturing a flat display device. 9. A first display area and a second display area each including a plurality of pixel electrodes arranged on an insulating substrate, and electrically connected to the pixel electrodes of the first display area and outside the first display area. A plurality of first electrode wirings, both ends of which are respectively extended; and both ends which are electrically connected to the pixel electrodes of the second display area and extend outside the second display area, respectively.
A plurality of second electrode lines each having one end electrically connected to one end of the first electrode line; and a first pad electrically connected to another end of the first electrode line. Contacting an inspection probe with the first pad of the electrode substrate; and supplying an inspection signal from the inspection probe to the second electrode wiring via the first electrode wiring and the first electrode wiring, respectively, for inspection. And a step of separating the first display area and the second display area from each other. 10. The method according to claim 9, wherein a second pad is disposed between the one end of the first electrode wiring and the one end of the second electrode wiring. . 11. The first pad is a connection pad for obtaining an electrical connection with an external circuit corresponding to the first display area, and the second pad is corresponding to the second display area. 11. The method according to claim 10, wherein the connection pad is a connection pad for obtaining an electrical connection with an external circuit.