JPH10172966A - 集積回路絶縁体及びその製法 - Google Patents

集積回路絶縁体及びその製法

Info

Publication number
JPH10172966A
JPH10172966A JP9307308A JP30730897A JPH10172966A JP H10172966 A JPH10172966 A JP H10172966A JP 9307308 A JP9307308 A JP 9307308A JP 30730897 A JP30730897 A JP 30730897A JP H10172966 A JPH10172966 A JP H10172966A
Authority
JP
Japan
Prior art keywords
polymer
metal
fluorine
parylene
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9307308A
Other languages
English (en)
Japanese (ja)
Inventor
J Taylor Kelly
ジェイ.テイラー ケリー
Eisa Mona
エイサ モナ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JPH10172966A publication Critical patent/JPH10172966A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
JP9307308A 1996-11-08 1997-11-10 集積回路絶縁体及びその製法 Pending JPH10172966A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US029749 1993-03-11
US2974996P 1996-11-08 1996-11-08

Publications (1)

Publication Number Publication Date
JPH10172966A true JPH10172966A (ja) 1998-06-26

Family

ID=21850685

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9307308A Pending JPH10172966A (ja) 1996-11-08 1997-11-10 集積回路絶縁体及びその製法

Country Status (3)

Country Link
JP (1) JPH10172966A (ko)
KR (1) KR19980042229A (ko)
TW (1) TW382762B (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1018527A2 (en) * 1998-12-09 2000-07-12 Applied Materials, Inc. Nano-porous copolymer films having low dielectric constants
WO2001084626A1 (en) * 2000-04-28 2001-11-08 Tokyo Electron Limited Semiconductor device having a low dielectric film and fabrication process thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1018527A2 (en) * 1998-12-09 2000-07-12 Applied Materials, Inc. Nano-porous copolymer films having low dielectric constants
EP1018527A3 (en) * 1998-12-09 2004-10-27 Applied Materials, Inc. Nano-porous copolymer films having low dielectric constants
WO2001084626A1 (en) * 2000-04-28 2001-11-08 Tokyo Electron Limited Semiconductor device having a low dielectric film and fabrication process thereof

Also Published As

Publication number Publication date
TW382762B (en) 2000-02-21
KR19980042229A (ko) 1998-08-17

Similar Documents

Publication Publication Date Title
US6265303B1 (en) Integrated circuit dielectric and method
US6351039B1 (en) Integrated circuit dielectric and method
US6030706A (en) Integrated circuit insulator and method
US5759906A (en) Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits
US5393708A (en) Inter-metal-dielectric planarization process
US6265321B1 (en) Air bridge process for forming air gaps
KR100372216B1 (ko) O.5 및 0.5 미크론 이하의 ulsi 회로용 인터레벨 유전체소자로서의수소실세큐옥산계유동가능한산화물
EP0881678A2 (en) Improvements in or relating to porous dielectric structures
US6287979B1 (en) Method for forming an air gap as low dielectric constant material using buckminsterfullerene as a porogen in an air bridge or a sacrificial layer
US6291334B1 (en) Etch stop layer for dual damascene process
US7564136B2 (en) Integration scheme for Cu/low-k interconnects
US6599839B1 (en) Plasma etch process for nonhomogenous film
US6114186A (en) Hydrogen silsesquioxane thin films for low capacitance structures in integrated circuits
US6278174B1 (en) Integrated circuit insulator and structure using low dielectric insulator material including HSQ and fluorinated oxide
JPH10178006A (ja) 集積回路誘電体
US6905964B2 (en) Method of fabricating self-aligned metal barriers by atomic layer deposition on the copper layer
MXPA97007616A (en) A method to manufacture an integrated circuit structure inter-levels of low constant dielectr
JP2001168193A (ja) バイア被毒を緩和しつつ金属ライン間にボイドフリー低k誘電性材料を提供する集積回路構造のための低K誘電性複合材層
US5639345A (en) Two step etch back process having a convex and concave etch profile for improved etch uniformity across a substrate
US5888905A (en) Integrated circuit insulator and method
US6284675B1 (en) Method of forming integrated circuit dielectric by evaporating solvent to yield phase separation
US6800928B1 (en) Porous integrated circuit dielectric with decreased surface porosity
US5482900A (en) Method for forming a metallurgy system having a dielectric layer that is planar and void free
JP3399154B2 (ja) 積層絶縁膜のプラズマエッチング方法
EP0911875A2 (en) Integrated circuit dielectric and method of fabrication thereof