JPH10172966A - Integrated circuit insulating body and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To delay a fluorine processing to be after evaporation and to more simply evaporate a polymer film from a precursor which is simpler by stacking the film of parylene which is fluorine-processed and the film of polymer and copolymer of the same group and, directly fluorine-processing the film. SOLUTION: A device 200 has a stack room 202 and the stack room 202 has two entrances having valves. One entrance is for comonomer vapor and the other is for parylene monomer. The parylene monomer is obtained by sublimating dimer in a room 204 and by making it into monomer by cracking in a furnace 206. The dimer of parylene is a solid in a room temperature and it can be sublimated under the vapor pressure of about 13 millimeters and at 120 deg.C. When a connection pipe and the stack room 202 are kept to about 120 deg.C, the condensation or polymerization of vapor on the surfaces is removed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly, to an insulator for an integrated circuit and a method of manufacturing the same.

[0002]

BACKGROUND OF THE INVENTION Integrated circuits include a source / drain formed on a silicon substrate, an insulated gate on the substrate, and a plurality of top coverages formed on multiple levels. Field effect transistors having metal (or polysilicon) interconnects are typically included.
The insulating layer is between the gate / source / drain and the wiring formed from the first metal level (premetal), as well as between successive metal levels (intermetal dielectric). Also exists. Each insulating layer must cover the relatively uneven topography of the metal level wiring, or the gate, which involves gaps between closely spaced wiring at the same metal level. included. Also, the dielectric constant of the insulating layer is determined by the capacitive coupling between closely spaced interconnects at the same metal level and at adjacent upper and lower overlying metal levels.
Must be low enough to effectively limit

[0003] Various approaches have been developed to form an insulating layer over the entire surface of the uneven topography. All of these approaches involve reflowing deposited borophosphosilicate glass (BPSG) (r
eflowing, typically using siloxane spin-on glass (SOG), plasma enhanced chemical vapor deposition (PECVD) using tetraethoxysilane (TEOS) Silicon dioxide (or silicon oxide) mold by spattering while depositing, etching back a stack of deposited glass and spun-on planarizing photoresist, and chemical-mechanical polishing (CMP). Is formed.

All of these approaches suffer from the relatively high dielectric constant of silicon dioxide (of the order of 3.9). Due to such a problem, wiring is closely packed,
And the way in which low capacitive coupling can still be maintained is limited.

"Laxman, low ε dielectric: C
VD Fluorine Treated Silicon Dioxide, 18 Semiconductor International 71 (May 1995), describes a fluorine treatment for use as an intermetal level dielectric having a dielectric constant much lower than that of silicon dioxide. Reports on spent silicon dioxide are summarized. In particular, according to PECVD using a source gas of silicon tetrafluoride (SiF ₄ ), silane (SiH ₄ ), and oxygen (O ₂ ), fluorine is 10% or less, 3.0 to 3.0%.
SiO _x F _y can be deposited with a dielectric constant in the range of 3.7. However, such a dielectric constant still limits the packing density of the wiring.

Organic polymer insulators offer another approach to low dielectric constant insulators. The formation by chemical vapor deposition (CVD) ensures the filling of gaps between closely spaced wires. Some integrated circuit manufacturing methods include polyimide as a protective overcoat. However, polyimide has a dielectric constant of only about 3.2 to 3.4, and an affinity to absorb water, which adversely affects post-processing when used as a metal interlayer insulating film. Polyimide has a positive temperature tolerance of about 500 ° C. or less.

[0007] Parylene is a general term for a class of poly-para-xylylenes having the following structure:

[0008]

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Such polymers have low dielectric constants (eg,
2.35-3.15), is a member of a system of thermoplastic polymers with low water affinity and is conformally from vapors that are solvent-free and do not require high-temperature curing. ) Can be deposited. Parylene having hydrogen on aliphatic carbon may be used at a temperature of about 400 ° C. or less under N ₂ atmosphere. On the other hand, if the aliphatic is perfluorinated, the effective temperature rises to about 530 ° C.

"You et al., Vapor Deposition of Films from Precursors, Chemical Perspectives o
f Microelectronic Materials III), Materials Research Society Symposiu
m Proceedings) (November 30, 1992) "starts with a liquid precursor of dibromotetra-fluoro-p-xylene and then deposits the precursor at 350 ° C on a substrate for -15 minutes.
Disclosed is a process for preparing fluorinated parylene by conversion to active monomers that adsorb and polymerize at <RTIgt; The reaction is considered as follows.

[0011]

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Yu et al. Synthesize the precursor from dialdehyde (terephthalaldehyde) as follows.

[0013]

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The benzene ring is also (partially) fluorinated by standard halogenation methods. Such fluorine treatment lowers the dielectric constant and raises the effective temperature. Polyethylene films may be deposited by using dimers of active monomers as intermediates. See U.S. Pat. No. 5,210,341 to Yu et al. And Dolbier et al. The reaction is as follows.

[0015]

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However, there are problems with such fluorinated polyene approaches, including the inefficient preparation of the precursor and the lack of commercially available precursors.

[0017]

SUMMARY OF THE INVENTION The present invention provides for the deposition of a fluorinated parylene and similar series of polymer and copolymer films, and then forming the film in two steps by direct fluorination. I do. Advantages of the present invention include depositing a polymer film from a simpler precursor more easily, with the fluorination delayed until after the deposition. In addition, the fluorine treatment after the deposition replaces hydrogen with fluorine, resulting in an increase in the volume of the film. That helps to fill narrow gaps and removes voids.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1-5 illustrate elevations of steps of a first preferred embodiment of a method for forming an insulator dielectric between a plurality of metal lines during the manufacture of an integrated circuit. A sectional view will be described. More specifically, a polysilicon gate 104 and a field oxide film 106 are formed on a silicon substrate 102.
Starting with the partially formed circuit of FIG. 1 having
Then, a premetal level dielec
tric) Under (PMD) 110, place metal lines 112-120 on PMD 110 and metal-filled vias 122-124 extending through PMD 110. PMD110
May be silicon dioxide or boron, phosphorus, etc., BP
SG-forming dopants may be included (the dopants help to capture mobile ions). In fact, PM
D110 may be a layered structure comprising silicon dioxide with undoped silicon dioxide in contact with the gate and BPSG over the undoped oxide. The metal lines may be made of TiN clad aluminum on the top and bottom. The metal lines 112 to 120 have a width of 0.25 to 0.5 mm.
5 μm, height 0.5 μm, only 0.25-0.5 μ between lines 112-116 and between lines 118-120
m. Thus, the dielectric constant of the insulator between the metal lines must be as small as possible to limit the capacitive coupling.

As shown in FIG. 2, a thickness of 0.15 to 0.25 μm is formed on the PMD 110 and the metal lines 112 to 120.
m (at least about 1.5 times the minute space between metal lines) is conformally deposited. Metal line 1
It should be noted that voids can occur when the deposition pinches off at the top of the microspace, as shown between 12 and 114. Also, some micro-spaces need not be completely filled, as shown between metal lines 114-116.

[0020] The deposition may be performed as in apparatus 200 shown in FIG.
Occurs in low pressure (about 13 mTorr) deposition equipment. Device 2
00 has a capacity for copolymer deposition, which can be used in an alternative embodiment, and with a simpler device:
It can be used for the preferred embodiment of the present invention. The apparatus 200 has a deposition chamber 202,
Has two inlets with valves. One inlet is for a comonomer vapor not used in this preferred embodiment and the other is for a parylene monomer. This parylene monomer has a dimer in the chamber 2
04 and then cracked in a furnace 206 to monomer. Parylene dimers are solid at room temperature and can be sublimed at 120 ° C. under a vapor pressure of about 13 mTorr. Maintaining the connecting tube and the deposition chamber 202 at about 120 ° C. eliminates vapor condensation or polymerization on their surfaces. Substrate 102
Is cooled to about -25 ° C., then the monomers polymerize on the exposed surface, and then an unsubstituted (unsubstituted) parylene (PA-N) film is conformally (confo).
rmally) grow. The heated cracker is about 660 ° C
Temperature. The substrate 102 has only its surface,
The vapor has been exposed to the monomer at a temperature low enough to condense or polymerize. The overall reaction is considered as follows.

[0021]

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The polymer-coated substrate is then subjected to a pressure of about 50-100 mTorr at room temperature for about 40-60
During a minute, it is exposed to a stream of 5% fluorine (F ₂ ) and 95% helium (as diluent). Fluorine is immediately replaced with aliphatic and / or aromatic hydrogen in the Parrelin membrane by the following reaction.

[0023]

Embedded image (In the formula, X represents H or F.)

Having an aromatic part, an aliphatic part and a non-fluorinated part by a fluorination reaction,
Any copolymer film 140 having a dielectric constant of about 2.3 to 2.4 (compared to the deposited Parrelin film 130 having a dielectric constant of about 2.7) results. Also, fluorination increases the volume (thickness) of the film by about 20-40%.
This depends on the degree of fluorination. Due to such an increase in volume, voids and gaps in the micro space are closed,
Thus, the problem of void formation by evaporation is substantially reduced. In fact, fluorine diffuses into the polymer and reaction products, and mainly HF diffuses out of the polymer and is pumped out. By annealing at about 400 ° C., the remaining volatiles are removed and the film 14
0 shrinks to 10% or less. No further shrinkage occurs with subsequent annealing.

After the formation of the fluorinated polymer 140, only the polymer enters the space between adjacent metal lines,
In some cases, fluorine or
Etch back polymer 140 using an oxygen-based plasma to obtain anisotropy. FIG. 4 shows the portion 142 of the polymer that has been etched back.

Next, a thick (1 μm or more) layer of an oxide film or a fluorinated oxide film is deposited by plasma enhanced CVD. Finally, the deposited oxide film is planarized by using CMP to leave a flat oxide film 150 as shown in FIG. Vias are formed in the oxide film 150 and through the vias to the metal lines 112-120, downwardly.
It may be formed in another metal wiring layer formed on 0. Thus, the fluorinated polymer 142 adjacent to the metal wire and the (fluorinated) oxide film 150 (dielectric constant of the fluorinated oxide film is about 3.5)
(The dielectric constant is 2.3 to 2.4) and the IMD is completed. The two-component IMD has a very low insulating polymer in the most critical areas, where the metal lines are very dense.

The degree of fluorination can be controlled by extending the time of exposing the parylene film to a fluorinated atmosphere, or by increasing its temperature, so that each of the four Substituting up to 4 fluorines and replacing up to 4 aliphatic fluorines on two carbons between consecutive benzene rings can produce perfluoroparylene. Conveniently, the temperature of the fluorination is less than about 35 ° C. The fluorination time depends on the film thickness, the desired degree of fluorination, temperature and pressure. Fully fluorinated perfluoropolymers are very reactive. Therefore, fluorination of only about 60-70% of all available positions (4 on each benzene ring and 4 on aliphatic between successive rings) is preferred.

The degree of fluorination can be determined by measuring the molar ratio of carbon to fluorine or carbon to hydrogen. Substitution of fluorine is quite variable. Therefore, the molar ratio is not usually an accurate fraction such as 8/5, which is the value when the fluorinated monomer is used for polymerization. For example, for a fluorinated monomer having four aliphatic carbons, the molar ratio of carbon to fluorine is 8/4
become.

Preparation of Precursors Parerelin dimer is a commercially available product at a price of less than $ 1 / g.

[0030] The variation polymers of the copolymer was deposited, preferred approach for fluorine treatment then, the polymer other than parylene (other monomers (their own, to fluorination may allow, it may not be possible monomer) (Including copolymers of parrelin). In fact, one or more of the monomers may be partially fluorinated, with fluorination after deposition causing the film to swell and reduce the dielectric constant.

Preferred Embodiment of Blanket Polymer FIG. 7 illustrates a second preferred embodiment method for making an IMD. Specifically, starting with the first preferred embodiment, as shown in FIGS.
The parrelin polymer 130 is deposited on the entire surface of the surface 2 to 120. Next, the polymer 130 is fluorinated to form a fluorinated polymer 140 as shown in FIG.

Next, a thickness of at least 1 μm is formed on the fluorinated polymer 140 (fluorinated).
An oxide layer 150 is deposited. Next, the oxide film 1 is formed by CMP.
50 is flattened (see FIG. 7). The oxide film may be redeposited by plasma enhanced deposition of TEOS to complete the intermetal dielectric. The metal interlayer insulating film includes a fluorinated parelin polymer 140 (dielectric constant of 2.3 to 2.4) adjacent to the metal line and a flattened oxide film 150 (dielectric constant of 3 .5
Or 4.0) of an undoped oxide film. Thus, IMDs have very low dielectric constants in the most critical areas and where there are complexities of flat oxide levels to make up the wiring. Also, the oxide film 150
And a vertical via passing through the fluorinated polymer 140
Provides interlevel connections.

Preferred Embodiments of Multiple Metal Layers FIGS. 8-10 show two successive applications of the first preferred embodiment of the IMF for two continuous metal layers. Specifically, FIG. 8 shows metal lines 412-4 on insulator 402.
Parylene 430 is shown conformally deposited over the entire surface of 20, then fluorinated and annealed. Metal lines 414-420 are about 0.25 μm wide, about 0.7 μm high, and about 0.25 μm apart; metal lines 412 are about 0.4 μm wide for vertical via connections. Represents the widening of the metal line. Also, the metal can be aluminum with a cladding such as TiN on both the top and bottom.

FIG. 9 shows the polymer 432 etched back to fill the closely spaced metal lines while forming sidewalls. FIG. 9 also shows a planarized oxide 450 covering the metal lines and the polymer to a thickness of about 0.7 μm. The oxide film 450 can be deposited by plasma-enhancement using CMP for planarization thereafter.

FIG. 10 illustrates a first level metal line 412.
Is shown through the oxide 450 to a second level metal line 462 on the oxide 450 and to the second level other metal lines 464-470. The etched back polymer 482 (or deposited and fluorinated and annealed parelin) is provided with closely spaced metal lines 462-47.
0 and form a sidewall spacer on the other hand. Next, the planarized oxide 490 covers the second level metal lines. Via 492 filled with metal
Connects the second level metal line 470 to the oxide film 490 later.
Connects to a third level metal line (not shown) formed above. Metal filled vias 452 and 492
May be formed by patterning with photolithography (photoengraving). Then, etch the oxide film,
It is then filled with tungsten by blanket deposition and etchback; selective deposition; or by aluminum reflow or CVD aluminum overcoating the metal lines. Metal lines are formed by blanket metal deposition, then photolithographically patterned, and then anisotropically etched.

Preferred Embodiments for Refilling Polymers FIGS. 11-14 illustrate the IM for two continuous metal levels.
Two successive applications according to the third preferred embodiment of D are illustrated in elevational cross-section. More specifically, FIG.
Metal lines 512-520 above zero, and flattened (fluorinated) covering top of metal lines
The oxide layer 530 is shown. Metal lines 514, 516, 5
18 and 520 have a fine line width of about 0.25 μm and a height of about 0.7 μm. On the other hand, the metal line 512 has a width of about 0.4 μm to facilitate via arrangement.
Indicates that it is spread out. A pair of metal lines 514
516 and 518 to 520, the spacing between metal lines is as small as about 0.25 μm, but the spacing between other metal lines is large. The metal lines are formed by blanket deposition and then photolithographically patterned. The metal can be clad with aluminum.

The minute metal line interval is arranged by photolithography, and then, a portion of the oxide film 530 apart from the minute interval is etched. The etching may be anisotropic plasma etching, or may be selected depending on the metal, and metal lines may be used that stop etching the side surfaces. Overetching into the underlying insulator 510 (overetc
h) may be performed, which is the fringe electric field between the metal lines.
(fringing fields). After etching the oxide film, as described above, the parylene polymer 540
Are conformally deposited. Conformal deposits with a thickness of at least 0.125 μm are finely spaced (excluding possible voids)
Fill. In addition, the thicker deposition produces a coarse-grained plane over the entire surface at minute intervals, as shown in FIG. FIG. 12 illustrates a deposition of about 0.4 μm. The parylene is then fluorinated as described above.

FIG. 13 shows that the polymer 540 is etched back, leaving only the polymer filler during the minute interval. After the polymer has been etched back, the oxide film 5
50 is deposited on the order of 0.5 μm. Etchback of the polymer may alternatively be performed prior to fluorination. In this case, the fluorination expansion of parylene can be compensated somewhat for over-etching.

The metal level is defined by photolithography and then vias in oxide 530-550 are
It is completed by etching to the wide portion of the metal line, such as metal line 512, then filling the via with either selective metal or blanket deposition, and then etching back. The via may be filled with tungsten having a barrier layer. The metal-filled via 560 provides a connection to a second metal level formed in a manner similar to the metal level just described (see FIG. 14). An alternative is to fill the via 560 and then deposit a metal that is patterned to form a second level metal line in a single step. This can be done by any conformal metal deposition method, such as chemical vapor deposition or reflow of a metal such as aluminum (optionally,
A barrier layer of sputtered metal can be initially deposited).

The application described above, a metal (or other conductor) Fluorine treated polymer or copolymer between the lines can be applied to various types of integrated circuits. For example, a DRAM has a large group of long parallel conductive lines, such as bit lines, wordline straps, addresses, data buses, etc., and the fluorination method causes gaps within such multiple groups of parallel lines. Are reliably filled, and capacitive coupling is reliably reduced. The fluorinated polymer or copolymer may be disposed directly on the entire surface of the transistor (eg, between metal lines 112-114 in FIG. 3); or on the entire surface of the transistor (eg, metal line in FIG. 3). 118-120) or other metal lines above or below.

Partial Modifications / Modifications Partial modification or alteration of the fluorinated polymer after deposition can be made as long as most of the properties of those modifications / alterations are retained. For example, a very thin conformal adhesion / barrier layer of oxide can be deposited, followed by parylene (or other polymer or copolymer). Also, depositing the oxide and then performing the CMP can be replaced by an alternative planarization approach. In fact, alternative spin-on-glass (s
pin-on glass), Figures 1-4 (first preferred example)
Alternatively, a process as shown in FIGS. 1 to 3 (second preferred embodiment) is followed, in which the deposition of the oxide film and the planarization of the CMP are replaced by the planarization of the spin-on glass. For details, spin-on hydrogen silsesquioxane with an average thickness of about 0.5 μm
(HSQ); this is the low lying part (PMD exposed between the polymer on the side wall, or low coating polymer)
And will be as thin as 0.05 μm over the narrow metal lines and polymer structures. This provides most of the planarization.

Next, the HSQ is cured, and a (fluorinated oxide film) layer is deposited on the HSQ. This deposition method may be plasma enhanced under planarization conditions (high bias). If greater flattening is required,
A flattening technique such as P or resist etch back can be used. The completed IMD is a fluorinated polymer (dielectric constant of about 2.3-2.
4); HSQ later filled in between (having a dielectric constant of about 3.
0); and finished with (fluorinated) oxide (permittivity 3.5 probably with fluorinated oxide) extending to the next metal level. To make the insulating layer thinner,
An etchback may be included, and alternative spin-on-glass may be used. In particular, the spin-on glass can be totally removed on the polymer over the entire surface of the metal line and only remains in the gaps or low areas between the group of metal lines.

With respect to the above description, the following items are further disclosed. (1) In a method of manufacturing an insulating material for an integrated circuit, (a) attaching a polymer or copolymer onto a partially formed integrated circuit, and (b) introducing fluorine into the polymer or copolymer. And the above method. (2) the polymer or copolymer contains parylene;
The method according to claim 1. The method according to claim 1, further comprising (3) (a) etching a fluorinated polymer or copolymer, and (b) forming an insulating layer on the entire surface of the fluorinated polymer or copolymer. . (4) (a) containing a polymer or copolymer between adjacent conductive lines having a fluorine content characterized by a fluorine treatment after polymerization or copolymerization;
Insulation layer for integrated circuits. (5) A metal interlayer insulating film having a parylene polymer or copolymer 142 treated with fluorine between metal lines 112 to 120; and a vapor deposition method for performing polymerization or copolymerization and then treating the polymer or copolymer with fluorine.

[Brief description of the drawings]

FIG. 1 is an elevational sectional view of various steps of a first preferred embodiment and method.

FIG. 2 is an elevational sectional view of various steps of a preferred first embodiment and method.

FIG. 3 is an elevational sectional view of various steps of a first preferred embodiment and method.

FIG. 4 is an elevational sectional view of various steps of a first preferred embodiment and method.

FIG. 5 is an elevational sectional view of various steps of a first preferred embodiment and method.

FIG. 6 is an explanatory view showing an attaching device.

FIG. 7 is an explanatory view showing various steps of a preferred second specific example and method.

FIG. 8 is an explanatory view showing continuous application of a second preferred embodiment.

FIG. 9 is an explanatory diagram showing continuous application of a second preferred embodiment.

FIG. 10 is an explanatory diagram showing continuous application of a second preferred embodiment.

FIG. 11 is an explanatory diagram showing continuous application of a third preferred example;

FIG. 12 is an explanatory diagram showing continuous application of a third preferred example.

FIG. 13 is an explanatory diagram showing continuous application of a third preferred example.

FIG. 14 is an explanatory diagram showing continuous application of a third preferred example.

Claims (2)

[Claims] 1. A method of manufacturing an insulating material for an integrated circuit, comprising:
The above method, comprising: (a) depositing a polymer or copolymer on the partially formed integrated circuit; and (b) introducing fluorine into the polymer or copolymer. 2. An insulating layer of an integrated circuit comprising a polymer or copolymer between adjacent conductive lines having a fluorine content characterized by a fluorine treatment after polymerization or copolymerization.