JPH10171432A - Display control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a plotting processing at a high speed by skipping succeeding mask data calculation when all of generated mask data values become data which do not update. SOLUTION: This display control circuit plots eight points at a same time. A mask pattern judging circuit 8 evaluates the value of MP, and defines WZERO as 1 when mask calculations of all the affected eight points result in mask designation, but defines WZERO as 0 when at least one point is designated to be plotted without being masked. The generated WZERO is returned to the control circuit 11 for a dynamic control of processing procedure. The control circuit 11, even time when operating a mask calculation in a window of each number, checks a value of an output signal WZERO and determines the next processing based on the result of the checking, also including an output signal AG of WP-CW comparator 6. Thus, when AG becomes 1, the mask calculation is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control circuit for displaying a so-called window display on a display means in an information processing apparatus (OA equipment) such as a portable information terminal or a personal computer.

[0002]

2. Description of the Related Art In an information processing apparatus (OA equipment) such as a portable information terminal or a personal computer, display is performed using a display means such as a CRT or an LCD. A window function is used.

The window function is a function of displaying different display data in a specific display area (hereinafter, referred to as a window function) set in the previous display area on a display screen already displayed.

[0004] Such a window area may be set at a plurality of positions in a single display area, or another window display area may be displayed over another window display area that has already been displayed.

In order to realize such a window function, in a process for updating the display contents, it is determined whether or not the point is inside or outside the window at each position in the entire display area, and whether or not drawing is performed. It is necessary to perform a process (mask calculation) for discriminating whether or not (mask), and a large amount of address operations are required to determine the inside and outside of the window area.

Although this address calculation can be performed by software processing, since the amount of calculation is large, it is necessary to operate the CPU at high speed in order to obtain a practical processing speed, which leads to an increase in power consumption.

For this reason, in a battery-powered electronic device such as a portable information terminal, which is intended to be used in a portable manner, in order to realize high-speed address calculation with low power consumption, the above-described hardware process is used instead of software process. The mask calculation is realized.

FIG. 5 shows an outline of a display control circuit for performing a mask calculation by hardware processing for display.

In FIG. 1, a portion surrounded by a broken line corresponds to a mask calculation circuit.

This mask calculation circuit has a window coordinate data register for designating a rectangular area of a window.

The window coordinate data has a total of four values for the top, bottom, left, and right of the window for each window.

When a plurality of windows are to be displayed, coordinate data registers for a total of four points, up, down, left and right, are prepared for each window.

Next, an arithmetic circuit is provided for determining whether the coordinates of the drawing object are inside or outside of each set data of the window coordinates.

In this operation, it is necessary to determine the positional relationship between the left and right set points of the window and the X coordinate of the drawing position and the positional relationship between the upper and lower set points of the window and the Y coordinate of the drawing position for one window. For,
Four operation circuits (subtraction circuits) are used.

By synthesizing data generated through these four arithmetic circuits, mask data for one window can be obtained.

When a plurality of windows are set, it is necessary to perform the mask calculation for each set window.

For this reason, after performing a mask calculation for a certain window using the current window pointer, the current window pointer is incremented by one and the mask calculation for the next window is continuously performed. The results of the respective mask calculations are integrated to obtain the final mask data.

The VRAM control circuit that operates the display data storage memory (VRAM) using the created mask data performs the following processing.

In general, in a black-and-white display system, display data at eight or sixteen display positions is stored per VRAM address based on the memory configuration.

At the time of drawing using the window function, of the display data corresponding to the plurality of points, data corresponding to a position designated by a mask is not updated, and only data corresponding to a position not designated by a mask is updated.

Therefore, at the time of drawing, the data at the corresponding address is first read once, and the data corresponding to the position to be drawn without the mask is replaced with the drawing data, and the data corresponding to the position designated by the mask is replaced with the drawing data. The data read from the VRAM is left as it is, and the data of 8 dots (or 16 dots) obtained by combining them is written back to the same address of the VRAM again.

The operation will be described with reference to the flowchart of FIG. 6. Initial setting is performed (S601), and a window mask calculation for the first sheet is performed (S602).

As described above, if the set number is plural, the current window pointer is incremented by 1, and the Nth window mask calculation is superimposed (S603 to S605). Is executed and the processing is terminated (S606, S607).

[0024]

In the conventional display control circuit described above, when a large number of windows are set, the window calculation is repeatedly performed by the number of windows. It takes time to calculate.

Here, when a plurality of windows are set, the logical product of the mask data is taken when integrating the plurality of window data to obtain the final mask data. In other words, when any one of the calculation results for a plurality of window masks indicates a value indicating a mask (do not draw), that portion is designated as a mask regardless of the calculation results of other windows. .

That is, for example, when five windows are set and the mask calculation is performed, if the calculation result already indicates the mask in the first calculation result, the calculation values of the second and subsequent frames are set to the final result. Has no effect.

However, in the conventional mask calculation circuit, even in such a case, the mask calculation is always performed for all the set number of sheets. Therefore, when the number of windows is set to be large, the drawing processing speed is inevitably reduced.

Further, in the conventional display control circuit, access to the display data storage memory is always performed even when the mask calculation result indicates a value indicating a mask (no drawing) as in the above-described example. That is, once the data at the address corresponding to the drawing target position is read out,
A process of writing the read data back to the same address is performed, and a processing time for the process is spent.

An object of the present invention is to improve the drawing speed in the above case.

[0030]

According to a first aspect of the present invention, there is provided a display control circuit for storing window coordinate data for realizing a window function for limiting a display data update target position to a specific frame. Means, an address setting means for setting an address of the update display data,
A mask data generating unit that generates mask data that determines whether display data can be updated based on the window coordinate data and the address data, and that values of the mask data generated by the mask data generating unit do not update display data. A mask data detecting unit for detecting that the display data is a value representing the display data, and when the mask data detecting unit becomes a value indicating that all the display data is not updated, the subsequent mask data calculation is performed. A display control circuit that executes a skipping process.

A display control circuit according to claim 2, wherein a window coordinate data storage means for storing window coordinate data for realizing a window function for limiting a display data update target position within a specific frame; Address setting means for setting an address, mask data generating means for generating mask data for determining whether display data can be updated based on the window coordinate data and the address data, and a value of mask data generated by the mask data generating means Has mask data detecting means for detecting that all the display data are not updated, and the mask data detecting means changes the mask data value to a value indicating that all the display data is not updated. Read from the display data storage memory,
A display control circuit for executing a processing process for eliminating writing.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows the configuration of a display control circuit according to an embodiment of the present invention. The display control circuit includes a window data register 1, a subtractor 2, a mask pattern generation circuit 3, a window pointer register 4, a current window pointer circuit 5, a WP and CW comparator 6, a mask pattern superimposition circuit 7, and a mask pattern determination circuit 8. , Data operation circuit 9, VRAM data buffer 10, and control circuit 11
Consists of

The window data register 1 stores data defining the coordinates of the four corners of the rectangular window.

That is, one window holds four data items of the left end XLT, the right end XRT, the upper end YT, and the lower end YB. A total of 16 sets of this set of 4 data are stored at the same time, and a maximum of 16 windows can be handled. The window pointer register 4 is a register for storing which of the 16 windows is to be designated, a signal WP serving as an index thereof.

The WP has two major roles. One is to specify a target window number (the number of the window) when setting window data, and the other is to perform a mask calculation at the time of drawing. , The number of windows to be subjected to the mask calculation (the number of windows). The values of the window data register, window pointer register, and both registers are set by software control from the CPU.

The signal CW output from the current window pointer circuit 5 is also a signal for specifying a window number, but its role is different from that of WP.

CW is used only when performing mask calculation at the time of drawing, and indicates the number of the window where the mask calculation is currently performed. The function of the current window pointer circuit 5 itself is to increment the output signal by one according to external control, and in this embodiment, it is possible to increment the CW to 0TO15 corresponding to 16 windows. .

The operation specifications will be described later together with the operation of the WP / CW comparator 6. The subtracter 2 calculates the size relationship between the drawing target coordinates DX and DY and the four corner coordinates of the window, and performs four subtraction calculations simultaneously. There are two types of calculation contents, one of which is selected and executed based on the VH setting at the time of drawing.

In the display control circuit of this embodiment, drawing is simultaneously performed on eight points, and the arrangement direction of the eight points is set in advance. The VH setting is a setting for designating the arrangement direction of eight points of drawing data, and determines horizontal writing or vertical writing as shown in FIG.

Based on this VH setting, in the case of horizontal writing setting, subtraction of the following equations 1 to 4 is performed by the subtractor 2.

Left: SUBL = (DX + 8) -XLT (1) Right: SUBR = XRT-DX (2) Top: SUBT = DY-YT (3) Bottom: SUBB = YB- DY (4) In addition, in the case of vertical writing setting, the subtractor 2 performs subtraction of the following Expressions 5 to 8.

Left: SUBL = DX-XLT (5) Right: SUBR = XRT-DX (6) Top: SUBT = (DX + 8) -YT (7) Bottom: SUBB = YB- DY (8) Four values obtained by the above subtraction, SUBL, SU
From the BR, SUBT, and SUBB, the mask pattern generation circuit 3 generates a signal indicating whether the drawing target coordinate is inside or outside, that is, a mask information signal MP, for the window currently specified by the signal CW. You.

MP is set to VH, and D is set for horizontal writing.
It has eight points of mask information of X, DY to (DX + 7) and DY, and DX, DY to DX, (DY +
8) The mask information has eight points. Mask information signal MP
Indicates that the bit to be masked is 0 and the drawing is performed without masking bi
t is output as 1.

The mask information signal MP at this stage indicates the mask information for one window as described above. For this reason, when a plurality of windows are set, the mask information in each window is calculated, and the final mask information MSK obtained by integrating the mask information is calculated.
You need the ability to create

In this embodiment, the mask pattern superimposing circuit 7 performs a process of integrating the above-mentioned mask information. The internal configuration of the mask pattern superposition circuit 7 is a combination of an AND gate and a latch as shown in FIG. 3, for example. Also described in the description. The flow of operation of each unit at the time of drawing is described below.

First, coordinate data of each window is set in the window data register 1 in advance, and a window number to be drawn is set in the window pointer 4 before drawing. Whether to write horizontally or vertically,
VH setting is performed in advance.

When a drawing command is given, a mask calculation is first executed. At that time, the mask calculator is first initialized, and the current pointer CW and the mask information MSK are initialized.

CW is initialized to 0, and MSK is initialized to a state in which all 8 bits are 1, ie, all 8 dots are not masked. By the initialization of the CW, the coordinate data of the first (No. 0) window is output from the window data register 1, and the mask information calculation for the first window is sent to the subtracter 2 and the mask pattern generation circuit 3. And the mask information data MP relating to the first window is output.

In this state, in the mask pattern superposition circuit 7, the logical product of MP and MSK is latched and MSK is updated. The processing up to this point is for the first window.

Here, regarding the updated MSK value, since the MSK before the update is in the initialized state, that is, all are 1, the result of ANDing with MP is exactly the same value as MP. . That is, at the stage where the processing of the first window is completed, the mask information data relating to the first window is stored in the MSK.

Subsequently, the processing shifts to the processing for the second window.

First, the current window pointer circuit 5
In the above, CW is incremented by 1 to 1.

Thus, the window data register 1
, The coordinate data of the second window (number 1) is output, the mask information calculation for the second window is performed by the subtractor 2 and the mask pattern generation circuit 3, and the second window Information MP related to
Is output.

Then, in the mask pattern superposition circuit 7, the logical product of MP and MSK calculated for the second window is latched and MSK is updated again. Since the value of MP calculated for the first window is stored in the MSK before the update, the mask information data calculated for the first window and the value of the MP calculated for the second window after the update are stored. The logical product of the mask information data is stored.

This means that if either one of the first window and the second window shows a value indicating a mask, the coordinates are masked. doing.

Subsequently, the processing shifts to the processing for the third window. The processing flow is the same for the third and subsequent sheets.

First, the current window pointer is incremented by one, and a mask calculation for a new window is performed. As a result, the logical product of MP and the signal MSK in which the results of the previous mask calculation are aggregated is taken and MSK is relatched. Update the content.

In each of the above-described processes, the current window pointer CW is set to a predetermined window pointer WP.
Is repeated until the value of

This control is performed through the WP / CW comparator 6.

The WP / CW comparator 6 compares the values of WP and CW. If WP and CW have the same value, the output signal AG is set to 1; if not, AG is set to 0.

For example, when drawing on the fifth window, a value indicating the fifth window is set to 4 in the window pointer register in advance. In this case, since CW starts from 0 at the start of mask calculation, WP and CW have different values and AG is 0.

Thereafter, as described above, the mask calculation is executed sequentially from the first window, and the current window pointer is incremented. When the current window pointer reaches the value indicating the fifth window = 4,
AG changes to 1 when WP and CW match.

The control circuit 11 monitors the value of AG to determine the next operation.

That is, while the AG is 0, the mask calculation and the MSK update processing are continued. When the AG becomes 1, no further mask calculation process is performed and the VRA
The processing shifts to the M access routine. Taking the case where the previous WP setting is 4 as an example, this will be described in more detail.
In this example, since CW = 3 and AG = 0 at the stage when the mask calculation for the fourth window is completed, the mask calculation process is continued, and the process for the fifth window is started.

At the beginning of the processing of the fifth sheet, the current window is incremented, and the CW becomes 4. As a result, WP and CW match, and AG becomes 1.

Thereafter, the fifth window, ie, CW
The process is performed up to the mask calculation for MS = 4 and the update of the MSK.

At the stage where the MSK is updated, the control is changed based on AG = 1, and the process shifts to the VRAM access routine without entering the mask calculation step for the sixth window.

At this stage, the mask information MSK is finally determined. In the VRAM access routine, first, the VRAM data at the address corresponding to the drawing coordinates is read and stored in the VRAM data buffer 10.

Data D stored in data buffer 10
Based on B, the drawing data DA given by the CPU, and the mask information MSK, the data operation circuit 9 creates display data WD which is finally written to the VRAM after passing through the window function.

That is, MSK is used as a parameter,
In, the drawing is performed without masking the bit having the value of 1 so that the value of the CPU drawing data DA is adopted and applied to the corresponding bit of WD, and the bit having the value of MSK of 0 is masked, that is, the drawing is not performed. In order to continue the display data as it is, the value of the data DB read from the VRAM is adopted and applied to the corresponding bit of WD.

By performing this operation for eight bits, that is, for all eight bits, a WD is created.

Thereafter, the new display data WD is stored in the VRA
At the same address as in the M read, the data is written back to the VRAM. At the stage where the writing back to the VRAM has been performed, a series of drawing operations is completed.

In this embodiment, the mask pattern determining circuit 8 is provided as described above. The mask pattern determination circuit 8 evaluates the value of MP, and if the value of M is 0 for all 8 bits, the output signal WZ of the mask pattern determination circuit 8 is evaluated.
ERO is set to 1; otherwise, WZERO is set to 0 if there is a bit whose value is 1 even in 1 bit out of 8 bits.

That is, when all the mask calculation results of the eight target points are designated as masks, WZER
O is set to 1, and WZERO is set to 0 in a state where it is instructed to perform drawing without masking even one point.

The WZERO created in this way is returned to the control circuit 11 to perform dynamic control of the processing procedure.

The control circuit 11 checks the value of the output signal WZERO of the mask pattern judging circuit 8 together with the output signal AG of the WP-AG comparator 6 every time the mask calculation in the window of each number is performed, and based on the contents thereof, The following processing is defined.

As described above, when AG becomes 1, the mask calculation for the set number of windows is completed in that step, so that in the next step, the processing shifts to the VRAM access routine.

In the present embodiment, the operation based on this AG is an operation limited to the case where WZERO is continuously 0 until that stage.

In the control circuit of this embodiment, when WZERO becomes 1 before AG becomes 1, that is, before the mask calculation for the set number of windows is completed,
The control circuit 11 changes the next processing based on WZERO = 1 separately from the value of AG.

That is, when WZERO = 1, the process does not proceed to the mask calculation for the next window number.
The VRAM access routine is not performed, and the series of drawing operations is terminated.

If the mask pattern determination circuit 8 is not used as in the conventional method, the WZER
Even in the case where O becomes 1, that is, in the case where MSK becomes all 0, the mask calculation is continued until the window mask calculation of the initially set number is completed, that is, until AG becomes 1. However, once the MSK has all become 0, no matter what value the mask calculation value MP in the subsequent window number takes, the MSK already has all the 0s.
Therefore, the logical product of the MSK and MP is naturally all 0
It does not change even if the calculation is repeated.

Therefore, MSK becomes all 0 and W
After ZERO becomes 1, even if the subsequent window mask calculation is skipped as in the present embodiment, the mask calculation result does not change, and the processing can be speeded up by the skipped amount.

Further, in the case where all the MSKs become 0, if the VRAM access routine is performed as in the conventional method, the following operation is performed.

First, as described above, the VRAM data at the address corresponding to the drawing coordinates is read and stored in the VRAM data buffer. Data D stored in data buffer
B, the drawing data DA given by the CPU, and the mask information MSK, display data WD to be finally written to the VRAM after passing through the window function is created in the data operation circuit 9, but in this case, MSK Are all 0, WD is filled with the value of the data DB read from the VRAM for all 8 bits.

The data WD, which is the same data as that of the DB, is renewed at the same address as when reading the VRAM.
It is written back to RAM.

Therefore, the contents of the VRAM data after the execution of the VRAM access routine are not different from those before the execution of the routine.

Therefore, in the case where WZERO becomes 1, the same result can be obtained even if the VRAM access routine is omitted as in the present embodiment, and the processing can be speeded up by the skipped VRAM access routine.

FIG. 4 shows a flowchart of the processing procedure of the present embodiment described above.

The initial settings are made, the first window mask calculation is performed, and it is determined whether or not all the mask data is 0 (S401 to S403).

If it is 0, the process ends.

If it is not 0, the window processing for the set number is performed, the current window pointer is incremented by 1, and the window mask calculation is superimposed on the Nth window mask calculation (S404 to S404).
06).

When the window processing for the set number of sheets is completed,
Executes the VRAM access routine and ends (S40)
7, S408).

In the present embodiment, control of the processing procedure based on WZERO is added, and when WZERO becomes 1, the subsequent processes are skipped. By this branching process, the speed of the total drawing process can be increased.

In the present embodiment, the control change when WZERO = 1, that is, the subsequent skipping of the window mask calculation and the skipping of the VRAM access routine are as follows.
It is not always necessary to implement both at the same time. Even if only one of them is performed, the corresponding processing can be speeded up. If both are performed, the effect of increasing the speed can be obtained more.

[0096]

As described above, according to the present invention, in the middle of the mask calculation for a plurality of windows, all the mask data values generated by the mask data generating means do not update the display data. When the value becomes a value, the subsequent mask data calculation is skipped, so that the drawing processing can be performed at high speed.

Similarly, when the mask data value generated by the mask data generating means becomes a value indicating that all the display data is not updated, the reading of the display data scheduled to be performed subsequently in normal time is performed. Since writing is not executed and the process immediately proceeds to the process at the next display address, the drawing process can be further speeded up.

[Brief description of the drawings]

FIG. 1 is a block diagram of a display control device of the present invention.

FIG. 2 is an explanatory diagram of VH setting.

FIG. 3 is a configuration diagram of a mask pattern superposition circuit 7;

FIG. 4 is a flowchart showing the operation of the present invention.

FIG. 5 is a block diagram of a conventional device.

FIG. 6 is a flowchart showing the operation of the conventional device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Window data register 2 Subtractor 3 Mask pattern generation circuit 4 Window pointer register 5 Current window pointer circuit 6 WP, CW comparator 7 Mask pattern superposition circuit 8 Mask pattern judgment circuit 9 Data operation circuit 10 VRAM data buffer 11 Control circuit

Claims (2)

[Claims] 1. A window coordinate data storing means for storing window coordinate data for realizing a window function for limiting a display data update target position to a specific frame, and an address setting means for setting an address of updated display data. And mask data generating means for generating mask data for determining whether display data can be updated based on the window coordinate data and the address data, and the mask data values generated by the mask data generating means do not update the display data. Mask data detecting means for detecting that the display data is not updated, and when the mask data detecting means has determined that all the mask data values do not update the display data, Display control characterized by executing a process for skipping calculations circuit. 2. A window coordinate data storing means for storing window coordinate data for realizing a window function for limiting a display data update target position to a specific frame, and an address setting means for setting an address of updated display data. And mask data generating means for generating mask data for determining whether display data can be updated based on the window coordinate data and the address data, and the mask data values generated by the mask data generating means do not update the display data. And a mask data detecting means for detecting that the display data is not updated. Execute the processing process to stop reading and writing to And a display control circuit.