JPS63104191A - Drawn picture processor - Google Patents

Abstract

PURPOSE:To speedily display layout accompanied by the compression of picture data by providing a register which specifies the size of a picture element group to be reduced and a picture element to be calculated among the picture elements in the group. CONSTITUTION:A source address is transmitted to a switch 18 from a source address register 15. Simultaneously reduction pattern data is read out of a pattern RAM20. If the data is '1', the switch 18 is turned on to supply the data to a frame buffer 3. Picture data is read out and fetched to a drawn picture data register 12. Next the picture data is supplied to a drawn picture data computing element 11 to logically operate it, and the drawn picture data register 12 holds the results. If the data read out of the pattern RAM20 is '0', the switch 18 is turned off, and no data is read out. At the end of all operations regarding reduction, drawn picture data in the drawn picture data register 12 is outputted and written in the frame buffer 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a technique that is particularly effective when applied to a drawing processing technique and a calculation method for image data supplied to an image memory. The present invention relates to a technique that is effective for use in an arithmetic method in an LSI having a drawing function.

[Prior Art] In a microcomputer system equipped with a display device such as a word processor, only a portion of a document may be displayed on the display screen.

Even in such cases, you may want to know the layout of the entire document. Therefore, there are word processors that are capable of displaying not only a portion of a document but also the entire layout of the document (for example, WordPal, a word processor manufactured by Hitachi, Ltd.).

In the above case, since the entire document that cannot be displayed on one screen is displayed in a reduced size, it is necessary to compress or thin out the busy image data.

[Problems to be solved by the invention] However, the CRT used in the conventional display system
controller or graphics controller
Even if the device has a function of calculating image data to be written into the image memory, it does not have a function of compressing the image data.

Therefore, layout display in conventional display systems has had to be realized entirely through software processing. As a result, the time required for the data compression calculation process as described above increases. Moreover, with the shift to color display screens, the number of memory accesses increases as the amount of image data per pixel increases, making it increasingly difficult to display layouts in real time. be.

SUMMARY OF THE INVENTION An object of the present invention is to provide a drawing processing technique that can display a layout at high speed while compressing image data.

Another object of the present invention is to provide a drawing processing technique that can prevent fatal information loss when compressing image data and display a layout with higher accuracy.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, the drawing processing unit is provided with a register and RAM for specifying the size of the pixel group to be reduced and which pixels are to be subjected to calculation among them, and the source address calculated based on this information is output to the outside. It forms a control signal that determines whether or not to perform the reduction, reads out the image data of the specified pixel, and performs logical operations on the image data for each reduced area to form drawing data. .

[Function] According to the above-described means, since image data can be compressed by hardware, layout display accompanied by image data compression can be performed at high speed. In addition, by rewriting data in RAM or registers for specifying the calculation target in the reduction target area, it is possible to perform calculations on image data with a high degree of freedom, resulting in fatal information loss when compressing image data. It is possible to achieve the above-mentioned purpose of preventing the above problems and displaying a layout with higher accuracy.

[Embodiment] FIG. 2 shows a configuration example of a display system equipped with a graphic controller to which the present invention is applied.

That is, this system consists of a microprocessor (hereinafter referred to as MPU) 1, a system ROM (read-only storage device) in which system programs are stored, and a working RAM (read-only memory device) that serves as a work area and text area when the MPU works. A main memory 2 consisting of a writable storage device 2. A frame buffer (image memory) 3 that stores image data etc. displayed on the CRT display device 9. Image data is written to the frame buffer 3 based on instructions from the MPU 1. , a graphic controller 4 that performs reading, and a parallel-to-serial conversion circuit that forms and outputs a video signal such as an RGB (red, green, blue) signal based on the image data read out from the frame buffer 3. (or video controller) 5. DM that directly transfers data within the main memory 2 and between the main memory 2 and the frame buffer 3
It is composed of the A controller 6 and the like.

When the graphic controller 4 receives a command from the MPUI via the system bus 7, it decodes the command, calculates an address and creates image data, and supplies it to the frame buffer 3 via the local bus 8. , writes image data. Along with this, the graphic controller 4 has a display address generation section such as an address counter, and in parallel with the above-mentioned drawing processing, outputs display addresses one after another onto the local bus 8 and reads image data from the frame buffer 3. , this is a CRT
The data is supplied to the display device 9 and displayed on the display screen.

FIG. 1 shows an embodiment of the configuration of the drawing processing section of the graphic controller 4. As shown in FIG.

Reference numeral 11 denotes a drawing data calculator that calculates drawing data including color information, and 12 a drawing data register that holds the drawing data calculated by the drawing data calculator 11. The drawing data calculator 11 includes OR,
It is configured to be able to perform arbitrary logical operations such as AND or FOR, and performs logical operations on the image data read from the external frame buffer 3 and the data in the drawing data register 12, and uses the result of the operation. The data is sent to the drawing data register 12.

The drawing data held in the drawing data register 12 is supplied to the frame buffer 3 and written to a desired position.

In this embodiment, the type of operation in the drawing data calculator 11 is specified by a control signal formed by decoding a part of the command in the command register 13 that holds commands supplied from the MPU in the decoder 14. It is designed to be

Further, reference numeral 15 indicates a source address register in which an address for reading desired image data from the frame buffer 3 is stored, and reference numeral 16 indicates a source address register in which the drawing data calculated by the drawing data calculation unit 11 is to be written. This is a destination address register that holds the position (drawing address).

The addresses in the source address register 15 and destination address register 16 are supplied to the address calculator 17 and updated, and the formed address is stored in the original register.

The address in source address register 15 is switch 1
8 and directly the address in the destination address register 16, respectively.
9, the logical address indicated by the X-Y coordinates is converted into a physical address (linear address) corresponding to the memory space of the frame buffer, and the frame buffer 3
It is designed to be supplied to

In this embodiment, there is a pattern RAM 20 for specifying the calculation target in the pattern RAM 20, and a pattern control register 21 for specifying the usage range of data in the pattern RAM 20, that is, the target range dX, dY of reduction processing on the display screen. is provided. In addition, the above pattern RAM20
A RAM pointer control unit 22 is provided to indicate the position of data to be used next.

Values dX and dY indicating the usage range of the pattern RAM set in the pattern control register 21 are supplied to the address calculator 17 to calculate an address for the pattern RAM. The calculated address is set in a pointer in the RAM pointer control unit 22, and access to the pattern RAM 20 is executed based on it. At this time, data within the specified range dX, dY is read out one by one from left to right in the pattern RAM 20, and the switch 1
Provided as an 8-head on/off control signal.

As a result, for example, when the data read from the pattern RAM is "0", the switch 18 is turned off, and when the data is "1", the switch 18 is turned on,
The address in source address register 15 is switch 1
8 to the address conversion unit 19.

Further, a control section 30 is provided to sequentially control each of the above sections to execute desired drawing processing. The control unit 30 is composed of a micro ROM in which a micro program is stored, although it is not particularly limited.
The micro ROM is activated by a command supplied from the PU, and a series of micro instructions to execute the process corresponding to the command are read out one after another to form control signals for each register and arithmetic unit. It has become.

FIG. 3 shows an example of a control procedure in the control unit 30 when performing a reduction process on image data when displaying a layout. However, it is assumed that the settings in the source address register 15, destination address register 16, and pattern control register 21 are completed before the command instructing the reduction process is executed.

When a reduction processing command comes in, first the pattern RAM
The RAM pointer indicating the read position is reset. Also, if necessary, at this time, the drawing data register 1
Also perform the 2nd reset.

Next, the source address is read from the source address register 15 and sent to the switch 18, and the reduced pattern data is read from the pattern RAM 20. Here, if the data read from the pattern RAM 20 is "1", the switch 18 is turned on and the source address is supplied to the address conversion unit 19, where the logical address is converted into a physical address, and then the external is supplied to the frame buffer 3 of. As a result, the image data is read from the frame buffer 3, and this is taken into the drawing data register 12.

Then, the image data in the drawing data register 12 is supplied to the drawing data arithmetic unit 11, which performs a logical operation specified by the command, and causes the drawing data register 12 to hold the result.

Next, the source address in the source address register 15 is supplied to the address calculator 17 to update the source address, and then it is temporarily returned to the source address register 15, and the address in the pattern control register 21 is subjected to address calculation. 17 to update the RAM pointer. Then, it is determined whether or not all of the above arithmetic processing has been completed for the number of pixels corresponding to the data use range (dX, dY) in the pattern RAM 20. If not, the source address register 15 and the pattern RAM 20 are Read the data.

Therefore, the read data of the pattern RAM 20 is "0".
In this case, the switch 18 is turned off and the source address is not supplied to the address converter 19, so all arithmetic processing related to the reduction target (dx, dY) is completed without reading the image data or calculating the drawing data. Determine whether or not.

When all arithmetic processing related to the reduction target (dX, dY) is completed, the destination address is read from the register 16 and supplied to the address conversion unit 19, where it is converted into a physical address, outputted, and supplied to the frame buffer 3. At the same time, the drawing data contained in the image data register 12 at that time is output and written to the position indicated by the destination address in the frame buffer 3. Then, the address in the register 16 is supplied to the address calculator 17 to update the destination address, and after returning it to the original register 16, reduction calculation processing is performed on all image data on one display screen. It is determined whether or not the process is completed, and the above operation is repeated until the process is completed.

FIG. 4 shows the control procedure described above in the case where data 1.1.1 is written in 3 bits in a diagonal direction as shown in FIG. It shows how drawing data is formed when reduction calculation processing according to the above is executed.

First, the graphic controller 4 successively outputs source addresses for reading out the image data of the pixels indicated by ■, ■, ■ in the rectangular area S1 in the frame buffer 3. The image data thus read out is taken into the graphic controller 4, and a desired logical operation is executed to form the drawing data A as shown by the operation ``■ `` `` `` `` . The drawing data A is supplied from the graphics controller 4 to the frame buffer 3, and written to the position indicated by the destination address output from the graphics controller 4 at that time.

Similarly, the rectangular areas S2 and 8 in the frame buffer 3
3. S4. Three data logic operations are executed one after another for each image data of... to create drawing data B, C, D.
, . . . are generated and stored in the destination area of the frame buffer 3. As a result, for example, the image data of six rectangular areas (one area consists of nine pixels) shown in FIG. 4 is compressed into six pixel data and stored in the frame buffer 3. Therefore, when this compressed image data is read out and displayed on a CRT display device, an image reduced to one-ninth is obtained.

In the above case, the type of logical operation during the reduction process may be changed depending on the content of the image on the display screen (character display, graphic display, color display, etc.). Furthermore, in the above embodiment, the pixels to be subjected to calculation within the rectangular area can be changed by rewriting the data in the pattern RAM.

Therefore, good results can be obtained by rewriting the data in the pattern RAM, for example, depending on whether the image has many vertical or horizontal lines or the image has many diagonal lines on the display screen. In other words, when there are many vertical and horizontal lines on the display screen, the data pattern in the pattern RAM is as shown in FIG. 5(B).

If you select a data pattern like (C), there is a risk that vertical or horizontal lines may be missing, but this can be avoided if you select a data pattern like Figure 5 (A) as the data pattern for the pattern RAM. can. On the other hand, when there are many diagonal lines upward to the right on the display screen, data compression with less data loss can be achieved by using the data shown in FIG. 5(B) rather than the data pattern shown in FIG. 5(A). By determining the data pattern of the pattern RAM according to one display screen in this way, a good reduced screen can be obtained.

In the above embodiment, an example of the configuration of the drawing processing section is shown, but the graphics controller reads image data from the frame buffer separately from the drawing processing section and displays it on the display screen. A display processing unit is provided to perform processing to display the image.

Further, regarding the drawing processing section in FIG. 1, only the essential parts necessary for implementing the present invention are shown.

In addition, for example, a register indicating the drawing start position As in the frame buffer, a register indicating the drawing areas X and Y, and the like are provided.

Furthermore, in the above embodiment, a two-dimensional configuration pattern RAM is provided to store data on whether or not to perform calculations on pixels in a rectangular area to be reduced, but this is different from the one-dimensional configuration pattern RAM. It is also possible to use a register.

As explained above, in the above embodiment, the drawing processing unit is provided with a register and a RAM for specifying the size of a pixel group to be reduced and which pixels are to be subjected to calculation among them, and the drawing process is performed based on this information. Forms a control signal that determines whether or not to output the calculated source address to the outside,
Since the image data of specified pixels is read out and logical operations are performed on the image data for each reduced area to form drawing data, the image data can be compressed by hardware. This has the advantage that layout display accompanied by image data compression can be performed at high speed.

In addition, the drawing processing unit is equipped with a register and RAM for specifying the size of the pixel group to be reduced and the pixels to be calculated among them, and the source address calculated based on this information is output to the outside. It forms a control signal that determines whether or not to perform the reduction, reads the image data of the specified pixel, and performs logical operations on the image data for each reduction area to form drawing data. Since the area setting means is configured with RAM or registers, image data calculations can be performed with a high degree of freedom by rewriting data in RAM or registers, which prevents fatal information loss when compressing image data. This has the effect of preventing this problem and enabling more accurate layout display.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, in a microcomputer system equipped with a display device such as a word processor, layout display with compression of image data can be performed at high speed, and
Preventing fatal information loss when compressing image data,
This allows for more accurate layout display.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a drawing processing section when the present invention is applied to a graphics controller having a drawing function, and FIG. 2 is a configuration of a display system using the graphics controller. FIG. 3 is a flowchart showing an example of the control procedure of the reduction calculation process; FIG. 4 is an explanatory diagram showing the operation of the reduction calculation process; FIG.
A), CB), and (C) are explanatory diagrams showing an example of data in a pattern RAM that specifies a reduction calculation target. 9...CRT display device, 20...Calculation target designation means (pattern RAM), 21...Reduction area setting No. 4 Figure ■-0 Attack○卦■

Claims (1)

[Claims] 1. An address calculator for calculating a drawing address;
An image data calculator for calculating image data, a reduction area setting means for setting the size of a pixel group to be reduced and targeted, and a reduction area to be subjected to calculation among the reduction areas set by this reduction area setting means. It includes a calculation target designation means for designating a pixel, and an address register that holds the drawing address calculated by the address calculation unit, and outputs a source address only for the pixel designated by the calculation target designation unit to create an image. A drawing processing device characterized in that it reads data and performs logical operations on the image data for each reduced area to form drawing data. 2. The drawing processing device according to claim 1, wherein the reduction area setting means is constituted by a register or a memory that can be written to and read from at any time.