JPH03266151A - Vram access system - Google Patents

Abstract

PURPOSE:To speed up an image editing process by providing a bank setting register for reading and a bank setting register for writing independently. CONSTITUTION:A read processing part 3 reads image data out of part of, for example, a bank B2, and the image data is enlarged by, for example, an enlargement processing part 5 and written in part of a bank B20 by a writing processing part 4. Thus, the bank setting register for reading and the bank setting register for writing are provided independently of each other to perform a reading process and a writing process independently, so a multitask process becomes possible and reading and writing are put in parallel operation to speed up the image editing process.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Prior Art (Figures 3 to 5) Means for Solving the Problems to be Solved by the Invention (Figure 1) Working Examples (Figure 2) Effects of the invention [Summary] Regarding the VRAM access method, the purpose of this invention is to speed up image display and editing by performing read processing and write processing to VRAM independently. In an apparatus that has a VRAM configured of banks and displays an image by accessing the VRAM by bank switching control, a bank setting means for instructing a bank to be read from the VRAM;
A special field of industrial application characterized in that a bank setting means is provided to specify a bank for writing, and the bank of each access destination can be switched independently during reading and writing. ] The present invention relates to a VRAM (Visual RAM) access method, and in particular to a VRAM (Visual RAM) access method in an image display device that enables parallel operations of reading and writing operations.
Regarding M access method.

[Conventional technology]

The VRAM of conventional image display devices has about four layers (
For example, with a personal computer, there are four planes (RlG, B, and brightness) in terms of graphics, and the read/write time is not much of a problem.

However, in recent years, the demand for high-definition images has become stronger.
As shown in FIG. 3, devices that express one dot on a display surface by superimposing 8 bits each of R, G, and B are becoming common. Along with this, devices with VRAMs with a large number of planes have been developed, but it is necessary to switch the target plane for reading and writing. The challenge is to increase speed and speed.

In the case of a VRAM that is expressed with 8 bits each for R, G, and B, as shown in Figure 3, there are 8 planes for R (red), 8 planes for G (
This results in a superposition display of 24 layers: 8 planes (green) and 8 planes B (blue), and therefore shortening the plane switching time has become important.

The fastest method is to take VRAM addresses planarly and access them simultaneously. But 100 per horizontal scan line
In the case of a VRAM with a resolution of about 1000 x 800 with 0 dots and 800 horizontal scanning lines on one screen, the OS
This requires 2.3 Mbytes of address area on the main memory under management, which is not practical. Of course, in a system where the main storage area under OS management is about IM bytes, such a
It is impossible to manage 2.3 Mbytes.

Therefore, we devised the address structure of the VRAM, as shown in Figure 4 (B).
) As shown in FIG.
Lines 1 to 22 of the 00 horizontal scanning lines are set to bank B1.
and lines 23 to 44 are allocated to bank B2.

Thus, by using 36 banks, 2.
It becomes possible to manage and control access to a 3M byte area with a size of 64 bytes.

In this case, as shown in FIG. 5, a bank setting section 30 is provided for specifying which bank to access when accessing the VRAM, and the bank corresponding to the number written in the register 30-1 of the bank setting section 30 is provided. For reading, the processing section 31 or the writing processing section 32 accesses.

[Problem to be solved by the invention]

By the way, in the conventional VRAM interface, as shown in FIG. 5, it is possible to access only the bank number written in the register 30-1 of the bank setting section 30. It is possible to read and write at the same time to banks, but it is not possible to read and write to unwritten banks at the same time.

That is, reading and writing to different banks cannot be performed simultaneously. Therefore, when editing images, the reading processing section 3
For example, when the CPU enlarges an image read from bank B1 and the write processing unit 32 writes it to bank B20, a large work area is required on the main memory, which takes up space in other areas. Due to delays in processing, reduction in usable area, etc., a hard disk such as a magnetic disk device must be used for work. Therefore, the man-machine interface is poor (so-called slow response and long processing time).

Accordingly, an object of the present invention is to provide a VRAM access method that improves the man-machine interface by quickly switching planes when displaying and editing high-definition images.

[Means to solve the problem]

In order to achieve the above object, in the present invention, as shown in FIG. 1, a read bank setting section 1 used during reading and a write bank setting section 2 used during writing are provided. The read bank setting unit 1 is provided with a bank setting task 1-1, and the write bank setting unit 2 is provided with a bank setting register 2-1, in which bank numbers to be accessed are set respectively. This bank number is fixedly assigned in advance when the system is started up.

When this bank number is set in the bank setting register 1-1 of the read bank setting section 1, the read bank setting section 1 recognizes the address in the main memory of the bank with this cent number from the bank position instruction table. , access the bank with the set number.

Similarly, when the write processing unit 4 sets the write destination bank number in the bank setting register 2-1 of the write bank setting unit 2, the write bank setting unit 2 selects the bank with this set number. Can access and write data.

In this way, the bank setting register 1-1 for reading and the bank setting register 2-1 for writing are provided independently, so that reading and writing can be performed independently.

[Effect]

Therefore, the read processing section 3 can read image data from, for example, a part of the bank B2, the enlargement processing section 5 can enlarge the image data, and the write processing section 4 can write the image data into a part of the bank B20.

By providing the bank setting register for reading and the bank setting register for writing independently in this way, it becomes possible to operate the reading process and the writing process independently. Therefore, multitasking is possible, and reading and writing operations can be performed in parallel, making it possible to speed up image editing processing.

〔Example〕

An embodiment of the present invention will be described based on FIG.

FIG. 2 shows a configuration diagram of an embodiment of the present invention.

In Figure 2, parts with the same symbols as the map indicate the same parts,
10 is a CPU, 11 is a memory access control unit, 12 is a conversion table, 13 is a main memory, 14 is a display control unit, 15
16 is a display device, 16 is a video output section, 17 is a video signal input processing section, 18 is a video signal conversion processing section, 19 is a keyboard, and 20 is a mouse.

The CPU10 integrally controls the image processing device, and for example, when performing editing processing, there is a reading processing unit 3 that reads image data from each bank, a writing processing unit 4 that writes edited image data, and an image processing unit 3 that reads image data from each bank. It is equipped with an image enlargement processing section 5 and the like that enlarges the image.

The memory access control unit 11 controls access to the main memory 13, and in addition to the read bank setting unit 1 and the write bank setting unit 2, it also stores a conversion table 12 indicating the start address of banks B1 to B36, etc. Equipped with

The main memory 13 is the main memory of the device, and is, for example, a VRAM.
Banks 81 to B36 forming the .

The display control unit 14 performs various controls when displaying data on the display device 15, and performs controls such as detecting a designated position on the display screen and outputting it to the CPU10.

The display device 15 displays the data processed by the device, and in the case of image data, the resulting image is displayed.

The video output unit 16 outputs a video signal,
For example, it is composed of a video camera, etc.

The video signal input processing section 17 has a video signal conversion processing section 18 that converts the analog video signal transmitted from the video output section 16 into a digital video signal, and performs the video signal conversion processing and converts this signal into a VRAM. The data is transmitted to the memory access control unit 11 for writing. At this time, the write destination address to the VRAM, that is, the bank number and address within the bank, are transmitted from the CPU 10 to the write bank setting unit 2.

Next, the operation of the present invention will be explained in the area P of the display device 15.

~ Image of P1 is area P! The case of enlarging editing to P3 will be explained.

(1) When starting up the device, banks 81 to B36 are set in advance on the main memory 13, and the positions of the banks are entered in the conversion table 12 in correspondence with the banks.

(2) An analog video signal transmitted from a video output section 16 such as a video camera is converted into a digital video signal by a video signal conversion processing section 18. This video signal is sequentially transmitted to the memory access control section 11. At this time, the write destination bank number and address are sequentially transmitted from the CPU 10 to the write bank setting unit 2, and are sequentially stored in the banks B1 to B36. In this way V
The video signal stored in the RAM is displayed on the display device 15 by the display control section 14.

(3) Next, the operator presses the edit key on the keyboard 19 and operates the mouse 20 to cut out the positions Pa and Pl on the display device 15. Then, operate the keyboard 19 and mouse 20 to input the display start point P2 of the edited image,
Enter the magnification factor, for example 2.

(4) By inputting these positions Po and Pl, the display control unit 14 detects the positions of these PO, Pi, and Pl (the position of what bit of what horizontal scanning line), and converts them into CP.
Send to Ul0. Based on this, CPU10 uses PG
, Pi's bank number and in-bank address are detected.

Then, these information is notified to the induction processing section 3, and the extraction processing is performed.

At this time, the bank number is set in the register 1-1, so the read bank setting unit 1 accesses the conversion table 12 based on the bank number set in the register 1-1 to obtain the start address of the bank. The in-bank address is concatenated with this to obtain the access destination address of the VRAM, and successive data are sequentially extracted. This is done every time the bank number changes, and thus the image data of the Pa-pt area is sequentially output from the VRAM.

(5) The image data sequentially output in this manner is transmitted to the image enlargement processing section 5. At this time, the positional information of Pa, Pl, and P2 is also transmitted to the image enlargement processing section 5 in addition to the enlargement magnification. Therefore, based on the position information of P2, the bank number and in-bank address of the write start point are recognized. Then, based on this information, the image processing section 5 performs magnification processing, and the calculation results (initial bank number, bank number when changed, address in the bank, image data for that point, etc.) are sequentially written. The data is output to the input processing section 4.

(6) As a result, the write processing section 4 sequentially outputs these to the write bank setting section 2. As a result, the bank number is set in the register 2-2, and based on this, the conversion table 12 is accessed to obtain the start address of that bank, and the in-bank address is concatenated with this to obtain the access destination address. Write data.

(7) Since the display control unit 14 displays the image data written in this way on the display device 15, the image of the PoxPt area is displayed in an enlarged manner starting from the double layer.

In the above description, an example in which a bank is divided into 36 and an example in which an image is enlarged is explained, but the present invention is of course not limited to these.

〔Effect of the invention〕

According to the present invention, by having independent bank setting registers for reading and bank setting registers for writing, reading processing and writing processing can be operated independently, and these processing can be performed in the same VRAM. It becomes possible to execute the image editing process in parallel, thereby speeding up the image editing process. Additionally, since no extra work area is required, processing becomes faster. This speeds up VRAM access, speeds up image editing processing, and improves the man-machine interface.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is a configuration diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of the VRAM plane configuration, Fig. 4 is an explanatory diagram of the bank configuration, and Fig. 5 is a conventional example. It is. 1.--Read bank setting section 2 Write bank setting section 3-.-Read processing section 4.Write processing section Image enlargement processing section

Claims (1)

[Scope of Claims] In an apparatus that has a VRAM configured with a plurality of banks and displays an image by accessing the VRAM by controlling bank switching, there is provided a bank setting means (1-1) for instructing a bank when reading from the VRAM. 1), and bank setting means (2) for specifying the bank when writing.
-1), and is configured such that banks to be accessed can be switched independently during reading and writing.