JP3043077B2 - Frame buffer controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a multi-window display device for displaying a plurality of images on a single display.

[0002]

2. Description of the Related Art As a data display technique for a workstation or a personal computer, a multi-window display method of displaying a plurality of images on a display and executing different processes (programs) in respective windows has become important. By using this display method, the user of the system can simultaneously execute processes such as editing programs and data while simultaneously executing a plurality of programs, thereby improving development efficiency and man-machine interface.

On the other hand, there is a double frame buffer method as a method for stably displaying an image generated by graphic processing. This method is a method in which two frame buffers are prepared for one display. That is,
One of the two frame buffers is used for drawing, and the other is used for image display. When the drawing is completed, these frame buffers are switched so that the completed new screen is displayed instantaneously. This method enables stable and stable screen display.

In recent years, with the widespread use of graphic processing by workstations and personal computers, the need to display graphic images stably in the aforementioned multi-window system has increased.

Conventionally, in this multi-window display system, a system as disclosed in Japanese Patent Laid-Open No. 1-184525 has been used. FIG. 7 is a diagram showing a conventional configuration. Two sets of frame buffers FB1, FB2, frame buffer switch SW
1, SW2, SW3, display control unit DS1, display device DS
P and a processor CPU.

The configuration of the prior art shown in FIG. 7 will be described with reference to the operation explanatory diagram of FIG. Conventionally, one of the two sets of frame buffers (frame buffer FB1) is connected to the display device DSP via the display control unit DS1 for display by the frame changeover switch SW3. Also,
The other receives the output from the processor as non-display (for writing) by the frame switch SW2. Here, when it is necessary to update the display of the window W1 by the process corresponding to the window W1, first, an update screen of the window W1 is drawn in the non-display frame buffer FB2 at that time (FIG. 8B). ), And then the processor switches the frame buffer FB through the changeover switch SW1.
The pixel corresponding to the window W2 is read from 1 and is copied to the frame buffer FB2. Thus, an updated window W1 and a non-updated window W2 are configured in the frame buffer FB2.

Thereafter, by switching the changeover switches SW2 and SW3, the frame buffer FB1 is not displayed, and the frame buffer FB2 is used as a display image, thereby displaying a screen in which only the window W1 is updated. Also, the window W2 operates when it is changed in the same manner as described above.

[0008]

In the above-mentioned conventional technique, when a window is updated, an update screen is drawn in a non-display frame buffer. At this time, information of all non-updated windows is also displayed. Need to be read from the frame buffer and copied to a non-display frame buffer. For this reason, in the related art, there has been a problem that high-speed screen updating is hindered and high-speed screen display cannot be performed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display device capable of managing a display image on a window basis and updating a screen at a high speed.

[0010]

FIG. 1 is a block diagram showing the principle of the present invention. The frame buffers 1 and 2 are memories for storing data to be displayed. Display control information storage means 3
Stores data indicating one of the plurality of frame buffers 1 and 2 corresponding to a specific area. This specific area correspondence is, for example, dot correspondence.

The first selection means 4 reads the instruction data stored in the display control information storage means 3, and selects and outputs the contents of the frame buffer designated by the read data.

[0012]

A frame is allocated according to the window to be displayed, and an instruction signal corresponding to the window is stored in the display control information storage means. For example, when the frame buffer 1 is assigned to the first window and the frame buffer 2 is assigned to the second window, the display control information storage unit 3 stores area information corresponding to each window, that is, display instruction data. Then, when it is to be displayed, the display instruction data in the display control information storage means 3 is read out, the frame buffer instructed there is read, and the display is outputted to the display device. As a result, the information in the frame buffer can be selected according to the necessary window correspondence and the like, and since the information is assigned according to the area correspondence, for example, the dot correspondence, it is not necessary to write the same image to a plurality of memories, and high-speed display is possible.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 2 is a configuration diagram of an embodiment of the present invention. It comprises two sets of frame buffers FB01, FB02, window selection memory WCM01, display control table DCT1, frame buffer changeover switches SW01, SW02, display control section DS, display device DSP, and processor CPU.

The window selection memory WCM01 stores an identification number corresponding to each window displayed on the screen, and specifies a window to be scanned at that time for each pixel at the time of display, for example, according to a raster scan. Further, the display control table DCT1 specifies a frame buffer in which the window in the display state is stored. Under the control of the window selection memory WCM01 and the display control table DCT1, the data output from each frame buffer is selected by the switching mechanism SW2, so that the display state window distributed and drawn in each frame buffer is displayed. It can be displayed on a CRT as one screen.

Further, the operation will be described in detail with reference to FIG. In the initial state (a), it is assumed that the windows W01 and W02 drawn on the frame buffer FB01 are in the display state. Here, when an instruction to update the contents of the window W01 is issued, the processor CPU draws a new window W01 at a corresponding position on the frame buffer FB02. At this time, the changeover switch SW01 is switched to the frame buffer FB02 side for writing.

Next, the processor CPU sets the element corresponding to the window W01 of the display control table DCT1 to 0 (representing the frame buffer FB02). Thus, the window W01 on the frame buffer FB01
Is not displayed, and the window W01 on the frame buffer FB02 is displayed. Frame buffer FB01,
The output of FB02 is applied to a changeover switch SW02, and the changeover switch SW02 is connected to the display control table D described above.
The switch position is selected in dot units according to the information of CT1.

The window W02 is a frame buffer FB.
01 is kept in the display state. Thereby, the window W02 of the frame buffer FB01 and the window W0 of the frame buffer FB02 are displayed on the display screen.
1 will be displayed at the same time. With this configuration,
It is not necessary to copy a non-updated window from one frame buffer to the other frame buffer, and a high-speed screen update can be achieved.

FIG. 4 is a block diagram of another embodiment of the present invention. In FIG. 4, the frame buffers FB11, FB1
2. Window selection memory WCM2, display control table DCT2, frame buffer changeover switch SW1,
SW2, a display control unit DS, a display device DSP, a drawing control table GCT2, and a processor CPU.

The frame buffers FB11 and FB12 are 1280 × 1024 × 24 bits (8 for each of RGB).
Bit), and has two independent ports for drawing and displaying. Thus, the configuration is such that addresses can be independently set in the frame buffer FB11 and the frame buffer FB12 from the respective ports and reading and writing can be performed simultaneously.

Upon receiving the screen scanning address generated by the display control unit DS from the display port, the contents stored in the frame buffers FB11 and FB12 are sequentially output to the changeover switch SW12, and the display control table DCT2
According to the contents of the above, either the frame buffer FB11 or the frame buffer FB12 is selected for each pixel by the changeover switch SW12, and is output to the display control unit DS.

On the other hand, in the drawing port, that is, in the storage, an address is set by the processor CPU, and the changeover switch S is set based on the contents of the drawing control table GCT2.
The frame buffer FB11 or FB12 is selected by W11, and data is written.

The display controller DS generates a screen scanning address, fetches the data selected by the changeover switch SW12, and after D / A conversion, outputs an analog image signal to a display device DSP which is a CRT.
To display.

The window selection memory WCM2 is also composed of a two-port memory having the same size as the frame buffers FB11 and FB12. Window selection memory WCM2
Stores an identification number for distinguishing a window for each pixel when a new window is generated or the position of an existing window is changed. One of the two ports receives the screen scanning address generated by the display control unit DS, and the content (the identification number of the window at each point of the screen scanning) is output to the display control table DCT2. The other port has two modes. The first is the processor CP
U, an address is set, and the content (the identification number of the window at that address) is stored in the drawing control table GCT.
The second mode is a mode for reading and writing the contents of the window selection memory directly from the processor.
When generating a new window or changing the position of an existing window, the processor CPU designates the second mode and stores the window identification number in the window selection memory WC.
Set to M2.

The drawing control table GCT2 and the display control table DCT2 are tables having elements corresponding to the maximum number of windows to be generated on the screen, and their addresses correspond to window numbers and the contents correspond to frame buffers. In the configuration of FIG. 4, since the number of frame buffers is two, it is 1 bit. These are control of data writing from the processor CPU to the frame buffers FB11 and FB12, respectively,
The selection of data output from the FB 12 is controlled. Further, each table is connected to the processor, and its contents can be changed by software on the processor.

FIG. 5 is an explanatory diagram of drawing control to the frame buffer. When updating the contents of the window, two frame buffers FB are used to eliminate disturbance of the display screen.
11, the switch SW11 is controlled so that writing is performed to the frame buffer in a non-display state with respect to the window to be drawn. Specifically, when drawing from the processor CPU to a certain address of a certain window, the pixel can be drawn first by referring to the window selection memory WCM2 (whether or not the window has priority or whether or not the window has priority). Check if it is on the top surface). If drawing is not possible, the next pixel is tested. If drawing is possible, the contents of the corresponding address (window identification number) in the window selection memory WCM2 are output to the drawing control table GCT2, and this window selection memory WCM2 is output.
2, the number of the frame buffer in the non-display state (writable) corresponding to the window is output from the drawing control table GCT2, and the changeover switch SW11 controls the write signal from the processor CPU to control the non-display state frame. Drawing is performed on the buffers FB11 and FB12.

FIG. 6 is an explanatory diagram of display control of the frame buffer. In displaying a screen, a proper display screen is generated by sequentially selecting a frame buffer in a display state for each window in accordance with screen scanning, for example, raster scanning. Specifically, the window selection memory WCM2 is referred to by the display scanning read address generated by the display control unit DS. This reference identifies the window at the time of the scan. That is, it is determined which window should be designated. Then, by referring to the corresponding element of the display control table DCT2 and identifying the frame buffer in the display state with respect to the window, only the window in the display state on the designated frame buffer is selected to configure the display screen. I do.

[0027]

According to the present invention, it is not necessary to redraw or copy a non-updated window when updating a window, so that a multi-window system can provide a high-speed man-machine interface.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of the present invention.

FIG. 4 is a configuration diagram of another embodiment of the present invention.

FIG. 5 is an explanatory diagram of drawing control on a frame buffer.

FIG. 6 is an explanatory diagram of display control of a frame buffer.

FIG. 7 is a conventional configuration diagram.

FIG. 8 is a diagram illustrating a conventional operation.

[Explanation of symbols]

 1, 2 frame buffer 3 display control information storage means 4 first selection means

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-158393 (JP, A) JP-A-2-11795 (JP, A) JP-A-62-276588 (JP, A) JP-A-61-276 238089 (JP, A) JP-A-60-176093 (JP, A) JP-A-60-32091 (JP, A) JP-A-3-105388 (JP, A) JP-A-62-127885 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G09G 5/14

Claims (5)

(57) [Claims] And 1. A plurality of frame buffers for each specific area, the identification information corresponding to each of the window
And storing identifying information storage means, corresponding to the identification information
The frame in which the displayed window is stored.
A display control information storage means to store the display instruction data specifying Mubaffa, on the basis of the identification information and the display instruction data, a first selecting means for outputting reads the contents from the frame buffer, to have a Characteristic frame buffer control device. Wherein said the each specific area, the frame buffer control instrumentation <br/> location according to claim 1, characterized in that the each dot. Wherein frame of the display control information storage Hand stage or al the display of instruction data read of claim 2, wherein a reading order of scanning for display on the display means
Buffer controller . 4. An input data corresponding to the identification information.
Wherein the drawing control information storage means to store the input instruction data specifying a writable frame buffer further comprises a second selecting means for applying input data to the frame buffer instructed by the input instruction data, that The frame according to any one of claims 1 to 3,
Buffer controller . 5. The method according to claim 5, wherein the identification information and the display instruction data are
Further comprising processing means for setting, wherein the processing means
By setting the identification information and the display instruction data,
And the windows in the display state are stored for each window.
Switch the frame buffer that is The frame according to any one of claims 1 to 4, wherein
Buffer controller.