JPH10164348A - Data edit control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute editing and copying of data in a bit unit at a high speed. SOLUTION: Editing object data are stored in an editing object data storage part 4, edge data being head and last data in a data editing area are stored in an edge data storage part 2 and editing information of a position and a size of the editing object data and the data editing area are stored in a area setting part 3. An end data synthesis part 6 synthesizes the head and the last data from the editing object data storage part 4 with the data from the edge data storage part 2 in the unit of one byte. Moreover, a data synthesis part 7 synthesizes the other data than the head and the last data of the editing object data from the end data synthesis part 6 with data which are not synthesized previously from a holding data storage part 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data editing control circuit, and more particularly to a data editing control circuit capable of allocating page data in bit units.

[0002]

2. Description of the Related Art A conventional bit map control circuit reads a field of a memory to be edited once, edits data, and then returns the field to a field again.
Data editing is performed by two cycles of writing.

FIG. 5 is a block diagram showing the prior art. Referring to FIG. 5, a conventional bitmap control circuit includes a read data register unit 8, a data combining unit 9,
It comprises a read register decoding unit 10, a data synthesis format setting unit 11, an editing target data register unit 12, and an editing target register decoding unit 13.

First, data in an editing area to be written is read and stored in the read data register section 8. Then, the edit target data is stored in the edit target data register unit 12. The stored data is output by the read register decoding unit 10 and the editing target register decoding unit 13 to output an arbitrary number of data, and the combined data is combined by the data combining unit 9 in accordance with the format set by the data combining format setting unit 11. Editing control is performed to write in the editing area.

[0005] For example, see Japanese Patent Application Laid-Open No. Hei 3-22086.
No. 3, Japanese Patent Application Laid-Open No. 3-43281 also reads the field of the memory to be edited once,
After editing the data, the data is returned to the field again, and the data is edited in two cycles of read / write.

[0006]

In the above-mentioned prior art, since one-byte data is edited by a read / write cycle, there is a problem that data processing takes a long time. In addition, since data is edited by re-reading even in the editing area once set and confirmed in the editing area, there is a problem that data processing takes time.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data editing control device which reduces control time by reducing data reading from a data editing area as much as possible, thereby improving control efficiency as a whole.

[0008]

A first data editing control circuit according to the present invention comprises: (a) an origin, width, and width of a data editing area;
An area setting unit for storing editing information including a vertical width and an origin, a horizontal width, and a vertical width of the editing target data written in the data editing area; and (b) an editing target data storing unit for storing the editing target data. (C) an edge data storage for storing edge data at both ends of the data editing area; and (d) end data for combining data from the data to be edited with data from the edge data storage. A combining unit; (e) a pending data storage unit for storing, as pending data, a portion of the data to be edited that has not been composed by the end data compositing unit; and (f) data from the pending data storage unit and the end data. A data synthesizing unit 7 for synthesizing data from the synthesizing unit; and (g) the data editing area based on the edge data in the edge data storage unit. Holding the positions of both ends, and a region edge recognition section for controlling the end data combining unit and the data combining unit.

The second data editing control circuit according to the present invention is the first data editing control circuit, wherein the first data editing control circuit receives the data from the editing target data storage section based on a bit position indicated by the origin of the data editing area. 2. The data editing control circuit according to claim 1, further comprising the end data synthesizing unit that discards and joins data from the edge data storage unit.

A third data editing control circuit according to the present invention is the first data editing control circuit, wherein the first data editing control circuit receives a signal from the end data synthesizing section based on a bit position indicated by the origin of the data editing area. 2. The data editing control circuit according to claim 1, further comprising the data synthesizing unit that discards and joins data and data from the reserved data storage unit.

[0011]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

In the following description, the term “synthesis” refers to a combination of a part of 1-byte data of data to be edited and edge data, and a part of 1-byte data that has not been combined with the data to be edited in the previous composition. , Means joining with a part of the data to be edited this time.

FIG. 1 is a block diagram showing a data editing control circuit according to the present invention. Referring to FIG. 1, a data editing control circuit according to the present invention includes an editing target data storage unit 4 for storing editing target data to be edited, an edge data storage unit 2 for storing data at both ends of a data editing area. An area setting unit 3 for storing a data editing area and editing information such as a position, a vertical width and a horizontal width of data to be edited, and a pending data storage unit 1 for storing data immediately before the current editing.
An end data synthesizing unit 6 for synthesizing the first and last data of one row from the output of the edge data storage unit 2 and the output of the destination data storage unit 4; A data synthesizing unit 7 for synthesizing the output of the synthesizing unit 6 and the output of the pending data storage unit 1, and an area edge recognizing unit 5 for recognizing the positions of both ends of the data editing area
It is composed of

FIG. 2 is a diagram showing the relationship between the data to be edited and the data editing area. Referring to FIG. 2, the data to be edited is aligned on a 1-byte boundary, and is divided and copied at specified intervals in a data editing area that is not aligned on a 1-byte boundary at specified intervals. You.

FIG. 3 is an explanatory diagram showing a data editing area. Referring to FIG. 3, the data editing area according to the present invention includes, as editing information, an origin indicating the head of the area,
It is represented by a horizontal width indicating the length of one line and a vertical width indicating the total number of lines. Also, the first data (1 byte) at the beginning of each line
Then, the last end data (1 byte) is combined with the data to be edited (1 byte) with a shift of the designated bit. The rest of the data to be edited that has not been combined becomes pending data.

Copying is performed using one line as a basic unit as shown in FIG. Although addresses are continuous in one row, the end address of the row and the start address of the next row are not continuous. Therefore, the start address from the second row is generated by adding an offset address to the start address of the previous row.

The origin of the data editing area corresponds to the fifth bit of the head address. If the copy source data is copied as it is, it is impossible to write up to the fourth bit of the byte data in the data editing area. In order to avoid this and copy the data of the copy source from the origin position, 4 bits of the copy source data and 4 bits of the edge data are combined into 1-byte data. Then, the 4-bit data that has not been combined in the copy source data is set as pending data, combined with the next copy source data, and copied to the data editing area. By performing this operation from the beginning to the end of the data editing area, data can be copied to the data editing area in bit units.

FIG. 4 is a flowchart showing the operation of the data editing control circuit of the present invention. Referring to FIG. 4, first, in the flow of the present invention, a data editing area is set. Specifically, a setting is made of the start address of the area, the bit number of the address as the origin, the total data amount, and the vertical and horizontal widths. Then, the editing data is set. Specifically, a start address, a data amount, and a width and a width are set. After the setting of the data editing area and the data to be edited is completed, the editing is started by the data editing start command.

Next, the operation of the present invention will be described with reference to the drawings. First, in order to determine the data editing area, the start address, the origin indicating the bit number of the address, and the vertical and horizontal widths of the area are set in the area setting unit 3 (step 1 in FIG. 4). Next, the start address and the vertical and horizontal widths of the data to be edited are set in the area setting unit 3 (Step 2 in FIG. 4). Then, after the setting of the area is completed, the data editing control circuit is started (step 3 in FIG. 4).

First, data at both ends of the data editing area are read and stored in the edge data storage unit 2. Further, the edit target data is stored in the edit target data storage unit 4. Then, the first data of the edit target data in the edit target data storage unit 4 (the first one byte data of one line)
And the edge data in the edge data storage unit 2 by the end data synthesizing unit 6 according to the set format,
The data is output to the data synthesizing unit 7 as synthesized first data. The synthesized first data is output from the data synthesizing unit 7 without being synthesized with the reserved data. The remaining part of the first data of the data to be edited is held in the suspended data storage unit 1.

From the next data to the second data from the end of one row, the pending data storage 1
And the output of the end data combining unit 6 are combined by the data combining unit 7 and output.

Finally, the output for the end data (the last one byte data of one row) from the edge data storage unit 2 and the end data from the edit target data storage unit 4 are synthesized by the end data synthesis unit 6. Then, the output of the pending data storage unit 1 is re-synthesized and output by the data synthesizing unit 7 (FIG. 4).
Step 5).

The data editing control circuit of the present invention repeats the control sequence of one line for the number of vertical widths set in the area setting section 3 (step 6 in FIG. 4), and ends the editing control (step 7 in FIG. 4). ).

The area setting section 3 counts the number of horizontal width data (from first data to end data) and the number of vertical widths in one line, and controls the area of the editing area and the end of editing. The number of widths is one cycle (1 byte synthesis,
Is counted in the area setting unit 3 every time the writing is started.
A signal indicating the end is output. Then, the area edge recognition unit 5 controls the synthesis of data according to the input data. Further, the number of vertical widths is counted in the area setting section 3, and after the counting is completed, the data editing control ends.

By this series of operations, bit map control in page units can be performed at high speed.

When another editing is to be performed within the same set data editing area, the data at both ends of the data editing area has already been stored in the edge data storage unit 2, and the data must be edited without a reading operation. Can be.

[0027]

The effect of the present invention is that the data processing can be performed in about half the time required for the data edit control for performing the normal read modify by performing only the write operation except for both ends of the data edit area.

When data is edited using the same data editing area, the editing can be performed completely only by the write operation, and the control time can be further reduced.

The second effect is that the circuit configuration can be simplified and the size can be reduced by allocating the functions in units of pages.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a relationship diagram between data to be edited and a data editing area.

FIG. 3 is an explanatory diagram showing a data editing area.

FIG. 4 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 5 is a block diagram of a conventional technique.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 reserved data storage unit 2 edge data storage unit 3 area setting unit 4 edit target data storage unit 5 area edge recognition unit 6 end data synthesis unit 7 data synthesis unit 8 read data register unit 9 data synthesis unit 10 read register decode unit 11 data Synthetic format setting unit 12 Data register unit to be edited 13 Register decoding unit to be edited

Claims (3)

[Claims] (A) an area setting unit for storing editing information including an origin, a width, and a vertical width of a data editing area and an origin, a width, and a vertical width of data to be edited written in the data editing area; b) an edit target data storage section in which the edit target data is stored; (c) an edge data storage section in which edge data at both ends of the data edit area are stored; An end data synthesizing unit for synthesizing data and data from the edge data storage unit; and (e) a reserved data storage unit for storing, as reserved data, a portion of the data to be edited that is not synthesized by the end data synthesizing unit. (F) a data synthesizing unit 7 for synthesizing data from the reserved data storing unit and data from the end data synthesizing unit; Serial based on the edge data, the holding positions of both ends of the data editing area, said end data synthesizing section and said a region edge recognition unit that controls the data synthesizer, data editing control circuit characterized in that it comprises a. 2. The end data synthesizing unit which discards and joins data from the data to be edited and data from the edge data storage based on a bit position indicated by the origin of the data editing area. 2. The data editing control circuit according to claim 1, comprising: 3. The data synthesizing unit which discards and joins data from the end data synthesizing unit and data from the reserved data storage unit based on a bit position indicated by the origin of the data editing area. 2. The data editing control circuit according to claim 1, wherein: