JP2000105993A - Register circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a register circuit for writing and reading data to read the data with the absolute minimum circuit. SOLUTION: This circuit is provided with a memory 20 in which, when data 14 are written in a register 10 in a timing when a clock 13 which is to be generated by a write signal and a signal in which an address signal 12 is decoded in a decoding circuit 30 is to be inputted to the register 10, the same data as the data written in the register 10 are to be stored simultaneously with it and at the time of reading the data in the register, when a read signal 15 is inputted to the memory 20, the data stored in the specified address 12 of the memory 20 are outputted to read the data of the register 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to reading data from a register circuit, and more particularly, to a register circuit capable of reading data stored in a register of the register circuit with a minimum number of circuits.

[0002]

2. Description of the Related Art Conventionally, electronic equipment has a register for holding data in an internal circuit, and data is written to the register by controlling a write signal input from the outside. When the read data is read from the register, the data is read via a readback circuit under the control of a read signal input from the outside.

In particular, in reading data, a readback circuit for reading the contents of data held in a register is provided. When reading data,
When a read signal is input from the register holding the data to the readback circuit, the data of the register is read by returning the data of the register to the data bus.

FIG. 2 is a diagram showing a configuration of a conventional register circuit 100.

The register circuit 100 includes a register 10 for holding data, a decode circuit 30 for detecting a specific address, a readback circuit 40 for reading data held in the register 10, a gate 50, and a gate 60. The address 12 is transmitted through an address bus 70, and the data 14 is transmitted through a data bus 80.

[0006] The readback circuit 40 holds data output from the output terminal Q of the register 10 when the data 14 is written to the register 10. Therefore, data having the same contents as the data held in the register 10 is held. When a signal generated by calculating the logical product of the signal obtained by decoding the address 12 by the decode circuit and the read signal 15 is input to the read terminal RD of the read back circuit 40, the read back circuit The data held by 40 is returned to data bus 80.

Therefore, the provision of the readback circuit 40 makes it possible to read data held in the register 10.

Next, data write and read operations in the conventional register circuit 100 will be described.

When writing data to the register 10,
A write signal 11 input from the outside and a signal obtained by decoding the address 12 by the decode circuit 30 are applied to a gate 50.
When the clock 13 generated by calculating the logical product in the gate 50 is input to the clock terminal CK of the register 10, the data 14 is input to the input terminal D of the register 10 at this timing. ,
Data 14 is held in the register 10.

When reading the data held in the register 10, a read signal 15 input from the outside and a signal obtained by decoding the address 12 by a decoding circuit 30 are input to a gate 60, and a logical product is calculated in the gate 60. Is input to the read terminal RD of the readback circuit 40,
Data from the data bus 8 through the readback circuit 40.
By outputting to 0, the data held in the register 10 is read.

[0011]

However, when a plurality of registers 10 are provided in the register circuit 100 in the data reading operation of the conventional register circuit 100, data having the same contents as those of the registers 10 are respectively stored. In order to hold the data, it is necessary to provide the same number of readback circuits 40 as the registers 10. Therefore, as the size of the system increases and the number of registers 10 increases, the number of readback circuits 40 also increases, which causes a problem that the entire circuit of the system becomes very large.

An object of the present invention is to provide a register circuit capable of reading data with a minimum circuit when there are a plurality of registers in order to solve such a problem.

[0013]

According to the first aspect of the present invention,
A register circuit that writes and reads data to and from a register by controlling a write signal and a read signal input from the outside stores the same data as the write data to the register, and controls a read signal input from the outside. And a memory for outputting the data stored in the memory.

According to the register circuit of the present invention, in a register circuit for writing and reading data to and from a register by controlling a write signal and a read signal input from the outside, Store the same data in memory as
The data stored in the memory is output under the control of a read signal input from the outside.

Therefore, instead of a readback circuit for reading data, it is possible to read data written in a register using a memory, so that it is not necessary to prepare as many readback circuits as there are registers. In addition, the configuration of the register circuit can be simplified.

In this case, the above object is achieved, for example, by claim 2
In the register circuit according to the first aspect of the present invention, a decoding circuit for detecting that a specific address is specified, a specified address detected by the decoding circuit, and a write signal input from the outside. From
A clock generation circuit that generates a clock signal and outputs the clock signal to a register at a specified address, wherein the register writes data at a timing at which a clock signal output by the clock generation circuit is input, and the memory Stores the same data as the write data to the register at a specified address in synchronization with a clock signal output by the clock generation circuit, and when a read signal is input to the memory by specifying an address. It is effective to output the data stored at the specified address.

According to the register circuit of the second aspect of the present invention, in addition to the effect of the first aspect of the present invention, it is possible to write and read data to and from the register and the memory by specifying an address. And,
Since writing to the register and writing to the memory are performed at the same timing, it is possible to provide a register circuit that performs an efficient writing operation.

The object of the present invention is to provide a register circuit according to a second aspect of the present invention, wherein an address bus is connected to the decode circuit and the memory, and the data write operation is performed. Since the designated address is simultaneously input to the decode circuit and the memory via the address bus, circuit wiring can be simplified, and even when a memory is used, production costs can be reduced. be able to.

In the register circuit according to the third aspect of the present invention, the memory inputs a clock signal generated by the clock generation circuit as a data write signal. By writing data to the designated address input from the data bus in synchronization with the input timing of the data write signal, even if a memory is used, the control signal wiring can be simplified to reduce the production time. Costs can be reduced.

According to a fifth aspect of the present invention, in the register circuit of the first to fourth aspects, the memory includes a plurality of storage areas for storing data corresponding to the plurality of registers. It is effective to use at least one memory.

According to the register circuit of the fifth aspect, in addition to the effects of the first to fourth aspects, a plurality of registers are provided by using a memory having a capacity corresponding to the amount of data to be written into the register. Even in such a case, since the circuit can be configured with the number of memories being minimized, the circuit scale can be reduced.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a register circuit 1 according to the present invention will be described in detail with reference to FIG. FIG.
FIG. 1 is a diagram showing a configuration of a register circuit 1 of the present embodiment.

First, the configuration will be described. As shown in FIG. 1, the register circuit 1 includes a register 10, a memory 20, a decode circuit 30, and a gate 50. The address 12 is transmitted by an address bus 70, and the data 14
Is transmitted by the data bus 80.

This register circuit 1 is conventionally provided with a register 1
When reading the data held in 0, the data read from the readback circuit 40 (see FIG. 2) is replaced with the data written in the memory 20 at the same time the data is written in the register 10. When reading data, data at a specified address is read from the memory 20 in which the data is written.

That is, in the register circuit 1 of the present invention,
When writing data to the register 10, a clock 13 generated by a write signal 11, which is a signal for controlling writing, and a signal obtained by decoding an address 12 specifying a write destination address by a decode circuit 30 is input to the register 10. At the same time, a memory 20 for storing the data 14 at the same time as writing the data 14 to the register 10 is provided.

When reading data, the data at the specified address is read by the read signal 15 which is a signal for controlling the reading of data from the memory 20 in which the data is stored and the address 12 specifying the read destination. The data held in the register 10 is read by returning the data to the data bus 80.

Hereinafter, the configuration of the register circuit 1 will be described in detail. When the write signal 11 and the signal obtained by decoding the address 12 by the decode circuit 30 are input to the gate 50, and the clock 13 generated by the gate 50 is input to the clock terminal CK, the data 10 13 is input from the input terminal D at the input timing. The register 10 holds the input data 14 and outputs the held data from the output terminal Q to the outside.

In the memory 20, a write signal 11 and a signal obtained by decoding the address 12 by the decode circuit 30 are input to a gate 50, a clock 13 generated by the gate 50 is input to a write terminal WR, and data 14 Is input from the data terminal D, the address 12
Saves the data 14 at the address specified by. The timing for writing data to the memory 20 is the same as the timing for writing data to the register 10.

A read signal 15 for controlling data reading is input from a read terminal RD of the memory 20.
When the address 12 is input to the address input terminal AD, data is output from the data terminal D from the address specified by the address 12 and returned to the data bus 80.

It is necessary to provide one or more memories 20 according to the number of registers and the capacity of the memory 20.

The decode circuit 30 detects that a specific address has been designated, decodes the address designated by the address 12, and outputs the decoded signal to one terminal of the gate 50. I do.

The gate 50 calculates the logical product of the write signal 11 for controlling the writing of the data 14 and the signal obtained by decoding the address 12 for specifying the address to which the data is to be written by the decoding circuit 30, and generates the clock 13 to generate the clock 13. 10 and outputs the clock 13 to the write terminal WR of the memory 20 at the same time.
Output to

Next, the operation will be described. When writing data to the register 10, the gate 50 performs a logical product operation on the basis of a write signal 11 for controlling data writing and a signal obtained by decoding the address 12 by the decoding circuit 30, and generates the clock 13. Data 14 is written to the register 10 at the timing when the generated clock 13 is input to the clock terminal CK of the register 10. At the same time, the clock 1 is also applied to the write terminal WR of the memory 20.
When the clock 3 is input and the clock 13 is input, the data 14 is input to the data terminal D of the memory 20 with respect to the address specified by the address 12.

When reading the data held in the register 10, when a read signal 15 for controlling the reading of data is input to the read terminal RD of the memory 20,
Data is read from the address specified by the address 12 input to the address input terminal AD of 0, and is returned as data 14.

As described above, the register circuit 1 according to the present embodiment uses the address 12, clock 13, data
The data is written to the memory 20 by using the address 12 and the read signal 15 at the time of reading the data.
0 is transferred to the data bus 80.
To return.

Therefore, the conventional readback circuit 40
As in the case of (see FIG. 2), by designating the address of the memory 20, desired data can be read.

Further, even when the register circuit 1 has a plurality of registers, the memory 20 can hold the data held in each register as long as the capacity permits. By inputting a read signal to the memory 20 while designating an address, desired data can be read.

As a result, the same number of readback circuits as the number of registers can be used instead of the same number of memories, so that the circuit scale can be minimized.

[0039]

According to the first aspect of the present invention, it is possible to read data written in a register using a memory instead of a readback circuit for reading data. It is not necessary to prepare a read-back circuit, and the configuration of the register circuit can be simplified.

According to the second aspect of the present invention, it is possible to write and read data to and from a register and a memory by designating an address, and furthermore, writing to a register and writing to a memory are the same. Therefore, it is possible to provide a register circuit that performs an efficient write operation.

According to the third aspect of the present invention, the circuit wiring can be simplified, and the production cost can be reduced even when a memory is used.

According to the fourth aspect of the present invention, even when a memory is used, the production cost can be reduced by simplifying the control signal wiring.

According to the fifth aspect of the present invention, by using a memory having a capacity corresponding to the amount of data to be written into the register, the number of memories can be minimized even when there are a plurality of registers, and the circuit can be reduced. Since it can be configured, the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a register circuit 1 according to the present invention.

FIG. 2 is a diagram showing a configuration of a conventional register circuit 100.

[Explanation of symbols]

 Reference Signs List 1 register circuit 10 register 20 memory 30 decode circuit 50 gate 11 write signal 12 address 13 clock 14 data 15 read signal

Claims (5)

[Claims] 1. A register circuit for writing and reading data to and from a register by controlling a write signal and a read signal input from the outside, wherein the register circuit stores the same data as the write data to the register and receives the data from the outside. A memory for outputting data stored under the control of a read signal. 2. A decoding circuit for detecting that a specific address has been designated, and a clock signal generated from a designated address detected by the decoding circuit and a write signal inputted from the outside, to register the designated address. A register that writes data at a timing when a clock signal output by the clock generation circuit is input; and the memory outputs the clock by the clock generation circuit. In synchronization with the clock signal, the same data as the write data to the register is stored at a specified address, and when a read signal is input to the memory by specifying an address, the data stored at the specified address is stored. 2. The register circuit according to claim 1, wherein the register circuit outputs a signal. 3. An address bus is connected to the decoding circuit and the memory, and a designated address at the time of writing the data is simultaneously input to the decoding circuit and the memory via the address bus. The register circuit according to claim 2. 4. The memory inputs a clock signal generated by the clock generation circuit as a data write signal, and transfers data to a designated address input from the data bus in synchronization with an input timing of the data write signal. 4. The register circuit according to claim 3, wherein said register circuit is written. 5. The memory according to claim 1, wherein said memory comprises at least one memory having a plurality of storage areas for storing data corresponding to the plurality of registers. Register circuit.