JPH10164170A - Formatter and method for controlling the formatter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a formatter and a formatter control method whereby fixed length data is outputted to a device (system) which processes output data of the formatter. SOLUTION: Data writing end information from a data writing end monitoring part 6 is received and also an operation is shifted to the change-over operation of a double buffer 1 when a data leading signal is inputted. Therefore, when the data leading signal is inputted before prescribed-sized data is written, a double buffer change-over control part 7 is not shifted to the operation for changing-over the double buffer 1 but it keeps reading. Since a writing side resets an writing address by the input of the data leading signal, succeeding conversion object data is overwritten on illegal data where writing is not finished. A unobtained data information control part 10 fetches overridden position information to an outside.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a formatter and a formatter control method, and more particularly to a formatter for converting input data into a predetermined format and a formatter control method.

[0002]

2. Description of the Related Art As a conventional formatter, there is a method of real-time data format conversion using a double buffer. This double buffer is composed of two buffer memories. When one buffer memory is writing data, the other buffer memory is reading data. The format conversion is performed by changing the order in which the read addresses are written.

Each of the above two buffer memories usually has a capacity capable of holding (storing) one line of data, and when the storage of one line of data is completed in one buffer memory, the reading side of the buffer memory is read. This is performed in a time-division manner such as switching the buffer memory to another system. In many cases, since the length of one line of data is fixed, a method of switching between the buffer memory on the write side and the buffer memory on the read side by inputting a signal indicating the beginning of data is adopted. That is, control by the toggle operation is performed.

As a matter of course, if the reading is not faster than the writing, the written data cannot be read completely. Therefore, a method of making the reading rate higher than the writing rate is adopted. For example, even for variable-length data, there is no data having an extremely different data length. Therefore, if the read rate is set to be somewhat higher than the write rate, the data cannot be read completely.

[0005] The data synchronized in the synchronization section at the preceding stage of the formatter is output in a fixed length. Also,
The data is controlled to have a fixed length even when synchronization is lost.

[0006]

However, in the above-mentioned conventional formatter, if the pseudo-lock of the synchronizing unit or the variable-length data is not synchronized for a long time and locked at a certain timing, the data input to the formatter is lost. When the data becomes extremely short (a signal indicating the beginning of the data is input much earlier than in the normal case), the normal data stored in the double buffer at that time may not be completely read out, Shorter data is output. The reason is that since the double buffer is always switched by the signal indicating the head of the data, the double buffer is switched before the data on the read side of the double buffer is completely read.

For this reason, when data that is extremely shorter than the data length to be processed is output, a so-called level 0 data format (that is, serial data is converted into parallel data having some meaning, respectively), and (A format in which a header is added to parallel data having a predetermined number of words) becomes invalid and cannot be processed. Further, in a device (system) that processes output data of a formatter, the length of the data needs to be constant.

Further, in the conventional formatter described above, if a low-rate data, in particular, data of a small size of one format is read out from a double buffer at a high speed, a period shorter than a normal period of one format due to a pseudo lock or the like. The double buffer is switched.
In this case, even at a stage where writing to the double buffer is not completed, data reading is completed even in a period shorter than one format due to high-speed data reading and a low-speed data rate, so that illegal data is read. It becomes possible to read data at an appropriate size, and as a result, incorrect data is inserted for one format, which causes a problem that causes an abnormality in the next processing.

[0009] The present invention has been made in view of the above points,
A device (system) that processes the output data of the formatter
It is an object of the present invention to provide a formatter capable of outputting fixed-length data to a computer and a method of controlling the formatter.

Another object of the present invention is that the data input to the formatter is extremely short (a signal indicating the beginning of the data is input extremely quickly compared to a normal case).
It is an object of the present invention to provide a formatter and a control method of the formatter which can output the information at the time to a device (system) which processes output data of the formatter, thereby guaranteeing data quality and the like and improving data reliability. .

[0011]

In order to achieve the above object, the present invention has a first buffer and a second buffer, in which input data is written to one buffer to perform data format conversion, and the other is written to the other buffer. A double buffer for reading stored data from the buffer, and a write address for writing input data to a buffer on the write side of the double buffer, a write address generated in synchronization with an external input data head signal indicating the beginning of a predetermined unit of input data. A generating unit for supplying a read address set from the outside to a buffer on the read side of the double buffer for format conversion of input data and multiplexing of additional information, and reading data from the buffer on the read side at a rate higher than the write rate. Read control means for reading and additional information when inputting the data head signal The additional information control unit to be embedded, the data write end monitor unit that monitors the end of the writing of the input data to the write buffer of the double buffer, and the data head signal and the end information output from the data write end monitor unit are both input. The double buffer switch control unit that switches the buffer on the write side of the double buffer to the read side, and switches the buffer on the read side to the write side, and outputs the additional information from the additional information control unit and the output data of the double buffer. And a multiplexing unit for multiplexing and outputting.

In the present invention, the double buffer is switched when both the end information and the next data head signal are input. Therefore, even if the data head signal is input before the end information is input. Therefore, the switching of the double buffer is not performed, so that the reading does not end halfway and unnecessary data is not stored in the double buffer.

According to the present invention, when a data head signal is input before end information is input to the double buffer switching control unit, unacquired data information indicating the position is generated and output. Since the information control unit is further provided, the overwritten position information of the buffer that has been written halfway can be extracted to the outside.

Further, according to the control method of the present invention, one of the first and second buffers writes input data, the other buffer reads stored data at a higher rate than the write rate, and communicates with the write side. The read address of the double buffer in which the read side is alternately switched is set externally, and the write address is generated in synchronization with the data head signal indicating the beginning of the data for each predetermined unit of the input data, and the input data is converted from the double buffer. A method of controlling a formatter having a configuration in which additional information and time information are multiplexed and read out together with the read out data, wherein end information output when the input data has been written into the write-side buffer of the double buffer and data start-up When both signals are input, the The buffer on the read side is switched to the read side, and the buffer on the read side is switched to the write side. If the data head signal is input before the end information is input, the position at that time is acquired, and the data is output to the outside. It is output as acquired data information.

Since input data having an extremely short length can be determined to be unnecessary data, there is no need to write this data to the formatter. Therefore, the double buffer is basically switched by the data head signal, but if the data head signal comes before the writing is completed, the double buffer is not switched. That is, there is end information, and
The control method is such that the double buffer is switched when the data head signal comes. For this reason, the input data having an extremely short length is not written in the double buffer, so that the read data always has a fixed data length.

Further, it is possible to prevent data of a predetermined size from being read from the double buffer in a write-incomplete state at a low data rate. Further, information indicating where extremely shortened data is ignored can be output to the outside.

[0017]

Next, an embodiment of the present invention will be described.

FIG. 1 shows a configuration diagram of an embodiment of a formatter according to the present invention. In this embodiment, a double buffer 1 (buffer 1A, buffer 1B) for inputting / outputting data in order to perform data format conversion, and a write address generator 2 for generating an address for writing data in the double buffer 1 A read address setting unit 3 for externally setting a read address of the double buffer 1 for format conversion and multiplexing of additional information, an additional information control unit 4 for fetching additional information for multiplexing the additional information, A clock generation unit 5 for reading data at a high rate, a data write end monitoring unit 6 for monitoring the end of data writing to the double buffer 1 and informing the double buffer switching control unit 7 of end information.
A double buffer switching control unit 7 for controlling the switching of the double buffer 1 based on a signal indicating the start of one block of data and the end information of the data write end monitoring unit 6, an additional information from the additional information control unit 4, and the double buffer 1 And a processor interface unit 9 for receiving control from an external processor.

Further, the present embodiment has, in addition to the above configuration,
A position where input data is ignored (overwriting is performed without switching the double buffer 1) is acquired, and an unacquired data information control unit 10 capable of outputting the acquired position to the outside is added.

Next, the operation of this embodiment will be described.

First, before starting data input, an address for reading from the double buffer 1 for rearrangement for format conversion from an external processor (not shown) via the processor interface unit 9 as an initial setting is set in a read address setting unit. 3 and the data rate for reading is set in the clock generator 5. The data rate to be set is higher than the write data rate. As a result, usually, reading is completed before writing.

Data such as data to be converted, a clock, a data head signal indicating the head of the data to be converted, a signal indicating a range of the data to be converted, additional information, and time information are input to the formatter. When these various data are input to the formatter, the formatter starts operating.
Now, the buffer 1A of the double buffer 1 is on the writing side,
The buffer 1B of the double buffer 1 is on the reading side.

In the method of writing the data to be converted (input data) into the double buffer 1, the write address generator 2 resets the write address of the buffer 1A of the double buffer 1 based on a data head signal indicating the head of the data to be converted. In other words, only when a write address is set to "0" and thereafter a signal indicating the range of the data to be converted is input, the write address generator 2 increments the output write address each time a clock is input from the outside to convert the write address. Data is written into the buffer 1A of the double buffer 1. The additional information and the time information are taken into the additional information control unit 4 by using a data head signal indicating the head of the data to be converted as a trigger.

In the method of reading the data to be converted from the double buffer 1, both the data head signal indicating the head of the data to be converted and the data write end information from the data write end monitoring unit 6 are input to the read address setting unit 3. At the time, the buffer 1B of the double buffer 1 is initialized based on the read address set for rearrangement for format conversion in the read address setting unit 3 via the processor interface unit 9 by the external processor.
Read the data to be converted.

At this time, since the read address setting section 3 changes the output read address in synchronization with the clock from the clock generation section 5, the double buffer 1 operates at the data rate set in the clock generation section 5. Read. At the same time as the start of data reading, the additional information control unit 4 outputs data such as additional information and time information to the multiplexing unit 8 and multiplexes the data on the conversion target data read from the double buffer 1. While data is being read from the buffer 1B, the data write end monitor 6 constantly monitors whether or not all data has been written in the buffer 1A based on the change in the write address. Output end information.

The double buffer switching control unit 7 receives the data write end information from the data write end monitoring unit 6 and, when a data head signal indicating the head of the next data to be converted is input, performs writing until that time. The buffer 1A used for reading is switched to the one for reading, and the buffer 1B used for reading is switched to the one for writing. By repeating the above, data conversion is performed in real time.

Next, if a data head signal indicating the head of the next data to be converted is input before data of a predetermined size is written for some reason, the double buffer switching control unit 7 A data head signal indicating the head of the conversion target data is input from the write end monitoring unit 6 before the data write end information.

In this case, in the case of the conventional formatter, the operation shifts to the switching operation of the double buffer 1 by inputting the data head signal indicating the head of the data to be converted.
In this embodiment, when the data write end information is received from the data write end monitoring unit 6 and a data head signal indicating the head of the next data to be converted is input, the operation shifts to the switching operation of the double buffer 1. It is configured as follows. Therefore, if the data head signal indicating the head of the next data to be converted is input before the data of the predetermined size is written, the data writing ends even if the data head signal is input. Since the data write end information from the data write end monitoring unit 6 has not been input to the double buffer switch control unit 7, the double buffer switch control unit 7 shifts to the operation of switching the double buffer 1. And continue reading.

On the writing side, since the buffer is not switched, the write address generator 2 resets the write address of the buffer 1A of the double buffer 1 by inputting a signal indicating the head of the data to be converted, that is, sets the write address to "0". , The next data to be converted is overwritten on the unwritten data of the buffers 1A and 1B that have not been completely written. Since the illegal data at this time is not processed, there is no problem even if it is overwritten.

Further, in a device (system) at the subsequent stage of the formatter, processing such as adding dummy data to a position of data which is illegal data and is not to be processed may be considered for processing reasons. In the form,
Further, by adding an unacquired data information control unit 10 as an additional function, the overwritten position information can be extracted to the outside.

That is, the unacquired data information control unit 10 obtains the time information or the data indicating the head of the conversion target data from the data head signal indicating the head of the conversion target data and the data write end information from the data write end monitoring unit 6. A count value obtained by counting the head signal is stored, and the time information or the count value is stored in the processor interface unit 9.
To output the time information or the count value to an external processor.

In an apparatus (system) subsequent to the formatter, the multiplexing unit 8 counts the time information multiplexed on the output data of the double buffer 1 and the count value obtained by counting the data head signal indicating the head of the data to be converted. According to information from the unacquired data information control unit 10, dummy data insertion processing and the like are performed as necessary.

[0033]

Next, the configuration of an embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the formatter according to the present invention. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals. In FIG. 2, double buffer 1
Are high-speed static random access memories (hereinafter referred to as SRAMs) 11A and 11B corresponding to the buffers 1A and 1B, and the SRAMs 11A and 11B.
A first changeover switch 11C provided on the input side of B and a second changeover switch 11D provided on the output side,
It is configured to realize high-speed reading and writing of data.
As for the memory capacity of the SRAMs 11A and 11B, the image data amount of one line does not exceed 1 megabyte (1 MB) at present, so the one-system 1 megabyte SRAM, that is, the double buffer 1 has a capacity of 2 megabytes.

A line start signal is used as a data head signal indicating the head of the data to be converted. The write address generator 2 is composed of a 20-bit counter 20 that is reset by an input pulse of a line start signal. The read address setting unit 3 includes an SRAM 31 having a capacity of 3 MB capable of storing a read address of a double buffer from an external processor, and a 20-bit counter 32 for generating a read address of the SRAM 31.

The additional information control unit 4 uses a register 41 that latches additional information and time information at the line start, and uses the address of the read address setting unit 3 to control the multiplexing unit 8.
Is configured to control the buffer enable. The clock generator 5 includes an oscillator 51 that oscillates and outputs a high-frequency signal.
And a variable frequency divider 52 which divides the output high-frequency signal of the oscillator 51 to generate a clock pulse and whose frequency division ratio is variable by setting from an external processor.

The data write end monitor 6 includes a comparator 61 for outputting end information when the write address has been incremented by a predetermined write counter value written in the write address generator 2, an output end information and a line start signal. Performs reset and count-up control of the counter 32 of the read address setting unit 3 by
And a circuit 62.

The double buffer switching control section 7 includes a latch circuit 71 for latching the end information from the data write end monitoring section 6, an AND circuit 72 to which the end information from the latch circuit 71 and the line start are inputted, and an AND circuit 72. Circuit 72
Constituting double buffer 1 by output signal of
Flip-flop (F / F) 73 for generating chip select signals and write enable signals for 11A and 11B
And the SRAMs 11A and 11B by the output of the F / F 73.
And a switch circuit 74 that inputs a write address to one of them and a read address to the other and switches between them.

The multiplexing unit 8 selects one of the read data of the double buffer 1 and the output information of the additional information control unit 4 based on the output signal (multiplexed bit described later) of the read address setting unit 3, that is, time division multiplexing. And output.
The processor interface unit 9 includes a VME interface (I / F) 90 that can interface with an external processor via a VME bus of a general-purpose bus protocol, and realizes setting of each unit and reading and writing of SRAM.

Further, in addition to the above configuration, the unacquired data information control section 10 includes a gate circuit 101 for gate-outputting line start and end information from the data write end monitoring section 6.
A register 102 for latching time information based on an output signal of the gate circuit 101, a counter 103 for counting an input line start signal, and a gate circuit 101
, A register 104 for latching the output count value of the counter 103 by the output signal of the counter 103, the count value of the counter 103, the output time information of the register 102, and the register 104.
FIF that each output value is input and output
It consists of O105.

Next, the operation of the embodiment of the present invention having the above configuration will be described with reference to FIG.

First, an initial setting is made, and a setting mode is set by an I / O access of a VME bus from an external processor,
Read address setting unit 3 by ME bus memory access
In the SRAM 31, the addresses in the order of reading from the double-buffered SRAMs 11A and 11B are written for rearrangement for format conversion. The data at this time includes additional information, time information, information bits for multiplexing a counter value for counting the line start signal, and data of a read end bit. Also, the number of frequency division stages of the variable frequency divider 52 of the clock generator 5 is set by I / O access to the VME bus. The clock frequency at this time is selected to be higher than the write rate clock. This usually results in a double buffer 1
In this case, reading can be completed earlier than writing. Further, the count value for one format of data to be processed (the number of data to be written to the double buffer) is set in the comparator 61 of the data write end monitoring unit 6.

The formatter receives image data for one line, a clock, a line start signal indicating the start of one line of data, a data enable signal indicating an image data area, additional information, and time information at the timing shown in FIG. Is done.

After the initial setting, the formatter releases the setting mode by the I / O access of the VME bus from the external processor, and when the above various data is input, the operation of the formatter is started.

To write the data in the double buffer, the counter 20 of the write address generator 2 is reset by the line start signal, and the SRAM 1 of the double buffer 1 is written.
The address of the write-side SRAM among 1A and 11B is set to “0”. When the data enable signal is at a high level, the counter 20 continues to count up, updates the write address of the SRAM on the write side of the double buffer, and writes the input image data to the SRAM on the write side. The additional information and the time information are latched at the line start and stored in the register 41.

Data is read from the double buffer when the output signal of the AND circuit 62 for performing a logical product operation of the line start signal and the write data end information is at a high level.
SRA storing double buffer read address
The counter 32 that generates the address of M31 is reset, and the counter 32 starts counting up. The counter 32 stops when the high-level data of the read end bit of the SRAM 31 storing the read address is read. Until then, the counter 32 continues to count the clock input from the variable frequency divider 52.

One bit of the data written in the SRAM 31 storing the read address of the double buffer is allocated as a bit for reading out the multiplexed data. When this bit is at a high level, additional information as the multiplexed data and The output data of the register 41 latching the time information is selected by the changeover switch 81. When the output data is at the low level, the SRAMs 11A and 11B of the double buffer 1 are selected.
Out of the read-side SRAMs, and outputs the selected data as output data.

The counter value to be written to the double buffer and the count value from the counter 20 which is incremented as an address after the writing to the double buffer is started are compared by the comparator 61. When the values match, one bit is added. End information (write end bit)
And stored at a high level. When this state is reached, it is determined that the writing is completed. This data write end information maintains the high level state until the next line start is input.

Next, the switching control of the double buffer is as follows.
The flip-flop 73 is toggled by the output signal of the AND circuit 72 which performs the logical product operation of the data write end information and the line start, and the SRAM 1 of the double buffer 1 is operated.
The chip select and the write enable of 1A and 11B are generated, and the double buffer 1 is switched. That is, when the data write end information is at the high level and the line start signal is at the high level, the double buffer is switched. With the above operation, data conversion is performed in real time.

Next, when data having the timing shown in FIG. 4 is input to the formatter, if a predetermined number of data cannot be written for some reason, the formatter informs the formatter before the data write end information becomes high level. , A high-level line start signal is input.

In the case of the conventional formatter, the double buffer is switched by inputting the line start signal at a high level. Therefore, as shown in FIG. Is switched, and the data 2 is read only halfway. Since data 4 and subsequent data have the correct length, data 3 and subsequent data are output with the correct length, but the output of data 2 is short, and the beginning of subsequent data is shifted. In addition, data 3 which is unnecessary illegal data is read out (wavy line portion) and output more than it is written.

On the other hand, in this embodiment, the double buffer is switched when the data write end information is at the high level and the next line start signal is at the high level. Nothing like that happens.

The operation at the timing shown in FIG. 4 will be described with reference to FIG. Data 1 is S
When writing to the RAM 11A, the SRAM 11B
The data written in the SRAM 11B is read before the writing of the data 1 is completed. Next, when a line start signal of data 2 is input, after the double buffer is switched, data 2 is written into the SRAM 11B as schematically shown in FIG.
Data 1 is read from the RAM 11A.

After the normal writing of the data 2 to the SRAM 11B is completed, the double buffer is switched again so that the SRAM 11A is on the writing side and the SRAM 11B is on the reading side, and the next data 3 is stored in the SRAM 1B.
1A, and normal data 2 starts to be read from the SRAM 11B. However, since the data 3 is invalid data, during the above operation, as shown by a in FIG. A line start signal is input.

In this case, in this embodiment, since the reading of the data 2 has not been completed, the data write end information remains at the low level. Therefore, even if the line start signal (a in FIG. 4) of the data 4 is input, the output signal of the AND circuit 72 that controls the switching of the double buffer 1 does not become high level and the switching of the double buffer 1 is not performed. At this time, the counter 32 that generates the address of the SRAM 31 storing the read address of the double buffer 1 keeps counting up the clock pulse from the variable frequency divider 52. Reading is continued.

Further, the counter 20 which generates the double buffer write address is reset by the line start signal of data 4 (FIG. 4A), that is, the write address becomes "0", while the SRAM 11A is in the read side. 5A, and is still on the writing side. As schematically shown in FIG. 5A, the SRAM 11A that has written the data 3 which is incorrect data overwrites the next data 4 with the data 3. Will be. Since the data 3 at this time is illegitimate data and is not processed, there is no problem even if it is overwritten.

Then, the SRAM which has continued reading is
The reading of data 2 from 11B is completed, and the SRA
When the writing of data 4 to M11A ends normally,
Since the data write end information becomes high level and the line start signal of the next data 5 is input, the SRAM 11A is switched to the read side and the SRAM 11B is switched to the write side, and the data 4 is read from the SRAM 11A. Data 5 is written to the SRAM 11B.

As a result, as schematically shown in FIG. 5B, the length of the output data is constant, no illegal data is output, and the processing of the apparatus (system) at the subsequent stage of the formatter is performed. You don't lose the data you need.

Further, as an additional function, it is possible to have a function of extracting the position information overwritten by the unacquired data information control unit 10 to the outside. When the high-level line start signal is input and the data write end information is at the low level, the unacquired data information control unit 10 latches the time information or the count value obtained by counting the line start signal into the registers 102 and 104. , Each output of the registers 102 and 104 and the counter 103
Input to the FIFO 105 and write independently of each other,
The signals read from the FO 105 independently of each other
One of the signals is selected by the E bus I / F 90 so that the information can be taken out to the control processor.

In the apparatus (system) at the subsequent stage of the formatter, the time information multiplexed on the output data of the formatter, the count value of the signal indicating the head of the data to be converted, and the information from the unacquired data information control unit are output. To insert dummy data.

[0061]

As described above, according to the present invention,
By switching the double buffer when the data write end information is output and the next line start signal is input, it is possible to prevent the reading from being terminated halfway or storing unnecessary data in the double buffer. Therefore, the length of output data can be made constant, illegal data is not output, and data necessary for processing of a device (system) at a subsequent stage of the formatter can be prevented. Further, according to the present invention, when the read speed is high, even if data of a predetermined size cannot be written, data of a predetermined size is read, thereby preventing generation of a line that should not exist. it can.

Further, according to the present invention, the function of extracting the overwritten position information of the buffer in which writing has been completed halfway is also provided, so that the apparatus (system) downstream of the formatter is convenient for processing. In addition, even if it is necessary to insert dummy data at a position of data that is too short to be read, which is illegal data and cannot be processed, the position can be easily known, and therefore, dummy data insertion processing can be performed. Can be easily performed, which is useful for improving data quality.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of one embodiment of the present invention.

FIG. 3 is a timing chart of data input to a formatter.

FIG. 4 is a timing chart for explaining the operation of FIG. 2;

FIG. 5 is an operation explanatory diagram of FIG. 2;

FIG. 6 is a diagram illustrating an operation of an example of the related art.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Double buffer 1A, 1B buffer 2 Write address generation part 3 Read address setting part 4 Additional information control part 5 Clock generation part 6 Data write end monitoring part 7 Double buffer switching control part 8 Multiplexing part 9 Processor interface part 10 Unacquired data information Control unit 11A, 11B Static / random buffer
Access memory (SRAM) 20, 32, 103 Counter 31 Static random access memory (SRAM) 41, 102, 104 Register 51 Oscillator 52 Variable frequency divider 61 Comparator

Claims (4)

[Claims] 1. A double buffer having first and second buffers for writing input data to one buffer and reading stored data from the other buffer for performing data format conversion, and writing the double buffer. A write address generator for generating a write address for writing the input data in a buffer on the side in synchronization with an external input data head signal indicating the start of a predetermined unit of the input data; and a format conversion and addition of the input data Read control means for supplying an externally set read address to a read buffer of the double buffer for information multiplexing and reading data from the read buffer at a rate higher than a write rate; and Additional information control unit that captures the additional information at the time of input A data write end monitoring unit that monitors the end of writing of the input data to the write buffer of the double buffer; and the data head signal and end information output from the data write end monitoring unit. The buffer on the write side of the double buffer to the read side,
And a double buffer switching control unit that switches a buffer on the read side to a write side, and a multiplexing unit that multiplexes and outputs the additional information from the additional information control unit and output data of the double buffer. Formatter to do. 2. The non-acquired data information for generating and outputting unacquired data information indicating the position when the data head signal is input before the end information is input to the double buffer switching control unit. The formatter according to claim 1, further comprising a control unit. 3. The formatter according to claim 2, wherein the unacquired data information is a count value of the data head signal or time information of the input data. 4. One of the first and second buffers writes input data, and the other buffer reads stored data at a higher rate than the write rate.
In addition, a read address of a double buffer in which a write side and a read side are alternately switched is set from the outside, and a write address is generated in synchronization with a data head signal indicating a start of data of a predetermined unit of the input data. A formatter control method for multiplexing and reading additional information and the time information together with data read by converting input data from a buffer, comprising: writing the input data to a write-side buffer of the double buffer. When both the end information output by the end and the data head signal are input, the buffer on the write side of the double buffer is switched to the read side, and the buffer on the read side is switched to the write side, and the end information is When the data head signal is input before input A method for controlling a formatter, wherein a position at that time is acquired and output as unacquired data information to the outside.