JPH07129756A - Buffer memory device - Google Patents

Abstract

PURPOSE:To reduce the number of necessary line buffers to reduce the circuit scale. CONSTITUTION:Buffers 14 and 17 which have a high impedance at the time of read operation are provided-between the data line of a memory device and input data lines of line buffers 12a and 12b and between output data lines of line buffers 12a and 12b and the data line of a memory 13, respectively, and buffers 15 and 16 which have a high impedance at the time of write operation are provided between output data lines of line buffers 12a and 12b and the data line of an output device and between the data line of the memory 13 and input data lines of line buffers 12a and 12b, respectively, and connection/ disconnection control is possible, and a pair of line buffers 12a and 12b can be used for input as well as output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer memory device used as an image memory in image-related equipment such as printers and copying machines.

[0002]

2. Description of the Related Art A configuration example of a conventional buffer memory board will be described with reference to FIG. This buffer memory device 1 is
It is arranged between the memory device 2 and an output device 3 such as a printer, and is composed of a memory 4, a line buffer section 5, and a control circuit 6. Here, the memory 4 is a memory having a common input / output data line, for example, DRA.
It is composed of M, and its input stage is FIFO
Line buffers 5a and 5b of (first in / first out) are connected, and line buffers 5c and 5d of FIFO are connected to the output stage. Also,
The control circuit 6 controls each memory (DR
It is configured to control the read / write operation to (AM, FIFO).

The operation of such a structure will be described. First, when the buffer memory device 1 is in the write mode, the input image data output from the memory device 2 is
After being written in the line buffers 5a and 5b of the input stage, they are written in the memory 4 (DRAM). When the buffer memory device 1 is in the read mode, the image data read from the memory 4 is written to the line buffers 5c and 5d at the output stage and then output to the output device 3.

Here, read / write of the buffer memory device 1
The write mode is selected by an external signal,
The read / write operation is performed based on the control signal of the printer interface as shown in FIG. That is, the pixel clock W. CLK, line synchronization signal L. Syn
c, the data line valid section signal L. Gate, the read start signal F. Gate is a control signal of the printer interface output from the output device 3. Then, the write operation start signal WF. Gate is generated pseudo in the buffer memory device 1.

The memory device 2 uses the write operation start signal WF. The image data is output to the buffer memory device 1 by Gate according to the control signal.

Specifically, the control circuit 6
One line buffer 5a in the input stage writes the image data at the timing when the odd line image data is input, and reads the image data in the line buffer 5a to the memory 4 at the timing when the even line image data is input. At the same time, the other line buffer 5b of the input stage writes the image data at the timing when the image data of the even line is input, and the image data in the line buffer 5b is written at the timing when the image data of the odd line is input. The memory 4 is controlled to read. The image data is read from the memory 4 in the same manner as the writing, the read mode is selected, and the read start signal F. When Gate is input, the image data of the odd line is written in the one line buffer 5c, and the image data of the even line is written in the other line buffer 5d. Then, the lines are alternately output from the line buffers 5c and 5d to the output device 3.

[0007]

In the case of the conventional buffer memory device 1, its address is the sync signal L. Since it is regulated by Sync, an unused portion of the memory occurs, which is wasteful.

When image data for one screen is written in the memory device 2 and data transfer between the memory device 2 and the output device 3 is controlled at different timings, the line buffer 5a is provided in each input / output stage. , 5b, line buffer 5c,
5d is required, and the circuit scale is large.

Incidentally, it has been proposed to use the internal clock of the buffer memory device to control the data transfer with the input / output device at different timings. However, there is a concern that the operation may become unstable depending on the pixel clock frequency of the output device.

[0010]

According to a first aspect of the present invention, a line buffer, a memory, and a control unit are provided and arranged between a memory device and an output device to control data and transfer of this data. In a buffer memory device in which a read / write operation is selected by an external signal using only a control signal as an interface, a data line between the data line of the memory device and an input data line of the line buffer, and an output data line of the line buffer. A buffer having a high impedance during a read operation is provided between each of the data lines of the memory and between the output data line of the line buffer and the data line of the output device, and between the data line of the memory and the data line of the memory. A buffer that becomes high impedance during a write operation between the line buffer and the input data line. Provided.

According to a second aspect of the present invention, a line buffer, a memory and a control unit are provided, and the line buffer, the memory and the control unit are provided between the memory device and the output device, and only the data and the control signal for controlling the transfer of the data are interfaced. As a buffer memory device whose read / write operation is selected by an external signal, at least four line buffers are provided in each of the input / output stages to form a parallel / serial conversion circuit together with the memory and to oscillate. And a pseudo signal generation circuit for generating a pseudo control signal based on the oscillation source.

According to a third aspect of the present invention, in addition to the second aspect of the invention, a cutoff circuit for cutting off various control signals input from the output device during a write operation is provided.

According to another aspect of the present invention, a line buffer, a memory, and a control unit are provided, and the line buffer, the memory, and the control unit are provided between the memory device and the output device. Only the data and the control signal for controlling the transfer of the data are interfaced. In a buffer memory device whose read / write operation is selected by an external signal as an address counter, an address counter for counting the number of data read or written in the memory, and a first and a second for counting the number of synchronization signals in the control signal. The output value of the line counter and the output value of the address counter is written by the synchronizing signal at the time of a write operation using the outputs of the first and second line counters as an input address, and the written count value of the address counter is output at the time of reading. Address pointer and the end address of the line to be latched A latch circuit, and a comparator for comparing the termination address value of the address value and the line in the lead, is provided an address decoder to stop the read operation of the memory by the comparator output.

According to a fifth aspect of the present invention, a line buffer, a memory, and a control unit are provided, and the line buffer, the memory, and the control unit are provided between the memory device and the output device. Only the data and the control signal for controlling the transfer of the data are interfaced. In a buffer memory device whose read / write operation is selected by an external signal as an address counter, an address counter for counting the number of data read or written in the memory, and a first and a second for counting the number of synchronization signals in the control signal. The output value of the line counter and the output value of the address counter is written by the synchronizing signal at the time of a write operation using the outputs of the first and second line counters as an input address, and the written count value of the address counter is output at the time of reading. Register the first address pointer and the end address of the line. An address decoder having a latch circuit for performing a read operation, a comparator for comparing the address value being read with the end address value of the line, and a second address pointer for resetting the line start address value in the address counter by the output of the comparator. Provided.

According to a sixth aspect of the present invention, with respect to the fourth or fifth aspect of the invention, the address pointer in the address decoder is a data memory in which the number of data written in one line is stored in advance as data. The address counter is an address counter that loads the final data number of the previous line with a sync signal at the time of reading and counts and outputs the data number in the line effective image section.
A comparator that compares the output of the address counter with the output of the data memory is used, and the line counter is a line counter that counts only the synchronization signal at the time of reading.

According to a seventh aspect of the present invention, with respect to the sixth aspect of the invention, the data memory in the address decoder has a plurality of data memories in which the number of data required for one line depending on the pixel density of the output device is stored in advance. Then, a selection circuit for selecting the corresponding data memory according to the pixel density signal is provided.

In the invention described in claim 8, claim 2 or 3
In addition to the invention described above, a determination means for determining the frequency of the pixel clock of the output device preset by the pixel density signal in the control signal transmitted and received to and from the output device, Stop means for stopping the generation of the control signal inside by stopping the oscillation source based on the judgment result of the judging means, a control signal generated inside based on the judgment result of the judging means, and a control output from the output device A selection means for selecting one of the signals is provided, and the write operation is performed using the control signal selected by the selection means.

In a ninth aspect of the present invention, a line buffer, a memory, and a control unit are provided, and the line buffer, the memory, and the control unit are provided between the memory device and the output device, and only the data and the control signal for controlling the transfer of the data are interfaced. In a buffer memory device whose read / write operation is selected as an external signal, a pixel density signal is included in a control signal exchanged with the output device, and an output device preset by the pixel density signal Determining means for determining the frequency of the pixel clock, and a frequency divider having a frequency division ratio set in advance by the pixel density signal, and the determining means for determining the pixel clock output from the output device by the frequency divider. According to the determination result of (1), the frequency is divided to generate various control signals so that the write operation is performed.

In a tenth aspect of the present invention, a line buffer, a memory, and a control unit are provided, and the line buffer, the memory, and the control unit are provided between the memory device and the output device. Only the data and the control signal for controlling the transfer of the data are interfaced. As a buffer memory device in which a read / write operation is selected by an external signal, a plurality of line buffers, each of which is at least four in number, are provided in an input / output stage to form a parallel / serial conversion circuit with the memory, and read A toggle circuit that operates at the time of operation and performs a toggle operation by the edge signal on the line leading end side of the line effective image width signal in the control signal output from the output device, and the output of this toggle circuit is the synchronization signal in the control signal. It is called a latch circuit that latches with and outputs two latch signals of positive and negative phases. The lead period extension circuit is provided which is,
The read operation is performed using the signal output from the read period extension circuit.

According to the invention of claim 11, claim 4,
The invention described in claim 1 is combined with the invention described in 5, 6, or 7.

[0021] According to the invention of claim 12,
The invention described in claim 2 is combined with the invention described in 5, 6, or 7.

In the thirteenth aspect of the invention, the invention of the twelfth aspect is configured by combining the invention of the third aspect.

In the fourteenth aspect of the present invention, the fourth and fourth aspects are provided.
With respect to the invention described in 5, 6, or 7, the invention described in claim 2 and the invention described in claim 8 are combined.

According to the fifteenth aspect of the present invention, the fourth and fourth aspects are provided.
The invention described in claim 9 is combined with the invention described in claim 5, 6 or 7.

According to the invention of claim 16,
With respect to the invention described in claim 5, 6 or 7, at least four line buffers are provided in each of the input and output stages to form a parallel / serial conversion circuit with a memory, and the invention according to claim 10 is combined. did.

According to the invention of claim 17, claim 4
With respect to the invention described in 5, 6, or 7, the invention described in claim 2 and the invention described in claim 10 are combined.

In the eighteenth aspect of the invention, the invention of the seventeenth aspect is formed by combining the invention of the third aspect.

In a nineteenth aspect of the present invention, a line buffer, a memory, and a control unit are provided, and the line buffer, the memory, and the control unit are provided between the memory device and the output device, and only the data and the control signal for controlling the transfer of the data are interfaced. 9. A buffer memory device in which a read / write operation is selected by an external signal as described above, wherein a plurality of line buffers are provided in each of the input / output stages to form a parallel / serial conversion circuit with the memory. The invention described in claim 10 and the invention described in claim 10 are combined.

According to the twentieth aspect of the invention, the fourth and fourth aspects are provided.
The invention described in claim 19 is combined with the invention described in claim 5, 6 or 7.

In a twenty-first aspect of the present invention, a line buffer, a memory, and a control unit are provided, and the line buffer, the memory, and the control unit are provided between the memory device and the output device. 10. A buffer memory device in which a read / write operation is selected by an external signal as described above, wherein a plurality of line buffers are provided at each of the input / output stages to form a parallel / serial conversion circuit with the memory. The invention described in claim 10 and the invention described in claim 10 are combined.

According to the invention of claim 22, claim 4
The invention described in claim 21 is combined with the invention described in claim 5, 6 or 7.

[0032]

According to the first aspect of the present invention, a buffer having a high impedance at the time of reading or writing is provided on each data line, so that the buffer is provided between the memory and the line buffer or the line depending on the operation mode (read / write mode). Connection between buffer and memory device and output device
Control of disconnection is possible, and two (pair) line buffers can be used for both input and output.
The number of line buffers can be reduced and the circuit scale can be reduced as compared with the conventional case.

According to the second aspect of the present invention, the control signal is generated based on the internal oscillation source at a speed at which the memory can operate, while at least four line buffers are provided to form the parallel / serial conversion circuit. Therefore, the data bit width can be expanded inside the buffer memory device more than the outside, and the buffer memory device can respond to a high-speed clock (pixel clock W.CLK) from the output device.

According to the third aspect of the present invention, since the external input signal from the output device side which is not required during the write operation of the buffer memory device is cut off by the cutoff circuit, the data writing to the memory can be stably performed. You can

According to the fourth aspect of the invention, an address decoder for storing and holding the start address of each line of the write data is provided, and the address held at the time of writing is compared with the address actually read, and this comparison is made. As a result, since a stop function for stopping the read operation of the memory is provided, the unused area of the buffer memory device is eliminated, and the data for each line can be read correctly.

According to a fifth aspect of the present invention, an address decoder for storing and holding the start address of each line of the write data is provided, and the start data address of each line is set in the address counter in the address decoder.
Address pointer is provided to compare the address held at the time of writing with the address actually read, and the second address pointer resets the head data address of each line to the address counter according to the comparison result. , I tried to read the data of that line again,
The unused area of the buffer memory device can be eliminated and the data for each line can be read correctly.

According to the sixth aspect of the invention, since the data memory for storing the leading address of each line of the write data in advance is provided, the structure of the address decoder can be simplified.

According to the seventh aspect of the invention, it is possible to easily configure an address decoder that can handle a plurality of write densities.

According to another aspect of the present invention, there is provided a buffer memory comprising a pixel clock determining means of the output device, a stopping means for stopping the internal pseudo signal generating circuit, and a selecting means for selecting an external or internal control signal. Since the generation or input of the control signal unnecessary for the read / write operation of the device is interrupted, the read / write operation of the buffer memory device can be stably performed.

In the ninth aspect of the invention, a frequency divider having a frequency division ratio set in advance in accordance with the pixel density signal of the output device is provided, and the pixel clock output from the output device is divided by this frequency divider. Since various control signals are generated by the rotation, an internal control signal generation circuit using an internal oscillation source is not required, and a stable buffer memory device can be easily configured.

According to the tenth aspect of the invention, when the data read cycle of the output device is faster than the data read cycle of the memory in the buffer memory device, a read period extension circuit is provided to set the data read period of the output device. Since the maximum is set within one line scanning period, the buffer memory device can read the effective image data as much as possible.

In the eleventh to twenty-second aspects of the present invention, the action corresponding to each combination can be obtained.

[0043]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the invention described in claim 1 will be described with reference to FIG. The buffer memory device 11 of the present embodiment is also arranged between the memory device and the output device similarly to that shown in FIG. 19, and basically, two line buffers 12a and 12b, The memory 13 and a control unit (not shown) are provided, and the read / write operation is selected by an external signal using only data and a control signal for controlling the transfer of this data as an interface.

Here, the line buffers 12a, 12
An input data line and an output data line are connected to b. Further, the data line of the memory device and the line buffer 1
A 3-state buffer (buffer) 14 is connected between the input data lines of 2a and 12b and a 3-state buffer (buffer) 15 between the data line of the output device and the output data lines of the line buffers 12a and 12b. Are connected. In addition, the data line of the memory 13 and the line buffer 1
A 3-state buffer (buffer) 16 is connected between the input data lines of 2a and 12b and a 3-state buffer (buffer) 17 between the data line of the memory 13 and the output data lines of the line buffers 12a and 12b. Are connected. These four 3-state buffers 14-17
Is controlled by a signal for selecting the operation mode of the buffer memory device 11. In the write mode, the three-state buffers 15 and 16 have high impedance,
In the read mode, the 3-state buffers 14 and 17 are set to have high impedance.

In such a configuration, first, when the buffer memory device 11 is in the write mode, the input image data output from the memory device is written / read to / from the line buffers 12a and 12b alternately for one line, and three states are set. It is written in the memory 13 via the data bus having the buffer 17. Here, since the 3-state buffer 16 is in the high impedance state, the input image data output from the memory device is not directly written in the memory 13.

On the other hand, when the buffer memory device 11 is in the read mode, the image data read from the memory 13 is 3
The data is written in the line buffers 12a and 12b via the data bus having the state buffer 16 as in the write mode. Then, these line buffers 12a,
The image data read alternately from 1b from 12b is 3
It is output to the output device via the state buffer 15.

As described above, according to the present embodiment, the three-state buffers 14 to 17 are provided on each data line, and depending on the operation mode (read / write mode), between the memory 13 and the line buffers 12a and 12b, or between the lines. Since it is possible to control connection / disconnection between the buffers 12a and 12b and the memory device and the output device, two (pair) line buffers 12a and 12b can be used for both input and output. Therefore, the number of line buffers can be reduced and the circuit scale can be reduced as compared with the conventional case.

Next, an embodiment of the invention described in claim 2 will be described with reference to FIGS. The buffer memory device 18 of this embodiment is basically arranged between the memory device and the output device similarly to that shown in FIG. 19, and includes four line buffers 19a to 19d and a memory. Two
0 and a control circuit (control unit) 21 are configured so that a read / write operation is selected by an external signal using only data and a control signal for controlling the transfer of this data as an interface (printer interface). There is.

Here, the memory 20 has a common input / output line, here, it is constructed based on a DRAM, and as shown in FIG. 3, two DRAMs 22a and 22b for odd and even are provided.
And one DRAM module 23 is formed. In the illustrated example, the DRAM module 23 is composed of eight groups a to h. In FIG. 3, / RA
S is a row address strobe signal, / CAS is a column address strobe signal, and / WE is a write enable signal. In addition, "/" in each signal indicates that it is an inverted signal (the same applies in the following description).

The line buffers 19a to 19d are
Each of them is configured as, for example, a module in which eight line buffer units (indicated by FIFO1 to 8) having an 8-bit FIFO structure are collected.
9b is connected to the input stage of the memory 20, and the line buffers 19c and 19d are connected to the output stage of the memory 20.

Further, in the present embodiment, the oscillation source 24 and the control circuit 2 for generating a pseudo control signal as a printer interface signal based on the oscillation source 24.
1 to the pseudo signal generating circuit 25, and the memory 20
And an address counter 26 that counts the addresses of. Therefore, each memory of input image data (DRA
A control signal output from the output device and a pseudo printer interface signal by the pseudo signal generation circuit 25 are input to the control circuit 21 for controlling reading / writing from / to the M, FIFO) 19a to 19d, 20. Has been done.

In such a configuration, first, input data of 8 bits (Data0) of one pixel input from the memory device.
~ 7) are line buffers 19 which are modules of the input stage.
It is taken in by a and 19b, expanded into image data 64 bits (Data 0 to 63) for 8 pixels, and written in the memory 20.

On the other hand, 64 bits of image data of 8 pixels read out from the memory 20 are written in the line buffers 19c and 19d which are modules of the output stage, and then the eight FIFOs of the line buffers 19c and 19d are sequentially operated. By reading out, the parallel / serial converted image data 8
It is output to the output device as bits (W.Data0 to 7). That is, the line buffers 19a to 19d and the memory 20
A parallel / serial conversion circuit 27 is formed by and.

The operation of this embodiment will now be described in more detail with reference to the timing charts shown in FIGS. 4 to 6 show timing charts at the time of writing, and FIGS. 7 to 9 show timing charts at the time of reading. In these figures, WL. Sync is a line synchronization signal, WL. Gate is a data line write section signal, WF. Gate indicates a data write start signal, both of which are control signals for the pseudo printer interface generated and output by the pseudo signal generation circuit 25.
In addition, / REF. P is a signal for refreshing the DRAM of the memory 20. Then, FIGS.
1 is based on the signal generated based on the internal oscillation source 24, and FIGS. 7 and 8 are based on the signal generated based on the internal oscillation source 24 according to the external signal.
1 is the pixel clock W. This is due to the signal generated from CLK.

First, the memory device stores the image data in the buffer memory device 1 according to the pseudo printer interface signal.
Output to 8. At this time, by the control circuit 21,
The line buffer 19a (module 1) writes the image data of odd-numbered lines (indicated by / FIFO1WE in FIG. 4) at the timing of inputting the image data of the odd-numbered lines, and as described above at the timing of inputting the image data of the even-numbered lines. The captured image data is read out to the memory 20 (F in FIG. 4).
IFO1RE), and in parallel with this, the line buffer 19b (module 2) writes the image data at the timing when the image data of even lines is input (see FIG. 4).
The image data captured as described above is read out to the memory 20 at the timing when the image data of the odd line is input (indicated by / FIFO2WE in FIG. 4) (FIFO2RE in FIG. 4).
(Shown in) is controlled.

The output line of the FIFO 1 in the line buffer 19a (module 1) is the line buffer 19b.
It is connected to the output line of FIFO1 in (module 2),
It is connected to the DRAM module a in the memory 20. Hereinafter, the line buffers 19a and 19b (module 1,
2) The output lines of the FIFO2 in are connected to each other by the memory 2
FRAM in line buffers 19a, 19b (modules 1, 2) connected to the DRAM module b in 0.
A DRAM in the memory 20 in which the output lines of O8 are connected to each other
It is connected to the module h.

As shown in FIG. 3, each of the DRAM modules a to h is composed of an odd-numbered DRAM 22a and an even-numbered DRAM 22b, and the 8-bit data input / output lines (DQ0 to 7) are connected to each other. Are connected to each other.
In addition, the line buffers 19a and 19b (module 1,
Each FIFO in 2) is sequentially written into each FIFO for every 8 input pixels (indicated by / WE1 to 8 in FIG. 5), and eight FIFOs simultaneously read (FIFO1R in FIG. 6).
6), and / RAS, / shown in FIG.
Data is written in the DRAM by the CAS and / WE signals.

That is, the image data of the first pixel of the odd line is the FIFO of the line buffer 19a (module 1).
The image data written from 1 to the odd-numbered DRAM 22a of the DRAM module a in the memory 20 and the image data of the eighth pixel of the even line is F of the line buffer 19b (module 2).
The data is written from the IFO 8 to the even-numbered DRAM 22b of the DRAM module h in the memory 20. Image data is read from these DRAMs in the same manner as at the time of writing. Image data of odd lines is written from the odd DRAM 22a to the line buffer 19c (module 3), and even line image data is read from the even DRAM 22b. It is written in the line buffer 19d (module 4) (see FIGS. 7 and 8).

Then, the line buffers 19c and 19d
(Modules 3 and 4) are sequentially read one by one in synchronization with the read clock (indicated by / RE1 to 8 in FIG. 9),
The image data expanded to 64 bits is parallel / serial converted to 8-bit data (W.Data0 to 7) and output as image data to an output device such as a printer. FIG. 9 shows the read operation of the FIFO of the line buffer 19c (module 3). In this case, the line buffer 19d (module 4) is the F buffer shown in FIG.
It does not operate like IFO2.

Here, the write mode and read mode of the buffer memory device 18 are distinguished by an external signal, and when the write mode is selected, the buffer memory device 18 is selected.
Internal oscillation source 24 (system clock Sys.CLK)
The pseudo printer interface signal generated based on the above is output to the memory device, and at the same time, various control signals are generated using the signal to perform a stable write operation.
During the read operation, the memory 2 is read based on the control (printer interface) signal input from the output device.
0 uses the internal oscillation source 24 and uses the line buffers 19a ...
After 19d, the pixel clock W. A read operation is performed using CLK.

As described above, according to this embodiment, the control signal is generated based on the internal oscillation source 24 at a speed at which the memory 20 can operate, while at least four line buffers 19a to 19d are provided. Since the parallel / serial conversion circuit 27 is formed in the buffer memory device 18,
The data bit width can be expanded wider than the outside inside, and can respond to the high-speed clock (pixel clock W.CLK) from the output device.

Next, an embodiment of the invention described in claim 3 will be described. This embodiment is configured by providing a cutoff circuit in the control signal section of the interface with the output device in the configuration of the above embodiment shown in FIG.
The cutoff circuit operates in the write mode of the buffer memory device 18 and cuts off the input of the printer interface signal output from the output device. In this case, since the write operation is controlled by using the pseudo signal from the built-in oscillation source 24 and the pseudo signal generation circuit 25, there is no problem even if the cutoff circuit cuts off various control signals. Such a cutoff circuit can be easily configured by an analog switch, a 3-state buffer, or the like.

According to this embodiment, the buffer memory device 1
Since the external input signal from the output device side which is not required during the write operation of 8 is cut off by the cutoff circuit, data writing to the memory 20 can be stably performed.

Further, an embodiment of the invention described in claim 4 will be described with reference to FIGS. 10 and 11. The present embodiment has a line buffer, a memory 28, and a control unit, and is arranged between a memory device and an output device, and uses only data and a control signal for controlling the transfer of this data as an interface for reading. / In the basic configuration of the buffer memory device in which the write operation is selected by an external signal,
An address decoder 31 as shown in FIG. 10 is provided. The same parts as those shown in the above embodiment are designated by the same reference numerals.

The address decoder 31 includes a first line counter 32 which counts a line synchronizing signal (/WL.Sync or /RL.Sync) and a line synchronizing signal / RL. A second line counter 33 for counting only Sync, an address counter 34 for setting an address of the memory 28, the first and second line counters 32,
Using the output value of 33 as an address, the address counter 3
The address pointer 35 that latches and outputs the value of 4 as data, and the second line counter 33.
The address pointer 3 when the output value of
5 is composed of a latch circuit 36 for latching the data (that is, the end address of the line), and a comparator 37 for comparing the output of the address counter 34 and the output of the latch circuit 36 during the read operation. .
The output of the comparator 37 is connected to the memory 28 so as to control the read operation thereof.

Here, the first line counter 32 starts counting at the start of the write / read operation of the buffer memory device and can output the count value only during the period of the line synchronization signal. The second line counter 33 has a line sync signal / R.
L. Delayed Sync / DL. The count value can be output only during the Sync period. Address counter 34
Is a line valid section signal L.
Gate period is counted and both write / write one frame
Counting is performed until the read operation is completed, and in the read mode, the output data of the address pointer 35 is set to the line synchronization signal / RL. It is loaded when a sync occurs, and is composed of, for example, a normal counter and a 3-state buffer. The address pointer 35 loads the data of the address counter 34 only during the synchronizing signal generation period during writing, and outputs the data loaded during the synchronizing signal generation period during reading. Also, D.I. CLK is memory 2
It is a clock synchronized with the data read / written to 8.

The operation of this embodiment having such a configuration will be described. First, when writing data,
The address counter 34 includes line buffers 17a and 17b.
(Modules 1 and 2) read clock D. CLK is a read start signal F. Until the end of Gate, the line valid section signal L. Counting is continued during the Gate period, and the count value is output to the memory 28, the latch circuit 36, the comparator 37 and the address pointer 35 as the write address data of the memory 28. Then, the line buffers 17a and 17b
The data read from (modules 1, 2) is written in the memory 28 whose address is the output of the address counter 34. The address pointer 35 is / WL. At the timing of Sync, the output of the first line counter 32 is used as an address input, and the output of the address counter 34 at that time is fetched as input data.

On the other hand, at the time of reading data, the address pointer 35 receives the line sync signal /RL.CLK according to the address value output from the first line counter 32. The data fetched at the time of writing is output at the timing of Sync. At the same time, the output is loaded (captured) by the address counter 34. Then, the line synchronization signal / RL. When Sync falls, the input / output data line of the address pointer 35 becomes high impedance, and the address counter 34 and the memory 2
8, only the latch circuit 36 and the comparator 37 are connected. Therefore, the line write section signal / RL.
The gate counter causes the address counter 34 to change from the loaded value to the write clock D.C. CLK is counted, and the count value output is output as the read address of the memory 28.

Here, the second value given the offset value 1
The line counter 33 of the line synchronizing signal / RL. Syn
delayed c / DL. The count value can be output only during the period of Sync, / DL. During the Sync period, the address pointer 35 outputs the data when the output of the second line counter 33 is used as the address. At the same time, the latch circuit 36 stores and holds the output of the address pointer 35. When the output of the latch circuit 36 and the output of the address counter 34 become the same, the comparator 37 outputs a signal to the memory 28 and stops the read operation. Further, the output signal of the comparator 37 is the line synchronization signal / RL. It is cleared by Sync and the read operation is performed again.

As described above, according to this embodiment, the address decoder 31 for storing and holding the start address of each line of the write data is provided, and the address held at the time of writing and the address actually read are compared. Since the comparison function has a stop function for stopping the read operation of the memory 28, the unused area of the buffer memory device is eliminated and the data for each line can be read correctly.

Next, an embodiment of the invention described in claim 5 will be described with reference to FIG. In this embodiment, a second address pointer 38 is added to the address decoder 31 in the above embodiment. The address pointer 35 becomes the first address pointer. In response to such addition of the second address pointer 38, the comparator 3
The output of 7 is input to the second address pointer 38 and the address counter 34 instead of the memory 28.

Here, the second address pointer 38
Operates only at the time of reading, and the head of the line D. The output data of the address counter 34 stored and held is output at the timing of CLK. Also,
The address counter 34 enters a data input accepting state by the output signal of the comparator 37, and outputs the output data of the second address pointer 38 to the D.D. Load by CLK. At this time, the memory address becomes the line head address.

When the address counter 34 loads the line head address, the signal output from the comparator 37 disappears and the output of the second address pointer 38 becomes high impedance. At the same time, the load state of the address counter 34 is released, and counting is started again. Here, the timing circuit 39 detects the line head D.D. of the second address pointer 38. Generate load timing with CLK.

As described above, according to this embodiment, the address decoder 31 for storing and holding the start address of each line of the write data is provided, and the start data address of each line is set in the address counter 34 in the address decoder 31. A second address pointer 38 is provided to compare the address held at the time of writing with the address actually read, and the second address pointer 38 addresses the start data address of each line according to the comparison result. By resetting to the counter 34 and reading the data of that line again, the unused area of the buffer memory device can be eliminated and the data of each line can be read correctly.

An embodiment of the invention described in claim 6 will be described with reference to FIG. In this embodiment, for example, the configuration of the address decoder 31 shown in FIG. 10 is modified to have the same function. That is, the address counter 34 is connected so that it operates only during reading and its output data is given to the memory 28 and the comparator 37. Also,
Data memories 40 and 41 instead of the address pointer 35
Is provided and is configured to store and hold the number of data for one line in advance. That is, the first data memory 40 outputs the data corresponding to the input address value during the synchronization signal, and the second data memory 41 always outputs the data to the comparator 37. The operation of the comparator 37 itself is shown in FIG.
This is the same as the case described in. Further, as the line counter, only one line counter 32 is provided, and the synchronization signal / RL. It is supposed to count only Sync.

In such a configuration, the sync signal / R
L. When the sync occurs, the first data memory 40 outputs the final data number of the previous line. This is because the line counter 32 is incremented at the rising edge of the sync signal. The address counter 32 loads the output of the first data memory 40 with the inverted synchronization signal,
/ RL. When Gate is generated, counting is started from this load value and output.

Therefore, according to this embodiment, since the data memories 40 and 41 for storing the start addresses of the respective lines of the write data in advance are provided, the structure of the address decoder 31 is simplified.

In the case of constituting the invention of claim 6 corresponding to the invention of claim 5, instead of the second address pointer 38 shown in FIG. A data memory stored and held may be used to read the value when the signal of the comparator 37 is output and load it to the address counter 34.

Further, an embodiment of the invention described in claim 7 will be described with reference to FIG. This embodiment is an extension of the embodiment shown in FIG. 13 to correspond to the pixel density of the output device. That is, in comparison with the above embodiment,
Second data memory 40a, 41a pair, first and second data memory 40b, 41b pair, first and second data memory 40
A plurality of pairs are provided according to the pixel density of the output device, such as c, 41c pairs ,. In this embodiment, a pixel density signal is prepared as an interface control signal for the output device and the buffer memory device, and any one of the first and second data memory pairs is selected by a selection circuit (not shown) by the pixel density signal. Is configured to be selected by.

Here, since the data lines of the first and second data memory pairs which are not selected based on the pixel density signal have high impedance, the operation is the same as in the case of FIG.

According to this embodiment as described above, the address decoder 31 capable of dealing with a plurality of writing densities can be easily constructed.

An embodiment of the invention described in claim 8 will be described with reference to FIG. In this embodiment, for example, a judging means 42, a stopping means 43 and a selecting means 44 are added to the configuration of the buffer memory device 18 according to the second aspect of the invention shown in FIG. 2, and an output device and a buffer memory device are added. The pixel density signal is prepared as a control signal for the interface.

First, the judging means 42 judges whether or not the frequency of the pixel clock output by the output device, which is set in advance by the pixel density signal, is a frequency at which the memory 20 in the buffer memory device 18 can be accessed. Is something
The determination result is output to the stopping means 43 and the selecting means 44.
When the determination means 42 outputs a determination result indicating that access is possible, the stopping means 43 stops the oscillation source 24 (for example, it can be realized by cutting off the power supply to the oscillation source 24 with an analog switch or the like). , Pseudo signal generation circuit 2
The signal generation of 5, that is, the generation of the control signal inside is stopped. Further, the selection means 44 is composed of, for example, a multiplexer, and causes the control circuit 21 to output the interface signal output from the output device to control the write operation.

On the other hand, when the determination means 42 outputs the determination result indicating that access is impossible, the stop means 43 does not function and the selection means 44 controls the pseudo interface signal output from the pseudo signal generation circuit 25. Circuit 2
1 to control the write operation.

As described above, according to this embodiment, the pixel clock determining means 42 of the output device, the stopping means 43 for stopping the internal pseudo signal generating circuit 25, and the selecting means 44 for selecting an external or internal control signal. Since the control signal unnecessary for the read / write operation of the buffer memory device 18 is cut off or input, the read / write operation of the buffer memory device 18 can be stably performed.

An embodiment of the invention according to claim 9 will be described with reference to FIG. In this embodiment, a frequency divider 45 is provided in place of the oscillation source 24, the pseudo signal generating circuit 25, the stopping means 43 and the selecting means 44 shown in the above embodiment.

First, the judging means 42 judges the frequency of the pixel clock output from the output device based on the pixel density signal and outputs it to the frequency divider 45. The frequency divider 45 defines a frequency division ratio for dividing the pixel clock into a clock (system clock in the buffer memory device 18) accessible by the memory 20 according to the pixel density. Based on the above, an appropriate control signal (pseudo printer interface signal) is generated and output to the control circuit 21. This control circuit 2
In No. 1, the signal required for the read / write operation of the memory 20 is generated based on the signal output from the frequency divider 45.

As described above, according to the present embodiment, the frequency divider 45 having the frequency division ratio set in advance according to the pixel density signal of the output device is provided, and the pixel clock output from the output device is divided by this frequency divider. Since the frequency divider 45 divides the frequency to generate various control signals, a stable buffer does not need the internal control signal generation circuit using the internal oscillation source 24, that is, the pseudo signal generation circuit 25 as in the above embodiment. Memory device 18
Can be easily configured.

FIG. 17 shows an embodiment of the invention described in claim 10.
And FIG. 18 will be described. This embodiment is shown in FIG.
A read period extension circuit as shown in FIG. 17 is added to the configuration shown in FIG. 17 in which at least four even-numbered line buffers 19a to 19d are provided and the parallel / serial conversion circuit 27 is formed by the memory 20. 46 is provided and configured. This read period extension circuit 46
Is a line effective image width signal / L. Gate
The toggle circuit 47 that performs a toggle operation with the edge signal on the line leading end side of the line, and the output of the toggle circuit 47 is the line synchronization signal / L. It is composed of a latch circuit 48 that latches at Sync and outputs two latch signals of positive and negative phases.

In such a configuration, the line effective width signal / L. Gate is input to the toggle circuit 47 as a clock, and the toggle circuit 47 is input to the latch circuit 48.
Of the data, line sync signal / L. Input Sync as a clock.

Here, when the buffer memory device 18 shifts to the read operation, the reset of the toggle circuit 47 and the latch circuit 48 is released, and as shown in FIG. 18, the toggle circuit 47 causes the line effective width signal / L. A toggle signal (Toggle Out) synchronized with the falling edge of Gate is generated. In response to this, the latch circuit 48 sends the toggle signal to the line synchronization signal / L. It latches at the rising edge of Sync and generates a read signal (Read Gate). The generated read signal is output to the control unit 21 and used as the read period signal of the line buffers 19c and 19d (modules 3 and 4) at the output stage (that is, the FIFO 3W in FIG. 7).
E, the part indicated by the broken line in the FIFO4WE corresponds).

When the read operation is performed with a signal based on the internal pseudo signal generation circuit 25, such a read signal is used in synchronization with the system clock of the buffer memory device 18.

As described above, according to this embodiment, when the data read cycle of the output device is faster than the data read cycle of the memory 20 in the buffer memory device 18, the read period extension circuit 46 is provided to read the data. Since the period is maximized within the one-line scanning period of the output device, the buffer memory device 18 can read the effective image data as much as possible.

As other embodiments, for example, each embodiment corresponding to the invention of claim 4, 5, 6 or 7 illustrated in FIGS. 10 to 14 is based on the invention of claim 1. As shown in FIG. 1, the buffers 14 and 17 having a high impedance during the read operation and the buffers 15 and 16 having a high impedance during the write operation.
May be provided (corresponding to the invention of claim 11).

According to this, the number of line buffers can be reduced to reduce the circuit scale, an unused area of the buffer memory device can be eliminated, and data for each line can be read correctly. .

Regarding each embodiment corresponding to the invention described in claim 4, 5, 6 or 7 illustrated in FIGS. 10 to 14, according to the invention described in claim 2, as shown in FIG. The oscillation source 24, the pseudo signal generation circuit 25, the four line buffers 19a to 19d, and the parallel / serial conversion circuit 27 including the memory 20 may be provided (corresponding to the invention of claim 12). Further, according to the invention of claim 3, a cutoff circuit for cutting off various control signals output from the output device during the write operation may be provided (corresponding to the invention of claim 13). .

According to this, the high-speed clock from the output device can be supported, the unused area of the buffer memory device can be eliminated, and the data for each line can be read correctly. According to the circuit provided with the cutoff circuit, it is possible to stably write data to the memory 20 by cutting off an external input signal which is not required during the write operation.

Further, regarding each embodiment corresponding to the invention of claim 4, 5, 6 or 7 illustrated in FIGS. 10 to 14, according to the invention of claim 2, as shown in FIG. The oscillation source 24, the pseudo signal generation circuit 25, the four line buffers 19a to 19d, and the parallel / serial conversion circuit 27 including the memory 20 are provided.
According to the described invention, the determining means 42, the stopping means 43, and the selecting means 44 may be added, and the pixel density signal may be used as a control signal for the interface between the output device and the buffer memory device 18 (claims). 14 corresponds to the invention described in 14).

Alternatively, with respect to each embodiment corresponding to the invention of claim 4, 5, 6 or 7 illustrated in FIG. 10 to FIG. 14, according to the invention of claim 9, the judging means 42 and the frequency divider 45 may be added (claim 15).
Corresponds to the described invention).

Further, regarding each embodiment corresponding to the invention of claim 4, 5, 6 or 7 illustrated in FIGS. 10 to 14, as shown in FIG. 2, four line buffers 19 are provided.
The parallel / serial conversion circuit 27 including the a to 19d and the memory 20 may be provided, and the read period extension circuit 46 including the toggle circuit 47 and the latch circuit 48 may be added according to the invention of claim 10. (Corresponding to the invention of claim 16). In this case, claim 2
According to the described invention, the oscillation source 24 and the pseudo signal generation circuit 2
5 may be included (corresponding to the invention of claim 17). At the same time, according to the invention of claim 3, a cutoff circuit may be provided for cutting off the input of various control signals output from the output device during the write operation (corresponding to the invention of claim 18).

Further, as shown in FIG. 2, according to the invention of claim 8, based on a structure in which four line buffers 19a to 19d and a parallel / serial conversion circuit 27 including a memory 20 are provided. While the write operation is controlled as a configuration in which a judging unit 42, a stopping unit 43 and a selecting unit 44 are added, a configuration in which a read period extension circuit 46 by a toggle circuit 47 and a latch circuit 48 is added as in the invention of claim 10. Alternatively, the read operation may be controlled (corresponding to the invention of claim 19).

Alternatively, as in the second aspect of the present invention, a configuration is provided in which the oscillation source 24 and the pseudo signal generating circuit 25 are provided together with the parallel / serial conversion circuit 27 including the four line buffers 19a to 19d and the memory 20. The write operation is controlled as in the invention of claim 8 by adding the judging means 42, the stopping means 43 and the selecting means 44, while the read by the toggle circuit 47 and the latch circuit 48 as in the invention of claim 10. The read operation may be controlled by adding a period extension circuit 46 (corresponding to the invention of claim 20).

Further, as shown in FIG. 2, determination is made according to the invention of claim 9 on the basis of the configuration in which the parallel / serial conversion circuit 27 including the four line buffers 19a to 19d and the memory 20 is provided. The write operation is controlled by adding the means 42 and the frequency divider 45, while the read operation is performed by adding the read period extension circuit 46 by the toggle circuit 47 and the latch circuit 48 as in the invention of claim 10. It may be controlled (corresponding to the invention of claim 21).

Alternatively, as in the invention as set forth in claim 2, the parallel line-to-serial conversion circuit 27 by the four line buffers 19a to 19d and the memory 20 as well as the oscillation source 24 and the pseudo signal generation circuit 25 are provided. While the write operation is controlled as in the invention of claim 9 by adding the judging means 42 and the frequency divider 45, the read period extension circuit by the toggle circuit 47 and the latch circuit 48 as in the invention of claim 10. The read operation may be controlled as a configuration in which 46 is added (corresponding to the invention of claim 22).

[0105]

According to the first aspect of the present invention, the line buffer, the memory and the control unit are provided between the memory device and the output device and control the data and the transfer of the data. In a buffer memory device in which a read / write operation is selected by an external signal using only signals as an interface, between a data line of the memory device and an input data line of the line buffer, and
A buffer having a high impedance during a read operation is provided between each of the output data line of the line buffer and the data line of the memory, and between the output data line of the line buffer and the data line of the output device, and Since a buffer that has a high impedance during a write operation is provided between each of the data line of the memory and the input data line of the line buffer, depending on the operation mode of the read / write mode, between the memory and the line buffer, or It is possible to control connection / disconnection between the line buffer, the memory device and the output device, and it is possible to use two (a pair) line buffers for both input and output. The number can be reduced and the circuit scale can be reduced.

According to the second aspect of the present invention, at least four line buffers are provided in each of the input / output stages to form a parallel / serial conversion circuit with the memory, and the oscillation source and this oscillation source are provided. Since the pseudo signal generating circuit for generating the pseudo control signal based on the above is provided, the data bit width can be expanded wider than the outside inside the buffer memory device, and the high speed clock from the output device can be responded.

According to the invention described in claim 3, in addition to the invention described in claim 2, since a cutoff circuit for cutting off various control signals output from the output device at the time of a write operation is provided, the buffer is provided. An external input signal from the output device side, which is not required during the write operation of the memory device, can be cut off by the cutoff circuit, and data writing to the memory can be stably performed.

According to the fourth aspect of the invention, the address counter for counting the number of data read or written in the memory, the first and second line counters for counting the number of synchronization signals in the control signal, and these An address pointer that outputs the count value of the written address counter at the time of writing while writing the output value from the address counter by the synchronization signal at the time of a write operation using the outputs of the first and second line counters as an input address, and a line Since it has a latch circuit for latching the end address of and the comparator for comparing the address value being read with the end address value of the line, and the address decoder for stopping the read operation of the memory by the output of the comparator is provided. In addition to eliminating the unused area of the buffer memory device, It can properly read the data for each Inn.

According to the invention of claim 5, an address counter for counting the number of data read or written in the memory, a first and a second line counter for counting the number of synchronization signals in the control signal, and these A first address pointer that outputs the count value of the written address counter at the time of reading while writing the output value from the address counter by the synchronization signal at the time of a write operation using the outputs of the first and second line counters as an input address. When,
A latch circuit that latches the end address of the line, a comparator that compares the address value being read with the end address value of the line, and a second address pointer that resets the line start address value in the address counter by the output of this comparator. Since the address decoder having is provided, the unused area of the buffer memory device can be eliminated, and the data for each line can be read correctly.

According to a sixth aspect of the present invention, with respect to the fourth or fifth aspect of the present invention, a data memory in which the address pointer in the address decoder is previously stored and held as the number of data to be written in one line as data. age,
The address counter is an address counter that loads the final data number of the previous line with the synchronization signal at the time of reading and counts and outputs the data number in the line effective image section, and the comparator compares the address counter output with the data memory output. As a comparator, the line counter as a line counter that counts only the synchronization signal at the time of reading,
Since the start address of each line of write data can be stored in advance, the configuration of the address decoder can be simplified.

According to a seventh aspect of the present invention, in addition to the sixth aspect of the invention, a plurality of data memories in the address decoder are preliminarily stored and held with the number of data required for one line depending on the pixel density of the output device. Since the data memory is provided with the selection circuit that selects the corresponding data memory according to the pixel density signal, an address decoder that can handle a plurality of writing densities can be easily configured.

According to the eighth aspect of the present invention, in addition to the second or third aspect of the present invention, the control signal transmitted to and from the output device is provided with a pixel density signal, and the pixel density signal is used in advance. Judging means for judging the frequency of the pixel clock of the set output device, stopping means for stopping the generation of the control signal inside by stopping the oscillation source based on the judgment result of this judging means, and the judgment result of the judging means By providing a selecting means for selecting one of a control signal internally generated based on the control signal and a control signal output from the output device, and performing a write operation using the control signal selected by the selecting means. Since the generation or input of the control signal unnecessary for the read / write operation is cut off, the read / write operation of the buffer memory device It can be performed stably.

According to the ninth aspect of the present invention, the control signal transmitted to and from the output device has a pixel density signal and the frequency of the pixel clock of the output device preset by the pixel density signal. And a frequency divider having a frequency division ratio set in advance by the pixel density signal, and the frequency divider divides the pixel clock output by the output device according to the determination result of the determination means. Since various control signals are generated by performing the write operation by performing a cycle, a stable buffer memory device can be easily configured without requiring an internal control signal generation circuit using an internal oscillation source. .

According to the tenth aspect of the present invention, at least four line buffers are provided in each of the input / output stages to form a parallel / serial conversion circuit with the memory, and the line buffer is activated during a read operation. A toggle circuit that performs a toggle operation by the edge signal on the line leading edge side of the line effective image width signal in the control signal output from the output device, and the output of this toggle circuit is latched by the synchronization signal in the control signal and is positive. By providing a read period extension circuit including a latch circuit that outputs two latch signals of opposite phases, and performing a read operation using the signal output from the read period extension circuit, the memory in the buffer memory device When the data read cycle of the output device is faster than the data read cycle, the read period extension circuit Since so as to maximize within one line scanning period of the output device read period over data, as much as possible effective image data may be a buffer memory device to read.

According to the invention described in claim 11, the invention described in claim 4, 5, 6 or 7 is constituted by combining the invention described in claim 1, and according to the invention described in claim 12, The invention according to claim 4, 5, 6 or 7 is configured by combining the invention according to claim 2, and according to the invention according to claim 13, according to the invention according to claim 12, claim 3
According to the invention described in claim 14, the invention described in claim 4, 5, 6 or 7 is constituted by combining the described inventions.
The invention according to claim 2 and the invention according to claim 8 are configured in combination, and according to the invention according to claim 15,
The invention of claim 5, 6 or 7 is configured by combining the invention of claim 9, and according to the invention of claim 16, a line buffer is added to the invention of claim 4, 5, 6 or 7. According to the invention of claim 17, according to the invention of claim 17, the parallel / serial conversion circuit is formed by a plurality of at least four output stages each provided with a memory, and the invention is combined. 4, 5, 6
Alternatively, the invention according to claim 7 is constituted by combining the invention according to claim 2 and the invention according to claim 10, and according to the invention according to claim 18, the invention according to claim 17 is related to the invention according to claim 3. According to the invention described in claim 19, it is arranged between the memory device and the output device with the line buffer, the memory and the control section, and controls the data and the transfer of this data. In a buffer memory device in which a read / write operation is selected by an external signal using only a control signal as an interface, a plurality of line buffers are provided in each of the input / output stages and a parallel / serial conversion circuit is formed by the memory. In addition, the invention according to claim 8 and the invention according to claim 10 are combined and configured, and according to the invention according to claim 20, Regard the invention of 4, 5, 6 or 7, wherein, formed by combining the invention of claim 19 wherein, claim 2
According to the first aspect of the invention, the read / write operation is provided between the memory device and the output device having the line buffer, the memory and the control unit, and only the data and the control signal for controlling the transfer of the data are used as an interface. In a buffer memory device in which a write operation is selected by an external signal, at least four line buffers are provided at each input / output stage.
A parallel / serial conversion circuit is formed with a memory provided by a plurality of units, and the invention according to claim 9 and the invention according to claim 10 are combined and configured.
According to the invention described in item 2, the invention described in claim 4, 5, 6 or 7 is configured by combining the invention described in claim 21, so that a synergistic effect according to each combination can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the invention described in claim 1.

FIG. 2 is a block diagram showing an embodiment of the invention described in claim 2.

FIG. 3 is a block diagram showing the configuration of the DRAM module.

FIG. 4 is a timing chart showing an operation at the time of writing.

FIG. 5 is a timing chart showing an operation at the time of writing.

FIG. 6 is a timing chart showing an operation at the time of writing.

FIG. 7 is a timing chart showing an operation at the time of reading.

FIG. 8 is a timing chart showing an operation at the time of reading.

FIG. 9 is a timing chart showing an operation at the time of reading.

FIG. 10 is a block diagram showing an embodiment of the invention according to claim 4;

FIG. 11 is a timing chart showing signals required at the time of reading.

FIG. 12 is a block diagram showing an embodiment of the invention according to claim 5;

FIG. 13 is a block diagram showing an embodiment of the invention described in claim 6;

FIG. 14 is a block diagram showing an embodiment of the invention described in claim 7;

FIG. 15 is a block diagram showing an embodiment of the invention described in claim 8;

FIG. 16 is a block diagram showing an embodiment of the invention according to claim 9;

FIG. 17 is a block diagram showing an embodiment of the invention described in claim 10;

FIG. 18 is a timing chart showing the operation.

FIG. 19 is a block diagram showing a conventional example.

FIG. 20 is a timing chart showing the operation.

[Explanation of symbols]

 12a, 12b Line buffer 13 Memory 14-17 Buffer 19a-19d Line buffer 20 Memory 21 Control part 24 Oscillation source 25 Pseudo signal generation circuit 27 Parallel / serial conversion circuit 28 Memory 32, 33 Line counter 34 Address counter 35 Address pointer 36 Latch Circuit 37 Comparator 38 Second address pointer 40, 41 Data memory 42 Judging means 43 Stopping means 44 Selection means 45 Frequency divider 46 Read period extension circuit 47 Toggle circuit 48 Latch circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G09G 5/00 550 M 9471-5G

Claims (22)

[Claims] 1. A line buffer, a memory, and a control unit, which are arranged between a memory device and an output device.
In a buffer memory device in which a read / write operation is selected by an external signal using only data and a control signal for controlling the transfer of this data as an interface,
A buffer having a high impedance during a read operation is provided between each of the data line of the memory device and the input data line of the line buffer, and between each of the output data line of the line buffer and the data line of the memory, A buffer having a high impedance during a write operation is provided between the output data line of the line buffer and the data line of the output device, and between the data line of the memory and the input data line of the line buffer. A buffer memory device characterized by the above. 2. A line buffer, a memory, and a control unit, which are arranged between the memory device and the output device.
In a buffer memory device in which a read / write operation is selected by an external signal using only data and a control signal for controlling the transfer of this data as an interface,
A plurality of line buffers, each of which is at least four in number, are provided in the input / output stage to form a parallel / serial conversion circuit with the memory, and an oscillation source and a pseudo signal for generating a pseudo control signal based on the oscillation source. A buffer memory device provided with a generation circuit. 3. The buffer memory device according to claim 2, further comprising a blocking circuit that blocks input of various control signals output from the output device during a write operation. 4. A line buffer, a memory, and a control unit, which are arranged between the memory device and the output device.
In a buffer memory device in which a read / write operation is selected by an external signal using only data and a control signal for controlling the transfer of this data as an interface,
An address counter for counting the number of data read or written in the memory, first and second line counters for counting the number of synchronization signals in the control signal, and inputs of the outputs of the first and second line counters An address pointer that writes the output value from the address counter by the synchronization signal during the write operation as an address and outputs the count value of the written address counter during the read operation, a latch circuit that latches the end address of the line, and a read A buffer memory device comprising: a comparator for comparing an internal address value with an end address value of a line; and an address decoder for stopping the read operation of the memory by the output of the comparator. 5. A line buffer, a memory, and a control unit, which are arranged between the memory device and the output device.
In a buffer memory device in which a read / write operation is selected by an external signal using only data and a control signal for controlling the transfer of this data as an interface,
An address counter for counting the number of data read or written in the memory, first and second line counters for counting the number of synchronization signals in the control signal, and inputs of the outputs of the first and second line counters A first address pointer that writes the output value from the address counter by the synchronizing signal during the write operation as an address and outputs the written count value of the address counter during the read operation, and a latch circuit that latches the end address of the line And an address decoder having a comparator for comparing the address value being read with the end address value of the line, and a second address pointer for resetting the line start address value in the address counter by the output of the comparator. A buffer memory device characterized by. 6. An address pointer in the address decoder is a data memory in which the number of data to be written in one line is previously stored and held as data, and the address counter is loaded with the final data number of the previous line by a synchronization signal at the time of reading. , An address counter for counting and outputting the number of data in the line effective image section, a comparator as a comparator for comparing the address counter output with the data memory output, and a line counter for counting only a synchronization signal at the time of reading The buffer memory device according to claim 4 or 5, wherein 7. The data memory in the address decoder is a plurality of data memories in which the number of data required for one line according to the pixel density of the output device is stored in advance, and the corresponding data memory is selected according to the pixel density signal. 7. The buffer memory device according to claim 6, further comprising a selection circuit for performing the operation. 8. A determining means for determining a frequency of a pixel clock of an output device preset by the pixel density signal in a control signal transmitted / received to / from the output device, and the determining means. Stop means for stopping the generation of the control signal inside by stopping the oscillation source based on the judgment result of the means, the control signal generated inside based on the judgment result of the judging means, and the control signal output from the output device 4. The buffer memory device according to claim 2, further comprising a selecting means for selecting one of the two, and the write operation is performed using the control signal selected by the selecting means. 9. A line buffer, a memory, and a control unit, which are arranged between the memory device and the output device.
In a buffer memory device in which a read / write operation is selected by an external signal using only data and a control signal for controlling the transfer of this data as an interface,
The pixel density signal is included in the control signal transmitted / received to / from the output device, and the pixel density signal is used to determine the frequency of the pixel clock of the output device preset by the pixel density signal. A frequency divider having a frequency division ratio set in advance is provided, and the frequency divider divides the pixel clock output from the output device according to the determination result of the determination means to generate various control signals and perform a write operation. A buffer memory device characterized in that 10. A read / write operation is provided between a memory device and an output device having a line buffer, a memory and a control unit, and using only data and a control signal for controlling transfer of this data as an interface. In a buffer memory device selected by an external signal, each of the line buffers has at least four input / output stages.
A plurality of more than one are provided in parallel with the memory.
A toggle circuit that forms a serial conversion circuit and that performs a toggle operation with the edge signal on the line leading end side of the line effective image width signal in the control signal that is activated during the read operation and that is output from the output device, and a toggle circuit of this toggle circuit. A read period extension circuit including a latch circuit that outputs two latch signals of positive and negative phases by latching the output with the synchronization signal in the control signal is provided, and the signal output from the read period extension circuit is used for reading. A buffer memory device characterized by being adapted to perform an operation. 11. A buffer having a high impedance during a read operation between a data line of a memory device and an input data line of a line buffer, and between an output data line of the line buffer and a data line of a memory. Is provided
A buffer having a high impedance during a write operation is provided between the output data line of the line buffer and the data line of the output device, and between the data line of the memory and the input data line of the line buffer. The buffer memory device according to claim 4, 5, 6, or 7. 12. An oscillation source, a pseudo signal generating circuit for generating various control signals based on the oscillation source, a plurality of line buffers each having at least four input / output stages, a buffer at an output stage and an output. 8. A buffer memory device according to claim 4, 5, 6 or 7, further comprising a parallel / serial conversion circuit located between the device and the device. 13. The buffer memory device according to claim 12, further comprising a cutoff circuit for cutting off various control signals output from the output device during a write operation. 14. An oscillation source and a pseudo signal generation circuit for generating various control signals based on the oscillation source are provided, and the line buffer is provided in at least four input / output stages.
A plurality of more than one are provided in parallel with the memory.
Determination means for forming a serial conversion circuit, and for giving a pixel density signal in the control signal transmitted / received to / from the output device, and for determining the frequency of the pixel clock of the output device preset by the pixel density signal. A stop means for stopping the generation of the control signal inside by stopping the oscillation source based on the judgment result of the judging means, and a control signal internally generated based on the judgment result of the judging means and output from the output device 7. A control means for selecting one of the control signals to be selected is provided, and the write operation is performed by using the control signal selected by the selection means.
Alternatively, the buffer memory device according to item 7. 15. Judging means for giving a pixel density signal in a control signal transmitted and received to and from an output device, and judging a frequency of a pixel clock of the output device preset by the pixel density signal, A frequency divider having a frequency division ratio set in advance by a pixel density signal is provided, and the pixel clock output from the output device is frequency-divided by the frequency divider according to the determination result of the determination means to generate various control signals. 8. The buffer memory device according to claim 4, 5, 6 or 7, wherein a write operation is performed. 16. A control signal output from the output device, which is provided with a plurality of line buffers at the input / output stage, at least four each, to form a parallel / serial conversion circuit with a memory and which is activated during a read operation. Inside the line effective image width signal, a toggle circuit that performs a toggle operation by the edge signal on the line front side, and the output of this toggle circuit is latched by the synchronization signal in the control signal, and two latch signals of normal and reverse phases are output. 8. A read period extension circuit comprising a latch circuit for performing the read operation is provided, and a read operation is performed using a signal output from the read period extension circuit. Buffer memory device. 17. An oscillation source and a pseudo signal generation circuit for generating a pseudo control signal based on the oscillation source are provided, and a plurality of line buffers are provided in each of the input / output stages and a plurality of line buffers are provided in parallel with the memory. And a toggle circuit that forms a serial-to-serial conversion circuit and that performs a toggle operation by the edge signal on the line front side of the line effective image width signal in the control signal that is activated during the read operation and is output from the output device, and the toggle circuit. The output of is latched by the synchronizing signal in the control signal, and is
6. A read period extension circuit including a latch circuit for outputting one latch signal is provided, and a read operation is performed using a signal output from the read period extension circuit. 6. The buffer memory device according to 6 or 7. 18. The buffer memory device according to claim 17, further comprising a blocking circuit that blocks input of various control signals output from the output device during a write operation. 19. A read / write operation is provided between a memory device and an output device having a line buffer, a memory and a control unit, and using only data and a control signal for controlling transfer of this data as an interface. In a buffer memory device selected by an external signal, a pixel density signal is included in a control signal transmitted / received to / from an output device, and the pixel clock frequency of the output device preset by the pixel density signal is determined. Judging means, stopping means for stopping the oscillation source to stop the internal generation of the control signal based on the judgment result of the judging means, control signal internally generated based on the judgment result of the judging means, and the output device And a control means for selecting one of the control signals output from the A parallel / serial conversion circuit is formed by a plurality of input / output stages each including at least four input / output stages, and a line effective image width signal in a control signal output from the output device when activated during a read operation. A read circuit including a toggle circuit that performs a toggle operation with an edge signal on the line leading end side of the line, and a latch circuit that latches the output of the toggle circuit with a synchronization signal in the control signal and outputs two latch signals of positive and negative phases A period extension circuit is provided, and a write operation is performed using the control signal selected by the selection means, and a read operation is performed using the signal output from the read period extension circuit. Buffer memory device. 20. Judging means for giving a pixel density signal in a control signal transmitted / received to / from an output device, and judging the frequency of a pixel clock of the output device preset by this pixel density signal, and this judgment. Stop means for stopping the generation of the control signal inside by stopping the oscillation source based on the judgment result of the means, the control signal generated inside based on the judgment result of the judging means, and the control signal output from the output device And at least four line buffers are provided in each of the input / output stages to form a parallel / serial conversion circuit with a memory, and the output is activated when a read operation is performed. A toggle operation is performed by the edge signal on the line leading side of the line effective image width signal in the control signal output from the device. A read period extension circuit comprising a toggle circuit and a latch circuit for latching the output of the toggle circuit with a synchronizing signal in the control signal and outputting two latch signals of positive and negative phases is provided and selected by the selecting means. 8. The write operation is performed using the control signal and the read operation is performed using the signal output from the read period extension circuit. Buffer memory device. 21. A read / write operation is provided between a memory device and an output device having a line buffer, a memory and a control unit, and using only data and a control signal for controlling transfer of this data as an interface. In a buffer memory device selected by an external signal, a pixel density signal is included in a control signal transmitted / received to / from an output device, and the pixel clock frequency of the output device preset by the pixel density signal is determined. A parallel / serial conversion circuit is provided with a judging means and a frequency divider whose frequency division ratio is set in advance by the pixel density signal, and a plurality of line buffers, each of which is at least four in the input / output stage, and a memory. And the line in the control signal output from the output device is activated during read operation. A toggle circuit that performs a toggle operation with an edge signal on the line leading end side of the effective image width signal, and a latch circuit that latches the output of this toggle circuit with a synchronization signal in the control signal and outputs two latch signals of positive and negative phases. A read period extension circuit is provided, and the frequency divider divides the pixel clock output by the output device according to the determination result of the determination unit to generate various control signals and perform a write operation, A buffer memory device, wherein a read operation is performed using a signal output from the read period extension circuit. 22. Judging means for giving a pixel density signal in a control signal transmitted / received to / from an output device, and judging the frequency of a pixel clock of the output device preset by the pixel density signal; A frequency divider having a frequency division ratio set in advance by a density signal is provided, and at least four line buffers are provided in each of the input and output stages to form a parallel / serial conversion circuit with the memory, and a read operation is performed. A toggle circuit that operates at times and performs a toggle operation by the edge signal on the line leading edge side of the line effective image width signal in the control signal output from the output device, and the output of this toggle circuit by the synchronization signal in the control signal. A read period extension circuit including a latch circuit that latches and outputs two latch signals of positive and negative phases is provided.
A signal output from the read period extension circuit while dividing the pixel clock output from the output device by the frequency divider according to the determination result of the determination means to generate various control signals to perform a write operation. 8. The buffer memory device according to claim 4, 5, 6, or 7, wherein a read operation is performed by using.