JPH04315269A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To provide the semiconductor memory device enabling serial access in an arbitrary data size with simple configuration. CONSTITUTION:This device is provided with a jump function to perform random access to the arbitrary address of a two-dimensional address space at least and to perform serial access from the address, and a line reset function to perform access from the arbitrary address of the line serially accessed by the above-mentioned function to the leading address of the next line and to perform serial access from the address. While combining the above-mentioned two functions of the jump function and the line reset function, a fixed rectangular area is scanned. Since address control for segmenting the arbitrary data size can be fetched into a chip, the number of external equipments can be reduced at a system to integrate the chip, and control is simplified.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and relates to a technique that is effective for use in, for example, a serial memory having a serial input/output function for image processing.

0002

2. Description of the Related Art Serial memories having a one-dimensional address space or serial memories having a two-dimensional address space corresponding to a television screen or the like are known. Further, a line reset function for resetting to the start address (0 or 0,0), and a jump function and line reset function for randomly accessing an arbitrary address are well known. An example of a serial memory with the above-mentioned line reset function is the "Field Buffer Memory μPD42270" sold by NEC Corporation, and an example of a serial memory with a jump function is the "Field Buffer Memory μPD42270" sold by Hitachi, Ltd. "Frame memory HM"
53051”.

FIG. 6 shows a block diagram of an example of a conventional serial memory. In order to achieve high-speed serial access, registers WR and RR are provided, and data read/write between the memory array MARY and the register is executed in parallel for one register length, and registers WR and RR perform parallel/serial conversion or Serial/parallel conversion is performed to serially read or write data between registers WR and RR and the outside. Thereby, serial access with the outside can be performed at high speed compared to the time required for internal memory read/write cycles.

To enable continuous serial access, buffers WB and RB with the same data size as registers WR and RR are provided, and while the data in register RR is serially read externally, the next read data is transferred to the memory array. Read from MARY to buffer RB and wait. Data serially written from the outside is transferred from the register WR to the buffer WB, and written in parallel to the memory array MARY while the next input data from the outside is serially written to the register WR. With the above, data can be serially accessed without interruption. When resetting a read or write address to "0", a dedicated register is provided so that serial access starts continuously from "0" without waiting time when a reset command is applied from the outside. “
In some cases, the latest data of 0'' can be read out at any time.

[0005]

Problems to be Solved by the Invention Memory data handled in systems in the image field, communication field, etc. is often scanned by cutting out a rectangular area due to its data characteristics or by cutting out a rectangular area. Alternatively, memory has a storage capacity that is designed for general purpose.
The cost of the chip will not be reduced unless the address structure is adopted and the mass production effect is achieved, so in order to support systems that handle two-dimensional data such as various image data, it is necessary to assume a somewhat large image data size. There is a need. Therefore, each user must be able to access memory with a data size suitable for his/her own user system. In this case, since the serial memory only has the above-mentioned reset function, jump function, and line reset function, it is necessary to provide an external counter and address control circuit to specify the required individual data size. It turns out. Therefore, there are problems in that the number of external parts increases and the data size becomes fixed due to the external circuit. An object of the present invention is to provide a semiconductor memory device that allows serial access of arbitrary data size with a simple configuration. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0006]

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows. In other words, there is a jump function that randomly accesses an arbitrary address in at least a two-dimensional address space and serially accesses from that address, and a jump function that allows you to access the next line from an arbitrary address of the line that is serially accessed using the above function. It has a line reset function of accessing the first address of , and serially accessing from that address, and performs an access mode of scanning a fixed rectangular area by combining the above two jump functions and the line reset function.

[0007]

[Operation] According to the above-mentioned means, since address control for cutting out data of arbitrary size can be incorporated into the chip, the number of external parts in a system incorporating it can be reduced and control can be simplified.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a block diagram of an example of a semiconductor memory device to which the present invention is applied. The embodiment shown in the figure is directed to a serial memory, and each circuit block in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. In order to achieve high-speed serial access as described above, a write register WR and a read register RR are provided to read and write data between the memory array MARY in which memory cells are two-dimensionally arranged and the registers WR and RR. executes data for one register length in parallel, performs parallel/serial conversion or serial/parallel conversion using registers WR and RR, and stores data in register W.
Read or write data between R, RR and the outside in a serial manner. Thereby, serial access with the outside can be performed at high speed compared to the time required for internal memory read/write cycles.

To enable continuous serial access, a write buffer WB and a read buffer RB of the same data size as registers WR and RR are provided.
The next read data is read from the memory array MARY to the buffer RB and waits. Furthermore, the data serially written from the outside is transferred from the register WR to the buffer WB, and while the next input data from the outside is serially written to the register WR, the data transferred to the buffer WB is transferred to the memory array MARY. are written in parallel. With the above, data can be serially accessed without interruption.

[0010] In order to perform window scans continuously, a means is required that can perform jumps and line resets continuously without waiting time. Since the jump address and line reset address are arbitrary, it is not possible to provide a dedicated register with a fixed address like the "0" reset register described above. In this embodiment, as shown in FIG. 1, there is provided an A read buffer ARB dedicated for jumping and an L read buffer LRB dedicated for line reset.

The operations of each of the buffers ARB and LRB are as follows:
It is as follows. When a read jump address is input from the outside, memory data at this address is read to the A read buffer ARB. When writing to the address set as the read jump address is executed, the latest write data is read to the A read buffer ARB. At the time of line reset (including internal increment), jump, or reset, the start address of the line next to the line where access is to be started after the reset is read to the L read buffer LRB. When writing is performed to the start address data of the next line while reading a certain line, this latest data is read to the L read buffer LRB. Regarding the write operation, the data is written to the memory array MARY using the same means as a normal address.

[0012] As described above, the data at the set jump address (A) and the data at the start address (L) of the next line being read are such that the latest written data is A.
Read buffer ARB and L read buffer LR
This means that it is being read out to B. Therefore, when a jump or line reset command is externally applied, the data in the A read buffer RAB or the L read buffer LRB can be immediately transferred to the register RR, and serial reading can be started without waiting time. . Also, the next address data is stored in this A read buffer A.
Since the data in the RB or L read buffer LRB can be read to the read buffer RB during serial reading, jumps and line reset reads can be performed continuously without interruption.

In the conventional serial memory configuration shown in FIG. 6, in order to read the latest written data, a write operation is performed to the memory array MARY after the serial input is completed, and then a write operation is performed from the memory array MARY to the read buffer RBB. It takes two cycles of memory operation to read the data. This point is the same for jumps and line resets explained in the above embodiments; after data is written to the set jump address, two cycles of memory operation are required to execute the jump and read the latest data. I need to wait a minute.

FIG. 2 shows a conceptual diagram of an embodiment of the window scan operation according to the present invention. When accessing the start address A (Hw, Vw) of the window scan area in order to start scanning the window scan area, the jump function as described above is used. That is,
When a read jump address is input from the outside while data on line Vn is being serially output in normal serial read, a jump is made to the start address A in operation 3. In this way, it is possible to seamlessly transition from normal scan to window scan.

[0015] After that, in normal scan, the address after the jump is incremented and accessed, and after accessing the final address of the same line, the address is incremented to the beginning of the next line, but in window scan mode, the jump address and the end point address are Must jump to the start address of the next line within the rectangular area specified by . At this time, the line reset function as described above is used. When entering the window scan mode, the H address of the read address to the L read buffer LRB is fixed to the H address Hw at the left end of the rectangular area. Thereby, line reset in window scan mode can be accessed continuously without interruption.

FIG. 3 shows a conceptual diagram of another embodiment of the window scan operation according to the present invention. In the embodiment shown in FIG. 2, the line reset function and jump function are used to flexibly specify the end point address from the outside for each line and each window scan. In contrast, in this embodiment, the end point address B is specified externally, and line reset and reset to the window start point are automatically controlled within the chip by monitoring this end point address.

FIG. 4 shows a conceptual diagram of another embodiment of the window scan operation according to the present invention. In this embodiment, the address of the center point W of the window and the sizes Hw and Vw of the window are specified. In this case, it is most suitable for an application system where the center point W of the window does not change and the window size is variable, such as electronic zoom.

FIG. 5 shows a conceptual diagram of still another embodiment of the window scan operation according to the present invention. This embodiment supports multi-windows. Continuous scanning is also performed for multi-windows by sequentially jumping the windows in a fixed order from the end point address Bn of each window to the start point An+1 of the next window (operation 3). In the figure, an example of three windows is shown, and an example of jumping from the end point B1 of the first window to the start point A2 of the next window, and from the end point of that window to the start point A3 of the last window is shown. .

FIG. 14 shows an overall block diagram of an embodiment of a serial memory with a window scan function according to the present invention. Each circuit block in the figure is formed on a single semiconductor substrate such as single crystal silicon using a known semiconductor integrated circuit manufacturing technique. The serial input buffer SIB takes in write data serially input from the input terminal IN in accordance with the write clock WCK, and transmits it to the write register WR. The write register WR converts the data in units of 32 bits taken in via the serial input buffer SIB into parallel data and transfers it to the write buffer WB. The write register WR may be a shift register, or the output signal of a counter that counts the write clock WCK is decoded by a decoder circuit, and a latch circuit pointed by the selection signal performs the same function as a shift register. It may be realized.

The write buffer WB is composed of 32 latch circuits that receive write data in units of 32 bits in parallel. Each latch circuit takes in write data from the write register WR in parallel in response to a write load signal generated by the write reset mode decoder WMD or the write counter WC. Then, a signal is output based on a write data transfer signal formed by the memory operation control unit MOC. As a result, parallel writing is performed on the memory block MB in units of 32 bits. Memory block MB is
It basically consists of a dynamic RAM (random access memory) memory array and its address selection circuit.

FIG. 15 shows a specific internal configuration diagram of one embodiment of memory block MB. The memory block MB selects the bit line 1/N by a selection signal formed by a memory array MARY similar to a normal dynamic RAM, a sense amplifier SA, and a decoder circuit YDEC that decodes the Y address MYA. A column switch circuit CW, a sub-sense amplifier SBA for forcibly inverting the sense amplifier SA according to write data during a write operation to the memory array MARY, and a word line selection signal is formed by decoding the X address MXA. It consists of a decoder circuit XDEC and a decoder circuit XDEC. Selection of 1/N of bit lines selects 32×9 bits of data in total. Actually, one memory array MARY is composed of 960 word lines and 32×9×3 bit lines, and a total of 3 mats (×3) are provided. Therefore, for one memory mat (memory array), column switch CW performs 1/9 selection in units of 3 bits. The sub-sense amplifier SBA is entirely connected to the memory mat M.
Like ARY, it is composed of three parts. Sub-sense amplifier SBA is coupled via an internal data bus to the write buffer WB on one side and to a read buffer RB, which will be described later, on the other side. With the above memory configuration, for example, if pixel data constituting one pixel is assigned 3 bits each to the three primary colors of red, blue, and green, a multicolor display of 512 colors can be achieved.

In FIG. 14, the read buffer RB is
Receives 32-bit data in parallel. The read buffer RB is for holding the next data to be serially outputted by the read register RR. That is, while the read register RR is serially outputting data consisting of 32 bits as described above, the data to be serially output next is read from the memory block MB and transferred in parallel to the read buffer RB. be done. The read buffer RB takes in 32-bit data in parallel based on the signal S1 generated by the memory operation control unit MOC. Parallel transfer from read buffer RB to read register RR is performed by read load signal S5 output from read counter RC. In reality, since each 9 bits are serially output as described above, the number of read buffers RB is nine in total.

The A read buffer ARB holds data to be output from the read register RR at the time of address jump. The data is taken in using a signal S3 generated by the memory operation control unit MOC. Signal S3 is read reset mode decoder RM
■When the read jump setting is changed by the signal (b) formed by D, the address controller AD
A signal (e) formed by C is generated when data is written to the set read jump address. Data transfer from A read buffer ARB to read register RR is performed by read load signal S7 generated by read reset mode decoder RMD. As a result, when jump or window mode is specified, serial data can be output from the specified address without waiting time.

The 0 read buffer 0RB holds address 0 data. Data is taken in using a signal S2 generated by the memory operation control unit MOC. Data transfer from 0 read buffer 0RB to read register RR is performed by read load signal S6 generated by read reset mode decoder RMD. Thereby, when the start address is reset to (0, 0), the data at the start address can be serially output without waiting time. L read buffer L
RB holds data to be output from the read register RR at the time of line reset. Data is taken in by a signal S4 generated by the memory operation control unit MOC. Signal S4 is used when: ■ When the line address being read changes due to 0 reset, line reset, or jump (captures the data at the start address of the next line after the change), ■ Reads the data at the address in a certain line to register RR. This is generated by the memory operation control unit MOC when the address data of the next line is rewritten by writing during output from the memory operation control unit MOC. Data transfer from the L read buffer LRB to the read register RR is performed by a read load signal S8 generated by a read reset mode decoder RMD. This results in
When a line reset is performed, data at the start address of the next line can be serially output without waiting time.

The read register RR receives 32 bits of data from each read buffer in parallel and converts it into serial data. The read register RR takes in parallel data at a timing according to signals S5 to S8. The serial output buffer SOB receives an internal clock (n
) is an output buffer that performs synchronous operation based on

[0026] The write reset mode decoder WMD is
It receives a control signal supplied from an external terminal, decodes it, selects a reset mode, and sends a memory operation request signal to the read/write/refresh arbitration logic circuit ABLG according to the mode, and also outputs a write register. Generates a timing signal to load data from WR to write buffer WB. The reset mode by the write reset mode decoder WMD is set by the following combination of control signals.

Write reset signal WRS, write address set signal WAS, write line reset signal WLR
S, the write window signal WWND, and the write clear signal WCLR are all external control signals whose low level (L) is an active level, and the following eight modes are set by their combinations. Here, H means high level, and blank means invalid. ■W
RS=H, WAS=H, WLRS=H, WWND=H,
When WCLR=H, a mode is set in which the write address is incremented in synchronization with the write clock WCK. ■ WRS=L, WAS=H, WLRS=
When H, WWND=H, and WCLR=H, the mode is set in which the write address is reset to (0, 0). ■
WRS=L, WAS=L, WLRS=H, WWND
=H and WCLR=H, the mode is set in which the write address is jumped to the set address 'A'. ■
WRS=H, WAS=L, WLRS=H, WWND=
, when WCLR=H, the mode is set to input a write jump address.

■ WRS=H, WAS=H, WLRS
When =L, WWND=H, and WCLR=H, a mode is set in which the write address is reset to the start address of the next line. ■ WRS=L, WAS=, WLR
When S=H, WWND=L, and WCLR=H, a mode is set in which the write address is reset to the window start address 'A'. ■ WRS=H, WAS
When =H, WLRS=L, WWND=L, and WCLR=H, a mode is set in which the write address is reset to the left end of the window of the next line. ■ WRS= ,
WAS= , WLRS= , WWND= , WC
When LR=L, a mode is set in which the set address and window are cleared and the write address is reset to (0, 0).

The read reset mode decoder RMD is
Receives a control signal supplied from an external terminal, decodes it, selects a reset mode, selects and enables one of the read load signals of signals S6 to S8 according to the mode, and also reads the read load signal from the memory block MB. A request signal for a read operation to read data into the read buffer RB, A read buffer ARB, and L read buffer LAB is sent to the read/write/refresh arbitration logic circuit ABLG. The reset mode by the read reset mode decoder RMD is set by the following combination of control signals.

Read reset signal RRS, read address set signal RAS, read line reset signal RLR
S, read window signal RWND, and read clear signal RCLR are all external control signals whose low level (L) is an active level, and the following eight modes are set by their combination. Here, H means high level, and blank means invalid. ■ R
RS=H, RAS=H, RLRS=H, RWND=H,
When RCLR=H, a mode is set in which the read address is incremented in synchronization with the read clock RCK. ■ RRS=L, RAS=H, RLRS=
When H, RWND=H, and RCLR=H, a mode is set in which the read address is reset to (0, 0). ■
RRS=L, RAS=L, RLRS=H, RWND
=H and RCLR=H, the mode is set in which the read address is jumped to the set address 'A'. ■
RRS=H, RAS=L, RLRS=H, RWND=
, RCLR=H, the read jump address input mode is entered.

■ RRS=H, RAS=H, RLRS
When =L, RWND=H, and RCLR=H, a mode is set in which the read address is reset to the start address of the next line. ■ RRS=L, RAS= , RLR
When S=H, RWND=L, and RCLR=H, a mode is set in which the read address is reset to the window start address 'A'. ■ RRS=H, RAS
When =H, RLRS=L, RWND=L, and RCLR=H, a mode is set in which the read address is reset to the left end of the window of the next line. ■ RRS= ,
RAS= , RLRS= , RWND= , RC
When LR=L, a mode is set in which the set address and window are cleared and the read address is reset to (0, 0).

The write counter WC counts 32 bits in accordance with the internal write clock signal formed by the write clock buffer WCKB which receives the write clock signal WCK input from the outside, and the data consisting of the above 32 bits is counted every 32 bits. A load signal is generated to transfer the stored data of the write register WR to the write buffer WB in parallel. In addition, the write counter WC transfers the data transferred to the write buffer WB,
A request signal (c) for a write operation to the memory array of memory block MB is sent to read/write/refresh arbitration logic circuit ABLG. The counter of the write counter WC is reset by a reset signal (j) generated by the write reset mode decoder RMD in accordance with the specification of the operation mode as described above.

Read counter RC counts 32 bits in accordance with an internal read clock signal formed by read clock buffer RCKB which receives externally input read clock signal RCK, and counts the data consisting of the above 32 bits every 32 bits. The completion of serial output is monitored and the read load signal S5 is enabled. In addition, the read counter RC sends a request signal (d) for read/write/refresh arbitration to read data at the next address from the memory array of the memory block MB to the read buffer RB for the data loaded by the signal S5. logic circuit ABLG
send to The counter reset of the read counter RC is performed by the reset signal (k
).

The refresh counter RFC counts the clocks generated by the internal clock generation circuit CKG and issues a refresh operation request signal (l) at a cycle as required.
) to the read/write/refresh arbitration logic circuit ABLG. Internal clock generation circuit CK
G consists of an oscillation circuit that operates constantly while the power is turned on, and is used to form a memory refresh clock. The read/write/refresh arbitration logic circuit ABLG receives memory operation request signals (a) and (b) from the write reset mode decoder WMD, read reset mode decoder RMD, write counter WC, read counter RC, and refresh counter RFC.
, (c), (d), and (l) and a memory operation request signal (e) from the address control unit ADC, which will be explained next, are prioritized to determine the memory operation, and the memory operation designation signal (f) is Memory operation control unit MOC and address control unit AD
Send to C.

The address control unit ADC includes a read/write/refresh arbitration logic circuit ABLG.
A necessary address is generated based on the memory operation designation signal (f) sent from the memory operation control unit MOC, and the address signal (g) is sent to the memory operation control unit MOC. The address control unit ADC compares the write address, the set read jump address, and the start address of the next line of the line being serially read, and if they are the same, the address controller ADC sends the write address to the read/write/refresh arbitration logic circuit ABLG. On the other hand, (E
) Read jump address data to memory block M
Sends a memory operation request signal (e) to reread data from memory array B to read buffer A, and (F) reread data at the start address of the next line of the line being serially read to read buffer LRB. do. The address control unit ADC monitors whether the read address and write address are the final line address or the final screen address. If it corresponds to the above line final address, a request signal for the read/write operation necessary for internal automatic reset is generated, and if it corresponds to the above screen final address, the read/write operation necessary for internal automatic line reset is generated. A request signal (e) is generated and sent to the read/write/refresh arbitration logic circuit ABLG, respectively.

The memory operation control unit MOC includes a read/write/refresh arbitration logic circuit ABL.
Memory operation designation signal (f) from G, address control section A
The following memory operations (1) through (2) are controlled by the address signal (g) from the DC. ■Operation of X decoder XDEC, ■Word line activation, ■Operation of sense amplifier SA,
■Y decoder YDEC operation, ■Activation of column switch CW, ■Operation of sub-sense amplifier SBA, ■Select data transfer signal (S1 to S3) by signal (f) and activate at necessary timing (refresh operation (sometimes not activated), ■Precharge operation.

FIG. 7 shows a concrete block diagram of one embodiment of the address control section ADC. External terminal R
AD and WAD are read jump addresses, respectively.
This is an address terminal for inputting a write jump address. These jump addresses are read clock RCK
, is input serially in synchronization with the write clock. These jump addresses are stored in address buffer ExRAB for reading and address buffer ExWA for writing.
It is taken in via B. Signals RAS0 and WAS0 are activation signals thereof. The above address buffer ExRAB
A jump address signal consisting of 15 bits input serially through ExWAB is converted into parallel signals by a read address conversion circuit RAC and a write address conversion circuit WAC, respectively. Jump address register Ex
RARG and ExWARG are for storing the jump addresses converted into parallel, respectively.

Read address register RARG, write address register WARG, and refresh address register RFAR store the output of A address incrementer AAIN, which increments the address of memory address register MARG according to the operation mode after memory operation is started. do. A register selection signal indicating in which address register the incremented address is to be stored is generated by an address control unit ADC, which will be described later. Address register ExRA+1 stores an address incremented by 1 from the read jump address. Under the control of the address control unit ADC, which will be described later, the read jump address of the memory address register MARG is incremented by the incrementer AAIN and stored in the address register ExRA+1. Address register LsWARG has write data of 3
This is used to store the last address when a write reset is applied with less than 2 bits. Address register LRA+1 is for storing the next address of the line address being serially output, and address register LRA+1 is for storing the next address of the line address being serially input. The next line address is determined by the control signal of the address control unit ADC.
Set the line address of memory address register MARG to V
It is formed by incrementing by address incrementer VAIN.

The A address comparison circuit AACP compares the write address and the read jump address A stored in the address register ExRAG, and when they match, generates a control signal ARRQ corresponding to the signal (e) in FIG. 14. The V address comparison circuit VACP compares the write address and the next line address V stored in the address register LRA+1, and when they match, outputs the signal (
A control signal LRRQ corresponding to e) is generated. The address reset circuit AR resets only the address A or H address of the memory address register MARG to 0 or 1 depending on the reset mode. Reset control is performed by the next address control unit ADC. The memory address register MARG stores necessary addresses in each of the above address registers R under the control of the address control unit ADC.
ARG, WARG, RFAR, ExRARG, ExWA
RG, ExRA+1, LsWARG, LRA+1 and L
WA+1 and the address reset circuit AR are pulled out and stored, and the X decoder XDEC of the memory block MB is
Addresses MXA and MYA required for Y decoder YDEC
generates an address.

The A address incrementer AAIN and the V address incrementer VAIN increment the address of the memory address register MARG to form an address to be re-stored in each of the address registers. These address incrementers AAIN and VAIN are controlled by an address control unit ADC. The read final address decoder RFLAD and the write final address decoder WFLAD monitor the final read and write addresses, respectively, and generate internally automatically generated line resets LRSin, LWSin, and 0 reset RSin.
, WSin and sends it to the read/write/refresh arbitration logic circuit ABLG. The above signals form a memory operation request signal (e).

FIG. 8 shows a block diagram of an embodiment of the read reset mode decoder RMD and the write reset mode decoder WMD. The upper half of the figure shows a block diagram corresponding to the read reset mode decoder RMD. The read reset mode decoder RMD, AS read request ASRQ, and reset read request RRRQ in the figure are as described in FIG. 14 above. This read reset mode decoder R
Among the signals in the MD, the read load signal RLoa
d0 corresponds to the signal S6 and is the read load signal RLo.
adA corresponds to the signal S7 and is the read load signal RL.
oadL corresponds to the signal S8. Also,
The signal (b) output from the read reset mode decoder RMD in FIG. 14 is a read request signal ASRQ to the A read buffer ARB, a read request signal RSRQ to the read buffer RB, and a read request signal LSRQ to the L read buffer LRB. Equivalent to. Read counter RC
, read load RL, and read request RRQ, the signal S5 is the read load signal RLoad.
Corresponding to S, the signal (d) corresponds to a read operation request signal SRRQ to the read buffer RB. Note that CGR is a clock gate read signal, which is fetched via a clock gate read buffer CGRB to control a read counter RC and the like. The function of this clock gate read signal is not directly related to the present invention, so a description thereof will be omitted.

A block diagram corresponding to write reset mode decoder WMD is shown in the lower half of the figure. The write reset mode decoder WMD, 0 read request 0RRQ, write load WL, write counter WC, and write request WRQ in the same figure are shown in FIG.
As explained in . Among the signals in write reset mode decoder WMD, the write load signal supplied to write register WR corresponds to write load signals WLoadS and WLoadA. The usage of S and A depends on whether the write reset timing is full 32 bits or less than 32 bits. Such different use of signals is not particularly required. Signal (a) in FIG. 14 is 0 read buffer 0 when data is changed by writing to 0 address.
This corresponds to the request signal 0RRQ for re-reading the newly written data at address 0 to RB. Signal (c) is a request signal SW for a write operation from the write buffer WB to the memory array to the memory block MB.
Corresponds to RQ and AWRQ. The usage of S and A above is as follows:
Same as above. Write address predecoder WAPD
forms a signal input to the decoder forming the write register WR. The latch circuit WRL latches the reset mode for 32 clocks. This is because, unlike the read operation, in the write operation, a data write request occurs 32 bits (clocks) after a reset and new data starts, so the reset mode is latched during that time. Clock gate write CGW and clock gate write buffer CGWB are not directly related to the present invention, and thus their explanation will be omitted like the read reset mode RMD.

FIG. 9 shows a block diagram of a specific embodiment of other parts of the address control unit ADC. The memory address selector MASL is the read/write/refresh arbitration logic circuit ABLG in FIG.
When the memory operation is determined, one of the address registers to transfer the address to the memory address register MAR in FIG. 7 is selected. Actually, SR, RS
, LS, AS, 0R, LR, SW, AW, REF 10
There are different types of memory operations. The address is determined by adding a reset mode to this. The increment address register selector INASL increments the address transferred from the memory address register by the memory address selector MASL after the memory operation starts, and re-stores it in each address register as necessary. Increment address register selector INASL
is used to select the storage destination address register at that time.

FIGS. 10 to 12 show timing charts for explaining an example of the operation of the serial memory. Further, FIG. 13 shows a conceptual diagram showing a memory address space corresponding to the operation. In the serial memory of this embodiment, serial read and serial write are performed asynchronously and independently of each other. However, since the serial read is performed in synchronization with the serial clock RCK and the serial write is performed in synchronization with the serial clock WCK, the read clock R supplied from the external terminal
By using the same clock as CK and write clock WCK, read operation and write operation can be synchronized.

The serial write operation shown in FIGS. 10 to 12 shifts from the normal write state to the window write operation shown by the broken line in FIG. 13, and then (M'
, N') is shown. In addition, in the serial write operation, window read operation 1 (Read-Wind 1) and window read operation 2 (Read-Wind 2) as shown by dotted lines in FIG. 13 are performed from the normal read state, and finally the window mode is reset. An example is shown.

In FIG. 10, the suffix B of the signal means that the low level is the active level. In the normal write mode, a jump address is captured in response to the write address set signal WASB being set to low level. A write address consisting of 16 bits in total is serially fetched from the write address terminal WAD. The fetching of such a jump address is performed in synchronization with the write clock WCKB similarly to the write data. Write address set signal WASB and write reset signal WRSB
When the write window signal WWND is set to low level, the window mode is set. A jump is made to the above-mentioned fetched address (M, N), and fetching of write data Din of 32 bits each is started from there. The final address of the N line is performed by setting the write line reset signal WLRSB to a low level. As a result, the right edge of the window on line N is (
M+m)×32+k bits.

In the normal read mode, a jump address is captured in response to the read address set signal RASB being set to low level. A read address consisting of 16 bits in total is serially fetched from the read address terminal RAD. The fetching of such a jump address is performed in synchronization with the read clock RCKB similarly to the read data. Read address set signal RASB and read reset signal RRSB
When the read window signal RWND is set to low level, the window mode is set. A jump is made to the address (P, Q) taken in above, and read data of 32 bits each is serially output from there. In this way, serial output of the data corresponding to the jump address (P, Q) specified at the same time as setting the window mode is performed after the jump address is captured and read from the memory block MB. This is because the data corresponding to the A read buffer ARB has already been stored and preparations have been made for reading without waiting time as described above. In the write window mode and read window mode as described above, updating of addresses in units of 32 bits on the same line is performed by monitor outputs of the write counter WC and read counter RC.

In FIG. 11, line updating (N+1) in the write window mode is performed in synchronization with the low level of the write line reset signal WLRSB. This write line reset signal WLRSB is synchronized with the write clock WCK, and enables line reset in bit units instead of address setting in word (32 bit) units as in window setting. That is,
An external control circuit counts write clocks WCK, and after counting k clocks, outputs a write line reset signal W.
When LRSB is set to low level, a line reset can be applied at that timing. As a result, the width of the light window can be set to 32×m+k bits. This also applies to line updating (Q+1) in the read window mode, which is performed in synchronization with the low level of the read line reset signal RLRSB. This read line reset signal RLRSB is synchronized with the read clock RCK, and enables line reset in bit units instead of address setting in word (32 bit) units as in window setting.

In FIG. 12, the read operation is performed in window 1 by the low level of the read reset signal RRSB.
Returns to the first address (P, Q) and performs a serial read operation for read window 1. During this serial read, set the read address set signal RASB to low level,
A new address (P', Q') corresponding to the beginning of the second read window is fetched. Then, read window mode RWN corresponds to the above window mode.
Since DB is at low level, when the read address set signal RASB and read reset signal RRSB are set to low level, serial read output is performed from the new address (P', Q'). And read clear signal RC
When LRB goes low, the read window mode is reset and the first address of the address space (
0, 0), and serial reading starts from there. At this time as well, since the data at the start address (0,0) is stored in the 0 read buffer 0RB, it can be serially output immediately without waiting time. In addition, due to serial write operations performed in parallel,
When writing is performed to the above start address (0,0),
The address comparison circuit monitors this and reads the latest rewritten data to the 0 read buffer 0RB.

Although not shown in the drawings, in the write operation, the window mode is reset by the low level of write clear WCLRB and a normal write operation is performed, similar to the read operation described above. During this normal write operation, the write address set signal WASB is set to a low level and a new address (M', N') is taken in. After this, write address set signal RASB and write reset signal W
When RSB is set to low level, the new address (M', N'
), and the serial write operation starts from there. That is, if the write window signal WWNDB is left at a high level, a jump is made to a new address and a serial write operation is started from there. And N
When the final address HE of ' is reached, the line address is updated (N'+1) by an internal automatic reset operation, and
Serial write is performed from (0, N'+1).

The effects obtained from the above examples are as follows. (1) It has at least a two-dimensional address space, and serially input data is internally converted into parallel data and written in units of multiple bits to the memory array assigned to the two-dimensional address space, and multiple bits are written from the memory array. A function that internally converts data read in parallel in bits into serial data and outputs it serially.
A serial memory that has a jump function that randomly accesses an arbitrary address and serially accesses from that address, and a line reset function that accesses the start address of the next line from any address on the line that is being serially accessed. By specifying a specific operation mode, the above two jump functions and line reset function are combined to define the start address and leftmost address specified by the jump function, and the rightmost and final address specified by the reset timing. The effect is that it is possible to realize an access mode in which a certain rectangular area is scanned. (2) The window scan mode described in (1) above allows address control for extracting arbitrary data sizes to be incorporated into the chip, which has the effect of reducing the number of external parts in a system that incorporates it and simplifying control. It will be done. (3) By inputting the two addresses of the start point and end point of the rectangular area from the outside, it is possible to automatically set the rectangular area internally.

(4) The address of the starting point of the rectangular area is specified by the jump function, and if there is no external specification, the final address of the entire memory area is the ending point, and if there is an external specification, that is the ending point. By using the above jump function to return to the specified starting point, the window scan mode can be realized simply by combining the above two jump functions and the reset function, and the circuit can be simplified accordingly. This effect can be obtained. (5) The end point address of the X system among the end points of the above rectangular area is externally specified by the above line reset function, and the data of the start point address of the specified rectangular area of the next line is stored in a dedicated buffer in advance. By reading the data in advance, it is possible to realize a serial window with no waiting time. (6) Among the above end point addresses, the end point address of the Y system is specified from outside using the jump function, and in window scan mode, the end point address of the rectangular area set after the line access of this specified end point address is completed. By resetting, it is possible to set the end point address in units of bits or pixels. (7) The window scan mode specified above can be canceled at any timing during the scan, and the serial number including the window scan mode can be canceled at any address newly set by specifying another jump or reset. By performing access, it is possible to realize a serial memory with an easy-to-use window scan function.

[0053] The invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say. For example, one word can be arbitrarily set to 32 bits, 40 bits, 48 bits, etc. Correspondingly, the configuration of the column switch of the memory array, the number of bits of the write buffer, write register, read buffer, and read register are also determined. Further, as the dedicated read buffer, the 0 read buffer, L read buffer, and A read buffer may be made common and replaced with a general-purpose read buffer by limiting the timing at which jumps and resets occur. The control circuits such as the memory control section and the address control section may be of any type as long as they realize the same functions as described above. Further, the address structure of the memory block may be such that a Z space is added in addition to the X, Y address space to configure a three-dimensional space and perform three-dimensional serial scanning.

[0054] The above explanation mainly describes the invention made by the inventor of the present application, which is the technical field in which it is based.
Although the case where the present invention is applied to a serial memory using AM has been described, the present invention is not limited to this, and the memory block MB may be configured using static memory cells. In this case, refresh control is not required, which simplifies control, and a sense amplifier that amplifies minute signals stored in an information storage capacitor, such as in dynamic RAM, is not required, resulting in faster operation and better control. becomes easier. In addition, data is input and output externally in serial, converted internally to parallel, and read/written, and the memory array is accessed in a fixed order according to clock pulses supplied from the outside. , data may be input/output according to the address. That is, the present invention can be widely used as an address setting technique for selectively specifying data in a certain area, in addition to being applied to window scan in a serial memory as in the embodiments described above. Therefore, data input/output is internally serial/parallel converted as described above.
In addition to those that perform parallel/serial conversion, various embodiments can be adopted, such as those that input/output data units, and those that input/output a relatively large amount of data in parallel.

[0055]

Effects of the Invention A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, it has at least a two-dimensional address space, internally converts serial input data into parallel data, writes it in units of multiple bits to a memory array assigned to the two-dimensional address space, and reads multiple bits from the memory array. It has a function to internally convert the data read out in parallel in units of 0 to serial and output it serially, a jump function to randomly access an arbitrary address and access it serially from that address, and a jump function to access it serially from that address. For serial memory that has a line reset function that accesses the start address of the next line from any address of the current line, the above two jump functions and line reset function can be combined to jump by specifying a specific operation mode. It is possible to realize an access mode in which a rectangular area defined by the start address and left end address specified by the function, and the right end and final address specified by the reset timing is scanned.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a serial memory according to the present invention.

FIG. 2 is an operation conceptual diagram showing an example of window scan operation according to the present invention.

FIG. 3 is an operation conceptual diagram showing another embodiment of the window scan operation according to the present invention.

FIG. 4 is an operation conceptual diagram showing another embodiment of the window scan operation according to the present invention.

FIG. 5 is an operation conceptual diagram showing still another embodiment of the window scan operation according to the present invention.

FIG. 6 is a block diagram showing an example of a conventional serial memory.

FIG. 7 is a block diagram showing a specific embodiment of an address control section of a serial memory according to the present invention.

FIG. 8 is a block diagram showing a specific embodiment of a reset mode decoder for a serial memory according to the present invention.

FIG. 9 is a block diagram showing a specific embodiment of another part of the address control section of the serial memory according to the present invention.

FIG. 10 is a timing diagram for explaining an example of the operation of the serial memory according to the present invention.

FIG. 11 is a timing diagram for explaining an example of the operation of the serial memory according to the present invention.

FIG. 12 is a timing diagram for explaining an example of the operation of the serial memory according to the present invention.

FIG. 13 is a conceptual diagram of an address space corresponding to the operations shown in FIGS. 10 to 12 above.

FIG. 14 is an overall block diagram showing a specific embodiment of a serial memory according to the present invention.

FIG. 15 is a specific block diagram showing an embodiment of a memory block section of a serial memory according to the present invention.

[Explanation of symbols]

WR...Write register, WB...Write buffer, RB...
Read buffer, RR...read register, ARB...A read buffer, LRB...L read buffer, MARY...
Memory array, MB...memory block, 0RB...0 read buffer, SOB...serial output buffer, SIB...
Serial input buffer, MOC...memory operation control unit, A
DC...address control unit, ABLG...read/write/refresh arbitration logic circuit, RC...read counter, WC...write counter, RFC...refresh counter, WMD...write reset mode decoder, RMD...read reset mode decoder, RCKB...
Write clock buffer, WCKB...Write clock buffer, CKG...Clock oscillation circuit, SA...Sense amplifier, CW...Column switch, SBA...Sub sense amplifier, XDEC...X decoder, YDEC...Y decoder, RA
C...Read address counter, WAC...Write address counter, RARG...Read address register, WAR
G...Write address register, RFRG...Refresh address register, ExRARG...Read jump address register, ExWARG...Write jump address register, EXRA+1, LsWARG, LRA+1,
WLA+1...address register, RFLAD...read final address register, WFLAD...write final address register, AACP...A address comparison circuit, VACP...V address comparison circuit, MARG...memory address register, AR...address reset, AAIN
...A address incrementer, VAIN...V address incrementer, MASL...memory address selector, I
NADL...Increment address register selector.

Claims (7)

[Claims] Claim 1: A memory array having a two-dimensional address space consisting of at least an During memory access, random access to an arbitrary address specified by an externally supplied address is performed.
It has a jump function that accesses from that address in the above fixed order, and a reset function that accesses the next Y series start address from any Y series address accessed in the above fixed order. . A semiconductor memory device characterized in that an access mode is executed in which a certain rectangular area is scanned by combining the jump function and the line reset function by specifying a specific operation mode. 2. The memory array has at least a two-dimensional address space, internally converts serially input data into parallel data, and writes data in units of multiple bits to a memory array allocated to the two-dimensional address space. There is a function to internally convert the data read out in parallel in multiple bits from the . It has a line reset function that accesses the start address of the next line from any address of the line being accessed, and by specifying a specific operation mode, the above jump function and line reset function can be combined to create a fixed rectangular area. A semiconductor storage device characterized by executing a scanning access mode. 3. The semiconductor memory device according to claim 1, wherein two addresses of a starting point and an ending point of said rectangular area are inputted from outside. 4. The starting point address of the rectangular area is designated by the jump function, and if there is no external designation, the final address of the entire memory area is the final address, and if external designation is made, that is the final address and the above is specified. 4. The semiconductor memory device according to claim 2, wherein a jump function returns to the specified starting point. 5. The end point address of the X system among the end points of the rectangular area is externally specified by the line reset function, and the data of the start point address of the specified rectangular area of the next line is reserved in advance. 5. The semiconductor memory device according to claim 4, wherein the semiconductor memory device is read out into a buffer. 6. Among the end point addresses, the end point address of the Y system is designated from outside by the line reset function, and in the window scan mode, the specified end point address is specified in the rectangular area set after the line access of this designated end point address is completed. 6. The semiconductor memory device according to claim 5, wherein the semiconductor memory device is reset to a starting point address. 7. The specified window scan mode can be canceled at any timing during the scan, and by specifying another jump or reset, the window scan mode can be changed to a newly set arbitrary address. Claim 2, Claim 3, Claim 4, characterized in that serial access including:
A semiconductor memory device according to claim 5 or claim 6.