JPH10163633A - Multi-layer circuit board and its manufacturing method - Google Patents

Multi-layer circuit board and its manufacturing method

Info

Publication number
JPH10163633A
JPH10163633A JP31761196A JP31761196A JPH10163633A JP H10163633 A JPH10163633 A JP H10163633A JP 31761196 A JP31761196 A JP 31761196A JP 31761196 A JP31761196 A JP 31761196A JP H10163633 A JPH10163633 A JP H10163633A
Authority
JP
Japan
Prior art keywords
circuit board
via hole
circuit
layer
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31761196A
Other languages
Japanese (ja)
Inventor
Toshiki Saito
俊樹 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denka Co Ltd
Original Assignee
Denki Kagaku Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denki Kagaku Kogyo KK filed Critical Denki Kagaku Kogyo KK
Priority to JP31761196A priority Critical patent/JPH10163633A/en
Publication of JPH10163633A publication Critical patent/JPH10163633A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a low cost substrate in good productivity, by connecting any via hole, at a multi-layer circuit board where a conductor circuit layer of 3 or more layers which is electrically connected with a via hole is provided through an insulation layer, to at least a conductor circuit in outer-most layer. SOLUTION: A recess reaching up to an insulation layer is formed at a specified position of a conductor circuit 2 with a drill, etc., then, an insulation 5 is melted by various laser light ray or chemical drilling to remove a portion from the conductor circuit 2 to a desired conductor circuit including an insulation layer, so that, generally, a column-like recess is formed on the bottom part of recess, for forming a via hole 1. For via hole's electric connection method, a conductive material coats an inner wall or bottom part or recess by plating, etc., or such conductive material as a conductive paste is filled in the recess. As a result, forming of the via hole 1 is done in a single process for higher productivity, thus a multi-layer circuit board comprising a conductor circuit of 3 or more layers in manufactured at low cost.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、3層以上の多層回
路基板とその製法に関し、バイアホールのいずれをも最
外層の導電回路層に接続されるように形成することで、
極めて生産性が高く安価な多層回路基板とその製法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board having three or more layers and a method of manufacturing the same, by forming each of the via holes so as to be connected to the outermost conductive circuit layer.
The present invention relates to an inexpensive multilayer circuit board having extremely high productivity and a method for producing the same.

【0002】[0002]

【従来の技術】近年、半導体素子のハイパワー化が進む
につれて、回路基板には一層の小型化、高密度化が求め
られてきており、導電回路が多層に積層された多層回路
基板への期待がますます強くなっている。しかしながら
従来の多層回路基板では、回路層数の増加に伴って、ス
ルーホールまたはバイアホール(以下単にバイアホール
という)の数が増加し、これらを形成するためのプロセ
ス数も増加しており、多層回路基板の生産性が著しく低
下し、この為に得られる多層回路基板も高価であるとい
う問題を抱えている。
2. Description of the Related Art In recent years, as the power of semiconductor devices has increased, the circuit board has been required to be further reduced in size and density, and a multilayer circuit board in which conductive circuits are stacked in multiple layers has been expected. Are getting stronger. However, in the conventional multilayer circuit board, as the number of circuit layers increases, the number of through holes or via holes (hereinafter simply referred to as via holes) increases, and the number of processes for forming these increases. There is a problem that the productivity of the circuit board is remarkably reduced, and the resulting multilayer circuit board is also expensive.

【0003】[0003]

【発明が解決しようとする課題】本発明の目的は、生産
性に優れ、従って安価な、3層以上の導体回路を有する
多層回路基板とその製法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-layer circuit board having three or more conductor circuits, which is excellent in productivity and therefore inexpensive, and a method of manufacturing the same.

【0004】[0004]

【課題を解決するための手段】本発明は、基板上に絶縁
層を介して3層以上の導体回路層が設けてなり、前記導
体回路層同士を電気的に接続するバイアホールが設けら
れてなる多層回路基板であって、該バイアホールのいず
れもが少なくとも最外層の導体回路に接続され設けられ
ていることを特徴とする多層回路基板であり、好ましく
は、前記基板がアルミニウム又はアルミニウム合金、若
しくは銅又は銅合金からなることを特徴とする前記の多
層回路基板である。
According to the present invention, three or more conductive circuit layers are provided on a substrate with an insulating layer interposed therebetween, and via holes for electrically connecting the conductive circuit layers are provided. A multilayer circuit board, wherein each of the via holes is provided to be connected to at least the outermost conductive circuit, preferably, the board is aluminum or an aluminum alloy, Alternatively, the multilayer circuit board is made of copper or a copper alloy.

【0005】また、本発明は、絶縁層が、酸化アルミニ
ウム、酸化珪素、窒化アルミニウム、窒化硼素、窒化珪
素のいずれか1種以上を含有するエポキシ樹脂からなる
こと、若しくは、ガラス繊維を含有するエポキシ樹脂か
らなることを特徴とする前記多層回路基板である。更
に、本発明は、バイアホールの直径が該バイアホールの
深さの1/3以上であることを特徴とする前記多層回路
基板であり、バイアホール内面が銅めっきされているこ
とを特徴とする前記多層回路基板である。
Further, according to the present invention, the insulating layer is made of an epoxy resin containing at least one of aluminum oxide, silicon oxide, aluminum nitride, boron nitride and silicon nitride, or an epoxy resin containing glass fiber. The multilayer circuit board is made of resin. Further, the present invention is the multilayer circuit board, wherein the diameter of the via hole is at least 1/3 of the depth of the via hole, wherein the inner surface of the via hole is plated with copper. The multilayer circuit board.

【0006】加えて、本発明は、基板上に絶縁層を介し
て3層以上の導体回路層が設けてなり、前記導体回路層
同士を電気的に接続するバイアホールが設けられてなる
多層回路基板の製法であって、絶縁層を介して導体回路
層を接合した後に該導体回路層より回路を形成する工程
を少なくとも2回以上経たのちに、バイアホールを形成
する工程を経ることを特徴とする多層回路基板の製法で
ある。
In addition, the present invention provides a multi-layer circuit comprising three or more conductive circuit layers provided on a substrate via an insulating layer, and via holes for electrically connecting the conductive circuit layers to each other. A method of manufacturing a substrate, wherein after a step of forming a circuit from the conductor circuit layer after joining the conductor circuit layer via an insulating layer has been performed at least twice or more, a step of forming a via hole is performed. This is a method for producing a multilayer circuit board.

【0007】[0007]

【発明の実施の形態】以下、図を用いて本発明について
詳細に説明する。図1及び図2は、いずれも本発明の多
層回路基板の一例を模した断面図であり、図1は、電気
絶縁性の基材6上に3層の導電回路2、4、7が絶縁層
3、5を介して設けられ、バイアホール1がいずれも最
外層の導電回路2に接続されている構造を有する。又、
図2は、金属板9上に3層の導電回路2、4、7が絶縁
層3、5、8を介して設けられ、バイアホール1がいず
れも最外層の導電回路2に接続されている構造を有す
る。本発明のバイアホール1は、上述のとおり、少なく
とも最外層の導電回路に接続されていれば良く、3個以
上の導電回路を接続するもの、例えば図1において導体
回路2、導体回路4、更に導体回路7のいずれをも接続
するもの、を含んでいても構わない。尚、図示していな
いが、導体回路2上には電子素子が必要に応じ搭載され
ていても良いし、ワイヤーボンディング等により他部品
と結合されていても構わない。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. 1 and 2 are cross-sectional views simulating an example of the multilayer circuit board of the present invention. FIG. 1 shows that three conductive circuits 2, 4, and 7 are insulated on an electrically insulating base material 6. The via holes 1 are provided through the layers 3 and 5, and each of the via holes 1 is connected to the outermost conductive circuit 2. or,
In FIG. 2, three conductive circuits 2, 4, and 7 are provided on a metal plate 9 via insulating layers 3, 5, and 8, and via holes 1 are all connected to the outermost conductive circuit 2. Having a structure. As described above, the via hole 1 of the present invention only needs to be connected to at least the outermost conductive circuit, and connects three or more conductive circuits, for example, the conductor circuit 2, the conductor circuit 4 in FIG. One that connects any of the conductor circuits 7 may be included. Although not shown, an electronic element may be mounted on the conductor circuit 2 as necessary, or may be connected to another component by wire bonding or the like.

【0008】本発明の構造によらない場合、バイアホー
ルの形成は下層の回路形成後その上層の導体回路を積層
する工程前に制限され、少数のバイアホール作成を数回
繰り返すことで所望数のバイアホールを形成する必要が
あった。本発明では、上記のとおり、バイアホール1の
いずれもが少なくとも最外層の導体回路2に接続されて
いることが特徴であり、この構造を採用することで、バ
イアホール形成を最終工程に集合させることが可能とな
り、従来法での工程切り替えに要する労力と時間のロス
を最小限にまで低減でき、生産性を格段に高くすること
ができるという効果を奏する。
In the case where the structure of the present invention is not used, the formation of via holes is limited after the formation of the lower layer circuit and before the step of laminating the conductor circuit of the upper layer, and a desired number of via holes are formed by repeating the formation of a small number of via holes several times. Via holes had to be formed. In the present invention, as described above, each of the via holes 1 is characterized in that it is connected to at least the outermost conductor circuit 2. By adopting this structure, the formation of the via holes is assembled in the final step. This makes it possible to reduce the labor and time loss required for the process switching according to the conventional method to a minimum, thereby achieving an effect of significantly increasing the productivity.

【0009】本発明のバイアホール1は、導体回路2か
ら所望の導体回路にまでその間の絶縁層を含めて除去
し、一般的には円柱状の凹みを形成させて得ることがで
きる。より具体的には、導電回路2の所定位置にドリル
等により絶縁層にまで達する凹みを形成した後、前記凹
みの底部に、例えばエキシマレーザー、CO2レーザ
ー、YAGレーザー等の各種レーザー光線を用いたり、
前記絶縁層に感光性樹脂を用いて露光によりパターニン
グした後にバイアホール部分を溶解することにより、あ
るいは、ケミカルドリリングにより化学的に絶縁層5を
溶解する方法などがあげられる。
The via hole 1 of the present invention can be obtained by removing the conductor circuit 2 from the conductor circuit 2 to the desired conductor circuit including the insulating layer therebetween, and forming a generally cylindrical recess. More specifically, after forming a dent reaching the insulating layer by a drill or the like at a predetermined position of the conductive circuit 2, various laser beams such as an excimer laser, a CO 2 laser, and a YAG laser are used at the bottom of the dent. ,
A method in which the insulating layer is patterned by exposing the insulating layer to light using a photosensitive resin and then dissolving the via hole portion or chemically dissolving the insulating layer 5 by chemical drilling.

【0010】前記バイアホールの電気的接続方法として
は、前記凹みの内壁及び底部にめっき等の方法で導電性
物質を被覆したり、前記凹みに導電ペースト等の導電性
物質を充填すること、或いは前記凹みの底部を利用して
ワイヤーボンディングすること等の公知の方法を用いる
ことができるが、信頼性の高い電気的接続を達成できる
ことから、銅めっきする方法が好ましい。
The via hole may be electrically connected by coating the inner wall and bottom of the recess with a conductive material by plating or the like, filling the recess with a conductive material such as a conductive paste, or A known method such as wire bonding using the bottom of the recess can be used, but a copper plating method is preferable because a highly reliable electrical connection can be achieved.

【0011】本発明において、バイアホール1の直径
は、その深さに対して1/3以上であることが好まし
い。前記バイアホール直径がその深さの1/3未満の寸
法比の場合には、銅めっきの入り込みや導電ペーストの
充填が安定して行えなくなることがあるからである。ま
た、バイアホール1の直径は0.25mm以上であるこ
とが好ましい。直径が0.25mm未満の場合には、銅
めっきの入り込みや導電ペーストの充填がやはり容易で
なくなることがあるからである。バイアホール1の直径
の上限については回路幅により制限されるので、本発明
において特に定める必要がないが、一般的には5mm程
度以下である。
In the present invention, the diameter of the via hole 1 is preferably at least one third of its depth. When the diameter of the via hole is less than 1/3 of the depth, the penetration of the copper plating or the filling of the conductive paste may not be performed stably. Also, the diameter of via hole 1 is preferably 0.25 mm or more. If the diameter is less than 0.25 mm, it may be difficult to insert copper plating or fill the conductive paste. Since the upper limit of the diameter of the via hole 1 is limited by the circuit width, it is not necessary to particularly define the upper limit in the present invention, but is generally about 5 mm or less.

【0012】本発明の基材、金属板の材質については、
特に制限はないが、バイアホール1に大電流を通電する
性格上、放熱性が良好な程好ましい。即ち、基材6とし
ては、電気絶縁性の公知の絶縁基板が用いられ、このよ
うな例として、ポリイミド樹脂、紙−フェノール樹脂、
ガラス−エポキシ樹脂等があげられる。又、金属板とし
ては、鉄、アルミニウム、銅等の金属やこれらを主成分
とする合金があげられるが、このうち銅及び銅合金、ア
ルミニウム及びアルミニウム合金は熱放散性、被加工性
に優れるという理由で好まれ、更にアルミニウム及びア
ルミニウム合金は工業上安価に供給されるという理由で
最も好ましく用いられる。尚、本発明におけるアルミニ
ウム合金とはアルミニウムにCu、Mn、Si、Mgの
うちの1種以上の元素を含有する合金をいい、銅合金と
は銅にPb、Fe、Sn、Znのうちの1種以上の元素
を含有する合金をいう。
Regarding the material of the substrate and the metal plate of the present invention,
Although there is no particular limitation, the better the heat dissipation property is, the more preferable it is to supply a large current to the via hole 1. That is, a known insulating substrate having electrical insulation properties is used as the base material 6, such as a polyimide resin, a paper-phenol resin,
Glass-epoxy resin and the like can be mentioned. Examples of the metal plate include metals such as iron, aluminum and copper and alloys containing these as main components. Among them, copper and copper alloys, aluminum and aluminum alloys are said to be excellent in heat dissipation and workability. Aluminum and aluminum alloys are most preferably used because they are industrially supplied at low cost. In the present invention, an aluminum alloy refers to an alloy containing one or more elements of Cu, Mn, Si, and Mg in aluminum, and a copper alloy refers to one of Pb, Fe, Sn, and Zn in copper. An alloy containing more than one element.

【0013】絶縁層の材質は特に制限はなく、エポキシ
樹脂、フェノール樹脂、ポリイミド樹脂、BTレジン、
テフロン樹脂などの有機樹脂が一般的に用いられる。前
記有機樹脂には、熱伝導性を高める等の目的で、いろい
ろの無機セラミックが単独若しくは複数で充填された
り、ガラス繊維などが充填される。ガラス繊維を充填し
たエポキシ樹脂は、いろいろの種類のものが市販されて
いて、多層回路基板のさまざまな用途に応じて選択する
ことができ、好ましく用いられる。また、無機セラミッ
クとしては、得られる絶縁層の電気特性、特に耐電圧性
を損なわずに熱伝導性を極めて高くすることができると
いう理由で、酸化アルミニウム、酸化珪素、窒化アルミ
ニウム、窒化珪素、窒化硼素などが好ましく用いられ
る。尚、各絶縁層は必ずしも同一種類、同一組成である
必要はないが、一般的には、同一のものが用いられる。
また、絶縁層の厚みは特に制限はなく、50μm以上が
一般的に採用されている。
The material of the insulating layer is not particularly limited, and may be epoxy resin, phenol resin, polyimide resin, BT resin,
An organic resin such as a Teflon resin is generally used. The organic resin is filled with various inorganic ceramics singly or plurally, or with glass fiber or the like for the purpose of enhancing thermal conductivity. Various types of epoxy resins filled with glass fibers are commercially available, and can be selected according to various uses of the multilayer circuit board, and are preferably used. Further, as the inorganic ceramic, aluminum oxide, silicon oxide, aluminum nitride, silicon nitride, nitrided nitride, or the like can be used because the thermal conductivity can be extremely increased without impairing the electrical characteristics of the obtained insulating layer, particularly, withstand voltage. Boron or the like is preferably used. The insulating layers do not necessarily have to be the same type and have the same composition, but generally, the same layer is used.
The thickness of the insulating layer is not particularly limited, and is generally 50 μm or more.

【0014】導体回路2、4、7の材質には、銅、アル
ミニウム、ニッケル、鉄、錫、銀、チタニウムのいずれ
か、または、これらの金属を2種類以上含む合金、及び
それぞれの金属或いは合金を使用したクラッド箔等が用
いることができる。また、この時の箔の製造方法は電解
法でも圧延法で作製したものでもよく、箔上にはNiめ
っき、Ni+Auめっき、はんだめっきなどの金属めっ
きがほどこされていてもかまわない。尚、各導体回路は
必ずしも同一材質、構成とする必要はないが、一般的に
は同一材質を用いる。又、導体回路2、4、7の厚みに
ついても、特に制限はなく、一般的には500μm以下
が用いられる。
The material of the conductor circuits 2, 4, and 7 may be any of copper, aluminum, nickel, iron, tin, silver, and titanium, an alloy containing two or more of these metals, and each metal or alloy. Can be used. At this time, the foil may be produced by an electrolytic method or a rolling method, and the foil may be plated with a metal such as Ni plating, Ni + Au plating, or solder plating. It should be noted that the conductor circuits need not necessarily be made of the same material and configuration, but generally the same material is used. The thickness of the conductor circuits 2, 4, and 7 is also not particularly limited, and is generally 500 μm or less.

【0015】本発明の多層回路基板は、従来から公知の
方法を組み合わせてバイアホールが形成されていない多
層回路基板を得て、これにバイアホールを形成すること
で得ることができる。前記バイアホールが形成されてい
ない多層回路基板を得る公知の方法の組み合わせとして
は、例えば、(1)金属板の少なくとも一主面上に絶縁層
を介して金属箔を接合し該金属箔をエッチング等の方法
で加工して回路を形成し金属ベース回路基板を得て、そ
の上に絶縁層を介して金属箔を接合し回路を形成するこ
とを2回以上繰り返してゆく方法、(2)少なくとも1層
以上の導体回路を有する絶縁基板を用い、前記導体回路
の少なくとも一方の上に、絶縁層を介して金属箔を接合
し回路を形成することを少なくとも1回以上繰り返す方
法、(3)金属板の少なくとも一主面上に絶縁層を介して
導体回路を設けた金属ベース回路基板上に、絶縁層を介
して、少なくとも1層以上の導体回路を両面に有する絶
縁基板を接合する方法、などがあげられ、更に前記(1)
〜(3)の方法を組み合わる方法があげられる。又、金属
箔を接合して後回路とする方法に換えて、予め回路形成
された金属箔を接合する方法によっても構わない。これ
らの方法のなかで、本発明者の検討によれば、金属ベー
ス回路基板又は絶縁基板を用いて該基板上に、絶縁層を
介して導体回路を接合し該絶縁層を硬化した後に回路を
形成する工程を2回以上経た後、バイアホールを形成す
る方法が、絶縁性が良好でバイアホール部での電気接続
不良等が少ない多層回路基板を安定して、生産性高く得
ることができることから、好ましい方法である。
The multilayer circuit board of the present invention can be obtained by obtaining a multilayer circuit board without via holes formed by combining conventionally known methods and forming via holes in the multilayer circuit board. As a combination of known methods for obtaining a multilayer circuit board in which the via hole is not formed, for example, (1) bonding a metal foil via an insulating layer on at least one main surface of a metal plate and etching the metal foil A method in which a circuit is formed by processing such as a method to obtain a metal-based circuit board, and a circuit is formed by joining a metal foil via an insulating layer on the circuit board twice or more, (2) at least A method of using an insulating substrate having one or more layers of conductive circuits, and repeating at least one or more times forming a circuit by bonding a metal foil on at least one of the conductive circuits via an insulating layer; A method of bonding an insulating substrate having at least one or more conductive circuits on both sides thereof via an insulating layer on a metal-based circuit board having a conductive circuit provided on at least one main surface of the plate via an insulating layer, And more Serial (1)
To (3). Further, instead of the method of joining metal foils to form a post-circuit, a method of joining metal foils on which circuits are formed in advance may be used. Among these methods, according to the study of the present inventor, according to the study of a metal-based circuit board or an insulating substrate, a conductor circuit is bonded on the substrate via an insulating layer, and after the insulating layer is cured, the circuit is formed. The method of forming a via hole after performing the forming step two or more times is because a method of forming a via hole can stably obtain a multi-layer circuit board with good insulation properties and few electric connection failures at the via hole portion and with high productivity. This is the preferred method.

【0016】以下、実施例に基づき、本発明をより一層
詳細に説明する。
Hereinafter, the present invention will be described in more detail based on examples.

【実施例】【Example】

【0017】〔実施例1〕銅箔厚が35μm、基板厚が
1.6mmのCEM−1(松下電工製;R1790Y)
の銅箔上に所定の回路を形成した後に、回路側の面上に
厚さ0.15mmのエポキシ系プリプレグ(松下電工
製;R1661)と厚さ35μmの電解銅箔を順次積層
し、熱プレスによりプレスした。この外層側の銅箔上に
所定の回路を形成した後に、回路側の面上に厚さ0.1
5mmのエポキシ系プリプレグ(松下電工製;R166
1)と厚さ35μmの電解銅箔を順次積層し、熱プレス
によりプレスした後、最外層側の銅箔上に所定の回路を
形成した。前記基板の最外層回路側からドリルによりφ
0.1mmの凹み開け、銅めっきにより厚さ20μmの
バイアホールを形成し、最外層回路と各内層回路間を電
気的に接続した。この多層回路基板について、バイアホ
ールに対する銅めっきの充填性、及び生産性を以下に示
す方法で測定したが、結果は表1に記載したように良好
であった。
Example 1 CEM-1 (R1790Y, manufactured by Matsushita Electric Works) having a copper foil thickness of 35 μm and a substrate thickness of 1.6 mm.
After a predetermined circuit is formed on the copper foil of No. 1, an epoxy-based prepreg (R1661 manufactured by Matsushita Electric Works) having a thickness of 0.15 mm and an electrolytic copper foil having a thickness of 35 μm are sequentially laminated on the circuit side surface, and hot pressing is performed. Pressed by After a predetermined circuit is formed on the copper foil on the outer layer side, a thickness of 0.1
5mm epoxy prepreg (Matsushita Electric Works; R166)
1) and an electrolytic copper foil having a thickness of 35 μm were sequentially laminated, pressed by hot pressing, and then a predetermined circuit was formed on the outermost copper foil. Drill from the outermost circuit side of the board by φ
A 0.1 mm dent was formed, and a via hole having a thickness of 20 μm was formed by copper plating to electrically connect the outermost layer circuit and each inner layer circuit. With respect to this multilayer circuit board, the filling property of copper plating into the via holes and the productivity were measured by the following methods, and the results were good as described in Table 1.

【0018】<銅めっきの充填性の評価方法>バイアホ
ールにより接続された(1)導体回路間の電気的接続の
有無、(2)バイアホール断面を研磨の後観察したとき
の、導体部の欠損の有無について、(1)及び(2)が
ともに良好な場合は○、(1)のみ良好で(2)が不良
の場合は△、(1)及び(2)のいづれもが不良の場合
は×と評価した。
<Evaluation Method for Filling of Copper Plating> (1) The presence / absence of electrical connection between conductor circuits connected by via holes, and (2) the conductor section when the cross section of via holes was observed after polishing. Regarding the presence / absence of a defect, ○ when both (1) and (2) are good, △ when only (1) is good and (2) is bad, and when both (1) and (2) are bad Was evaluated as x.

【0019】<生産性の評価方法>各々の製法で名刺サ
イズ(90mm×50mm)の基板10,000枚を製
造するのに要した時間で評価した。
<Evaluation Method of Productivity> Evaluation was made based on the time required to manufacture 10,000 substrates of business card size (90 mm × 50 mm) in each of the manufacturing methods.

【0020】[0020]

【表1】 [Table 1]

【0021】〔実施例2〕銅箔厚が35μm、基板厚が
1.6mmのCEM−1(松下電工製;R1790Y)
の銅箔上に所定の回路を形成した後に、回路側の面上に
厚さ0.15mmのエポキシ系プリプレグ(松下電工
製;R1661)と厚さ35μmの電解銅箔を順次積層
し、熱プレスによりプレスした。この外層側の銅箔上に
所定の回路を形成した後に、回路側の面上に再度厚さ
0.15mmのエポキシ系プリプレグ(松下電工製;R
1661)と厚さ35μmの電解銅箔を順次積層し、熱
プレスによりプレスした後、最外層側の銅箔上に所定の
回路を形成した。この基板の最外層回路側からYAGレ
ーザーによりφ0.1mmの凹みを開け、銅めっきによ
り厚さ20μmのバイアホールを形成し、最外層回路と
各内層回路間を電気的に接続した。この多層回路基板に
ついて、バイアホールに対する銅めっきの充填性、及び
生産性を実施例1に記した方法で測定したが、結果は表
1に記載したように良好であった。
Example 2 CEM-1 (Matsushita Electric Works; R1790Y) having a copper foil thickness of 35 μm and a substrate thickness of 1.6 mm
After a predetermined circuit is formed on the copper foil of No. 1, an epoxy-based prepreg (R1661 manufactured by Matsushita Electric Works) having a thickness of 0.15 mm and an electrolytic copper foil having a thickness of 35 μm are sequentially laminated on the circuit side surface, and hot pressing is performed. Pressed by After a predetermined circuit is formed on the copper foil on the outer layer side, an epoxy-based prepreg having a thickness of 0.15 mm (manufactured by Matsushita Electric Works; R
1661) and an electrolytic copper foil having a thickness of 35 μm were sequentially laminated and pressed by hot pressing, and then a predetermined circuit was formed on the outermost copper foil. A recess of φ0.1 mm was opened from the outermost layer circuit side of this substrate by a YAG laser, a via hole having a thickness of 20 μm was formed by copper plating, and the outermost layer circuit and each inner layer circuit were electrically connected. With respect to this multilayer circuit board, the filling property of the copper plating into the via holes and the productivity were measured by the method described in Example 1, and the results were good as described in Table 1.

【0022】〔実施例3〕板厚が1.5mmのアルミ板
上に、厚さ0.15mmのエポキシ系プリプレグ(松下
電工製;R1661)と厚さ35μmの電解銅箔を順次
積層し、熱プレスした後に所定の回路を形成し、再度回
路側の面上に厚さ0.15mmのエポキシ系プリプレグ
(松下電工製;R1661)と厚さ35μmの電解銅箔
を順次積層し、熱プレスによりプレスした。この外層側
の銅箔上に所定の回路を形成した後に、更に厚さ0.1
5mmのエポキシ系プリプレグ(松下電工製;R166
1)と厚さ35μmの電解銅箔を順次積層し、熱プレス
によりプレスした後、最外層側の銅箔上に所定の回路を
形成した。この基板の最外層回路側からYAGレーザー
によりφ0.1mmの凹み開け、銅めっきにより厚さ2
0μmのバイアホールを形成し、最外層回路と各内層回
路間を電気的に接続した。この多層回路基板について、
バイアホールに対する銅めっきの充填性、及び生産性を
評価したが、結果は表1に記載したように良好であっ
た。
Example 3 An epoxy prepreg having a thickness of 0.15 mm (R1661 manufactured by Matsushita Electric Works) and an electrolytic copper foil having a thickness of 35 μm were sequentially laminated on an aluminum plate having a thickness of 1.5 mm. After pressing, a predetermined circuit is formed. Again, an epoxy-based prepreg (Matsushita Electric Works; R1661) having a thickness of 0.15 mm and electrolytic copper foil having a thickness of 35 μm are sequentially laminated on the circuit-side surface, and pressed by hot pressing. did. After forming a predetermined circuit on the copper foil on the outer layer side, a further 0.1
5mm epoxy prepreg (Matsushita Electric Works; R166)
1) and an electrolytic copper foil having a thickness of 35 μm were sequentially laminated, pressed by hot pressing, and then a predetermined circuit was formed on the outermost copper foil. From the outermost layer circuit side of this substrate, a dent of φ0.1 mm is opened by a YAG laser, and a thickness of 2 mm is formed by copper plating.
Via holes of 0 μm were formed to electrically connect the outermost layer circuit and each inner layer circuit. About this multilayer circuit board,
The filling properties and productivity of the copper plating into the via holes were evaluated, and the results were good as described in Table 1.

【0023】〔実施例4〕銅箔厚が35μm、基板厚が
1.6mmのCEM−1(松下電工製;R1790Y)
の銅箔上に所定の回路を形成した後に、回路側の面上に
厚さ0.15mmのエポキシ系プリプレグ(松下電工
製;R1661)と厚さ35μmの電解銅箔を順次積層
し、熱プレスによりプレスした。この外層側の銅箔上に
所定の回路を形成した後に、回路側の面上に再度厚さ
0.15mmのエポキシ系プリプレグ(松下電工製;R
1661)と厚さ35μmの電解銅箔を順次積層し、熱
プレスによりプレスした後、最外層側の銅箔上に所定の
回路を形成した。この基板の最外層回路側からYAGレ
ーザーによりφ0.1mmの孔を開け、開口部に銅ペー
スト(アサヒ化研(株)製;ACP−052)を印刷法
で注入することでバイアホールを形成し、最外層回路と
各内層回路間を電気的に接続した。この多層回路基板に
ついて、バイアホールに対する銅めっきの充填性、及び
生産性を評価したが、結果は表1に記載したように良好
であった。
Example 4 CEM-1 having a copper foil thickness of 35 μm and a substrate thickness of 1.6 mm (R1790Y, manufactured by Matsushita Electric Works)
After a predetermined circuit is formed on the copper foil of No. 1, an epoxy-based prepreg (R1661 manufactured by Matsushita Electric Works) having a thickness of 0.15 mm and an electrolytic copper foil having a thickness of 35 μm are sequentially laminated on the circuit side surface, and hot pressing is performed. Pressed by After a predetermined circuit is formed on the copper foil on the outer layer side, an epoxy-based prepreg having a thickness of 0.15 mm (manufactured by Matsushita Electric Works; R
1661) and an electrolytic copper foil having a thickness of 35 μm were sequentially laminated and pressed by hot pressing, and then a predetermined circuit was formed on the outermost copper foil. A hole having a diameter of 0.1 mm is made from the outermost layer circuit side of the substrate by a YAG laser, and a via hole is formed by injecting a copper paste (manufactured by Asahi Kaken Corporation; ACP-052) into the opening by a printing method. The outermost layer circuit and each inner layer circuit were electrically connected. With respect to this multilayer circuit board, the filling property of the copper plating into the via holes and the productivity were evaluated. The results were good as described in Table 1.

【0024】〔実施例5〕銅箔厚が35μm、基板厚が
1.6mmのCEM−1(松下電工製;R1790Y)
の銅箔上に所定の回路を形成した後に、回路側の面上に
厚さ0.15mmのエポキシ系プリプレグ(松下電工
製;R1661)と厚さ35μmの電解銅箔を順次積層
し、熱プレスによりプレスし、この外層側の銅箔上に所
定の回路を形成した。更に、回路側の面上に再度厚さ
0.15mmのエポキシ系プリプレグ(松下電工製;R
1661)と厚さ35μmの電解銅箔を順次積層し、熱
プレスによりプレスした後、最外層側の銅箔上に所定の
回路を形成した。この基板の最外層回路側からYAGレ
ーザーにより所定の箇所にφ0.08mmの孔を開け、
銅めっきにより厚さ20μmのバイアホールを形成し、
多層回路基板を得た。この多層回路基板について、バイ
アホールに対する銅めっきの充填性、及び生産性を評価
したが、結果は表1に記載したように、良好であった。
Example 5 CEM-1 having a copper foil thickness of 35 μm and a substrate thickness of 1.6 mm (R1790Y, manufactured by Matsushita Electric Works)
After a predetermined circuit is formed on the copper foil of No. 1, an epoxy-based prepreg (R1661 manufactured by Matsushita Electric Works) having a thickness of 0.15 mm and an electrolytic copper foil having a thickness of 35 μm are sequentially laminated on the circuit side surface, and hot pressing is performed. To form a predetermined circuit on the copper foil on the outer layer side. Further, an epoxy-based prepreg having a thickness of 0.15 mm (Matsushita Electric Works; R
1661) and an electrolytic copper foil having a thickness of 35 μm were sequentially laminated and pressed by hot pressing, and then a predetermined circuit was formed on the outermost copper foil. From the outermost circuit side of this substrate, a hole of φ0.08 mm was made at a predetermined position with a YAG laser,
A via hole having a thickness of 20 μm is formed by copper plating,
A multilayer circuit board was obtained. With respect to this multilayer circuit board, the filling property of copper plating into via holes and the productivity were evaluated. The results were good as described in Table 1.

【0025】〔実施例6〕銅箔厚が35μm、基板厚が
1.6mmのCEM−1(松下電工製;R1790Y)
の銅箔上に所定の回路を形成した後に、回路側の面上に
厚さ0.15mmのエポキシ系プリプレグ(松下電工
製;R1661)と厚さ35μmの電解銅箔を順次積層
し、熱プレスによりプレスした。この外層側の銅箔上に
所定の回路を形成した後に、回路面上に再度厚さ0.1
5mmのエポキシ系プリプレグ(松下電工製;R166
1)と厚さ35μmの電解銅箔を順次積層し、熱プレス
によりプレスした後、最外層側の銅箔上に所定の回路を
形成した。この基板の最外層回路側からYAGレーザー
によりφ0.08mmの凹みを開け、銅めっきにより厚
さ20μmのバイアホールを形成し、最外層回路と各内
層回路間を電気的に接続した。この多層回路基板につい
て、バイアホールに対する銅めっきの充填性、及び生産
性を評価したところ、結果は表1に記載したように、銅
めっきの充填性に於いてやや難があったものの良好であ
った。
Example 6 CEM-1 (R1790Y, manufactured by Matsushita Electric Works) having a copper foil thickness of 35 μm and a substrate thickness of 1.6 mm.
After a predetermined circuit is formed on the copper foil of No. 1, an epoxy-based prepreg (R1661 manufactured by Matsushita Electric Works) having a thickness of 0.15 mm and an electrolytic copper foil having a thickness of 35 μm are sequentially laminated on the circuit side surface, and hot pressing is performed. Pressed by After forming a predetermined circuit on the copper foil on the outer layer side, a thickness of 0.1
5mm epoxy prepreg (Matsushita Electric Works; R166)
1) and an electrolytic copper foil having a thickness of 35 μm were sequentially laminated, pressed by hot pressing, and then a predetermined circuit was formed on the outermost copper foil. A recess of φ0.08 mm was opened from the outermost layer circuit side of the substrate with a YAG laser, and a via hole having a thickness of 20 μm was formed by copper plating to electrically connect the outermost layer circuit and each inner layer circuit. With respect to this multilayer circuit board, the filling property of the copper plating into the via hole and the productivity were evaluated. As shown in Table 1, the result was good although the filling property of the copper plating was slightly difficult. Was.

【0026】〔実施例7〕510mm×510mm×
1.5mmのアルミニウム板上に、窒化硼素(電気化学
工業(株)製;GP)を53体積%含有するビスフェノ
ールA型エポキシ樹脂(油化シェル(株)製;エピコー
ト828)を絶縁接着剤として用い、アミン系硬化剤を
加え、150μmの厚みとなるように塗布し、厚さが3
5μmの銅箔をラミネート法により貼り合わせた。次
に、銅箔をエッチングしてシールドパターンを形成した
後に、銅箔側の面上に前記絶縁接着剤にアミン系硬化剤
を加え、150μmの厚さとなるように塗布し、厚さが
35μmの銅箔をラミネート法により貼り合わせ、加熱
硬化した。この作業を再度繰り返し、得られた基板の最
外層回路側からYAGレーザーによりφ0.1mmの凹
みを開け、銅めっきにより厚さ20μmのバイアホール
を形成し、最外層回路と各内層回路間を電気的に接続し
た。上記操作で得られた多層回路基板について、バイア
ホールに対する銅めっきの充填性、及び生産性を評価し
たが、結果は表1に記載したとおり良好であった。
Example 7 510 mm × 510 mm ×
A bisphenol A type epoxy resin (manufactured by Yuka Shell Co., Ltd .; Epicoat 828) containing 53% by volume of boron nitride (manufactured by Denki Kagaku Kogyo KK; GP) was used as an insulating adhesive on a 1.5 mm aluminum plate. Add an amine-based curing agent and apply to a thickness of 150 μm.
A 5 μm copper foil was bonded by a lamination method. Next, after etching the copper foil to form a shield pattern, an amine-based curing agent was added to the insulating adhesive on the surface on the copper foil side, and applied so as to have a thickness of 150 μm. A copper foil was laminated by a lamination method and cured by heating. This operation was repeated again, a hole of φ0.1 mm was opened from the outermost circuit side of the obtained substrate with a YAG laser, a 20 μm-thick via hole was formed by copper plating, and an electric connection was established between the outermost layer circuit and each inner layer circuit. Connected. With respect to the multilayer circuit board obtained by the above operation, the filling property of the copper plating into the via holes and the productivity were evaluated, and the results were good as described in Table 1.

【0027】〔比較例1及び比較例2〕銅箔厚が35μ
m、基板厚が1.6mmのCEM−1(松下電工製;R
1790Y)の銅箔上に所定の回路を形成した後に、回
路面上に厚さ0.15mmのエポキシ系プリプレグ(松
下電工製;R1661)と厚さ35μmの電解銅箔を順
次積層し、熱プレスによりプレスした。この外層側の銅
箔上に所定の回路を形成した後に、YAGレーザーによ
り所定の箇所にφ0.10mmの孔を開け、銅めっきに
より厚さ20μmのバイアホールを形成した。その後に
回路側の面上に再度厚さ0.15mmのエポキシ系プリ
プレグ(松下電工製;R1661)と厚さ35μmの電
解銅箔を順次積層し、熱プレスによりプレスした後、最
外層側の銅箔上に所定の回路を形成した。この基板の最
外層回路側からYAGレーザーにより所定の箇所にφ
0.1mm(比較例1)及びφ0.04mm(比較例
2)の孔を開け、銅めっきにより厚さ20μmのバイア
ホールを形成し、多層回路基板(図3参照)を得た。こ
の多層回路基板について、バイアホールに対する銅めっ
きの充填性、及び生産性を以下を評価したが、結果は表
1に記載したように、生産性に於いて芳しくなかった。
[Comparative Examples 1 and 2] The copper foil thickness was 35 μm.
m, CEM-1 having a substrate thickness of 1.6 mm (manufactured by Matsushita Electric Works; R
After a predetermined circuit is formed on the copper foil of 1790Y), an epoxy-based prepreg (R1661 manufactured by Matsushita Electric Works) having a thickness of 0.15 mm and an electrolytic copper foil having a thickness of 35 μm are sequentially laminated on the circuit surface, and hot pressed. Pressed by After a predetermined circuit was formed on the copper foil on the outer layer side, a hole having a diameter of 0.10 mm was formed at a predetermined position by a YAG laser, and a via hole having a thickness of 20 μm was formed by copper plating. Thereafter, an epoxy-based prepreg (R1661 manufactured by Matsushita Electric Works) having a thickness of 0.15 mm and an electrolytic copper foil having a thickness of 35 μm are sequentially laminated again on the circuit side surface, and pressed by a hot press. A predetermined circuit was formed on the foil. From the outermost layer circuit side of this substrate,
Holes of 0.1 mm (Comparative Example 1) and 0.04 mm (Comparative Example 2) were formed, and via holes having a thickness of 20 μm were formed by copper plating to obtain a multilayer circuit board (see FIG. 3). With respect to this multilayer circuit board, the filling property of the copper plating into the via hole and the productivity were evaluated as follows. As shown in Table 1, the results were not satisfactory in the productivity.

【0028】[0028]

【発明の効果】本発明によれば、バイアホールのいずれ
もが少なくとも最外層の導電回路に接続された構造を有
するので、バイアホールを形成する工程を従来と異なり
1工程とすることが出来るので、生産性高く得ることが
でき、その結果、3層以上の導体回路を有する多層回路
基板が安価に得ることができ産業上有益である。
According to the present invention, since each of the via holes has a structure connected to at least the outermost conductive circuit, the step of forming the via hole can be reduced to one step, unlike the related art. As a result, a multilayer circuit board having three or more conductor circuits can be obtained at low cost, which is industrially beneficial.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の多層回路基板の一例を示す断面図。FIG. 1 is a sectional view showing an example of a multilayer circuit board of the present invention.

【図2】 本発明の多層回路基板の他の一例を示す断面
図。
FIG. 2 is a sectional view showing another example of the multilayer circuit board of the present invention.

【図3】 公知の多層回路基板の断面図。FIG. 3 is a cross-sectional view of a known multilayer circuit board.

【符号の説明】[Explanation of symbols]

1 バイアホール 2 導体回路 3 絶縁層 4 導体回路 5 絶縁層 6 基材 7 導体回路 8 絶縁層 9 金属板 DESCRIPTION OF SYMBOLS 1 Via hole 2 Conductor circuit 3 Insulating layer 4 Conductor circuit 5 Insulating layer 6 Base material 7 Conductor circuit 8 Insulating layer 9 Metal plate

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 基板上に絶縁層を介して3層以上の導体
回路層が設けてなり、前記導体回路層同士を電気的に接
続するバイアホールが設けられてなる多層回路基板であ
って、該バイアホールのいずれもが少なくとも最外層の
導体回路に接続され設けられていることを特徴とする多
層回路基板。
1. A multilayer circuit board comprising: a substrate; and three or more conductive circuit layers provided on the substrate with an insulating layer interposed therebetween, and via holes for electrically connecting the conductive circuit layers to each other. A multilayer circuit board, wherein each of the via holes is provided so as to be connected to at least an outermost conductor circuit.
【請求項2】 前記基板がアルミニウム又はアルミニウ
ム合金、若しくは銅又は銅合金からなることを特徴とす
る請求項1記載の多層回路基板。
2. The multilayer circuit board according to claim 1, wherein the board is made of aluminum, an aluminum alloy, copper, or a copper alloy.
【請求項3】 前記絶縁層が、酸化アルミニウム、酸化
珪素、窒化アルミニウム、窒化硼素、窒化珪素のいずれ
か1種以上を含有するエポキシ樹脂からなることを特徴
とする請求項2記載の多層回路基板。
3. The multilayer circuit board according to claim 2, wherein said insulating layer is made of an epoxy resin containing at least one of aluminum oxide, silicon oxide, aluminum nitride, boron nitride, and silicon nitride. .
【請求項4】 前記絶縁層がガラス繊維を含有するエポ
キシ樹脂からなることを特徴とする請求項1又は請求項
2記載の多層回路基板。
4. The multilayer circuit board according to claim 1, wherein said insulating layer is made of an epoxy resin containing glass fiber.
【請求項5】 バイアホールの直径が該バイアホールの
深さの1/3以上であることを特徴とする請求項1、請
求項2、請求項3又は請求項4記載の多層回路基板。
5. The multilayer circuit board according to claim 1, wherein the diameter of the via hole is at least 1/3 of the depth of the via hole.
【請求項6】 バイアホールの直径が該バイアホールの
深さの1/3以上であり、しかも、該バイアホール内面
が銅めっきされていることを特徴とする請求項1、請求
項2、請求項3又は請求項4記載の多層回路基板。
6. The via hole according to claim 1, wherein the diameter of the via hole is at least 1/3 of the depth of the via hole, and the inner surface of the via hole is plated with copper. The multilayer circuit board according to claim 3 or 4.
【請求項7】 基板上に絶縁層を介して3層以上の導体
回路層が設けてなり、前記導体回路層同士を電気的に接
続するバイアホールが設けられてなる多層回路基板の製
法であって、絶縁層を介して導体回路層を接合した後に
該導体回路層より回路を形成する工程を少なくとも2回
以上経たのちに、バイアホールを形成する工程を経るこ
とを特徴とする多層回路基板の製法。
7. A method for producing a multilayer circuit board, comprising three or more conductive circuit layers provided on a substrate via an insulating layer, and via holes for electrically connecting the conductive circuit layers to each other. A step of forming a via hole after at least twice a step of forming a circuit from the conductive circuit layer after joining the conductive circuit layer via an insulating layer, and a step of forming a via hole. Manufacturing method.
JP31761196A 1996-11-28 1996-11-28 Multi-layer circuit board and its manufacturing method Pending JPH10163633A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31761196A JPH10163633A (en) 1996-11-28 1996-11-28 Multi-layer circuit board and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31761196A JPH10163633A (en) 1996-11-28 1996-11-28 Multi-layer circuit board and its manufacturing method

Publications (1)

Publication Number Publication Date
JPH10163633A true JPH10163633A (en) 1998-06-19

Family

ID=18090130

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31761196A Pending JPH10163633A (en) 1996-11-28 1996-11-28 Multi-layer circuit board and its manufacturing method

Country Status (1)

Country Link
JP (1) JPH10163633A (en)

Similar Documents

Publication Publication Date Title
JP4767269B2 (en) Method for manufacturing printed circuit board
US5329695A (en) Method of manufacturing a multilayer circuit board
US7681310B2 (en) Method for fabricating double-sided wiring board
US6335076B1 (en) Multi-layer wiring board and method for manufacturing the same
JPH11126978A (en) Multilayered wiring board
TW200524502A (en) Method of providing printed circuit board with conductive holes and board resulting therefrom
JPH1145955A (en) Device built-in multilayered printed circuit board and its manufacture
JP2003031952A (en) Core substrate and multilayer circuit board using the same
JP2007281480A (en) Printed-circuit board using bump, and its manufacturing method
KR100747022B1 (en) Imbedded circuit board and fabricating method therefore
JPH10190232A (en) Multilayer interconnection board and its manufacture
JPH1117341A (en) Frinted multilayer wiring board
JP2005039233A (en) Substrate having via hole and its producing process
JP4582938B2 (en) Insulating sheet manufacturing method and wiring board manufacturing method
JP2003101219A (en) Circuit board and its manufacturing method
CN105191512B (en) Printed circuit board and manufacturing methods
JPH07115280A (en) Multilayer printed wiring board and its manufacture
JP2006128226A (en) Multilayer printed circuit board with built-in electric part, and its manufacturing method
JP2000223836A (en) Multilayer wiring board and its manufacture
JPH10163633A (en) Multi-layer circuit board and its manufacturing method
JP2009141297A (en) Multilayer wiring board and its manufacturing method
JP3955799B2 (en) Wiring board manufacturing method
WO2000046877A2 (en) Printed circuit boards with solid interconnect and method of producing the same
JP2003324280A (en) Manufacturing method of printed circuit board
JPH11289165A (en) Multilayer wiring board and method for manufacturing the same

Legal Events

Date Code Title Description
A977 Report on retrieval

Effective date: 20051018

Free format text: JAPANESE INTERMEDIATE CODE: A971007

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20051108

A521 Written amendment

Effective date: 20051220

Free format text: JAPANESE INTERMEDIATE CODE: A523

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20060117