JPH10154813A - Manufacture of thin film transistor and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form an LDD region and a diffusion layer region in a self-aligned manner without increasing the number of processes, by a method wherein, in a heat treatment process, an LDD region is formed between the source region and the channel region of a silicon thin film and between the source region and a drain region. SOLUTION: Implanted impurities are activated in a heat treatment process, and as the diffusion speed of P-ion molecule, having small molecular weight, is higher than the diffusion speed of As ions with large molecular weight. P-ion molecule only is diffused into the channel, and an LDD region 13b and an As-ion diffusion region 13c are formed by P-ions. Accordingly, an LDD region 13b is formed between the source region and the channel region of the diffusion region 13 and between the drain region and the channel region of the diffusion region 13c. As a result, a region having different density can be formed in a silicon thin film, and an LDD region and a diffusion layer region can be formed in a self-aligned manner without increasing the number of processes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor having a lightly doped drain (LDD) used in a liquid crystal display device.

[0002]

2. Description of the Related Art In order to manufacture a transistor having a good OFF current characteristic, an LDD structure has conventionally been adopted.
The LDD structure is a structure in which a low-concentration region is provided around a diffusion layer to reduce the concentration gradient and relax the source and drain voltages.

Hereinafter, an example of a conventional LDD structure will be described.
This will be described with reference to the drawings. 5A to 5F show cross-sectional views of an example of a conventional thin film transistor having an LDD structure in the order of manufacturing steps.

First, as shown in FIG. 5A, an amorphous silicon thin film 12 is formed on a glass substrate 10 via a coating layer 11 made of SiO ₂ . Amorphous silicon thin film 1
2 is formed by a plasma CVD method. Next, FIG.
As shown in (a) and (b), the amorphous silicon thin film 1
2 is irradiated with an excimer laser beam in the direction of arrow 28 to melt and crystallize the amorphous silicon thin film 12, thereby forming a polycrystalline silicon thin film 13.

Next, as shown in FIG. 5C, the polycrystalline silicon thin film 13 is processed into an island shape, and a gate insulating film 14 made of a silicon oxide thin film is formed. Further, a gate electrode 15 is formed on the gate insulating film 14.

After the formation of the gate electrode 15, FIGS.
As shown in (d), the first impurity implantation is performed in the direction of arrow 28 by ion implantation using the gate electrode 15 as a mask to form the LDD region 13b. In the first impurity implantation, phosphorus (P) ions are implanted at an acceleration voltage of 80 kV and a dose of 1 × 10 4.
Inject at ¹³ cm ^-2 . After the first impurity implantation, FIG.
As shown in (d), after forming an LDD region mask with the photoresist 16, a second impurity implantation is performed, and a high-concentration impurity implantation region (hereinafter referred to as “diffusion layer region”) 13.
Form c. In the second impurity implantation, phosphorus (P) ions are implanted at an acceleration voltage of 80 kV and a dose of 1 × 10 ¹⁵ cm ⁻² .

After the second impurity implantation, the photoresist 16
Is removed, and the implanted impurity is activated. Next, as shown in FIG. 5E, an interlayer insulating film 17 made of silicon oxide is formed. Finally, as shown in FIG. 5F, a contact hole is opened on the source and drain regions, and a source electrode 18 and a drain electrode 19 are formed to complete a thin film transistor.

[0008]

However, in the conventional method of manufacturing a thin film transistor as described above, the LDD
Fabrication of the structure required two high and low doping steps. Further, a separate photo step was required to form a mask. For this reason, LD
As compared with a thin film transistor not using a D structure, there is a problem that the number of steps increases and the manufacturing process becomes complicated.

If the number of steps increases and the manufacturing process becomes complicated, it becomes difficult to apply a thin film transistor having an LDD structure to an active matrix array used in a liquid crystal display device or the like. .

The present invention solves the above-mentioned problems and provides a method of manufacturing a thin film transistor capable of forming an LDD region and a diffusion layer region in a self-aligned manner without increasing the number of steps, and a liquid crystal using the method. It is an object to provide an active matrix array for a display device and a liquid crystal display device.

[0011]

In order to achieve the above object, a method of manufacturing a thin film transistor according to the present invention comprises the steps of: depositing an amorphous silicon thin film on a glass substrate; A crystallization step of crystallizing the thin film with a laser, a step of depositing a gate insulating film on the silicon thin film, and a step of depositing and patterning a gate electrode on the gate insulating film. A step of implanting two different impurities into the silicon thin film through the gate insulating film and the gate electrode, and a heat treatment step of heat-treating the silicon thin film after the implantation of the impurities. Between the source region and the channel region and between the drain region and the channel region of the silicon thin film Between, and forming an LDD region.

In the method of manufacturing a thin film transistor, instead of performing the crystallization in the crystallization step,
In the heat treatment step, the crystallization is preferably performed also as a heat treatment.

In the method of manufacturing a thin film transistor, it is preferable to use an ion doping method for the impurity implantation.

In the method of manufacturing a thin film transistor, it is preferable to use phosphorus (P) and arsenic (As) as the two different impurities.

In the method of manufacturing a thin film transistor, the heat treatment is preferably performed by laser annealing using argon or excimer laser.

In the method of manufacturing a thin film transistor, it is preferable that the heat treatment is performed by laser annealing from the back surface of the glass substrate.

According to the method of manufacturing a thin film transistor as described above, different atoms in the silicon thin film have different diffusion rates due to external heat treatment in the heat treatment step. That is, a substance having a large molecular weight has a lower diffusion rate than a substance having a small molecular weight. Therefore, regions having different concentrations can be formed in the silicon thin film, and the LDD region and the diffusion layer region can be formed in a self-aligned manner without increasing the number of steps.

Next, an active matrix array for a liquid crystal display device according to the present invention is an active matrix array for a liquid crystal display device having thin film transistors, wherein at least one of the thin film transistors for driving a pixel electrode is made of amorphous silicon. A silicon thin film deposition step of depositing a thin film on a glass substrate, a crystallization step of crystallizing the amorphous silicon thin film with a laser, and a gate insulation film deposition step of depositing a gate insulation film on the silicon thin film. Depositing and patterning a gate electrode on the gate insulating film, patterning a gate electrode for patterning; implanting two different impurities into the silicon thin film through the gate insulating film and the gate electrode; After the impurity implantation, the silicon thin film is heated. An LDD structure formed by a method of manufacturing a thin film transistor for forming an LDD region between a source region and a channel region and between a drain region and a channel region of the silicon thin film in the heat treatment process. A thin film transistor having:

In the active matrix array for a liquid crystal display device, according to the method of manufacturing a thin film transistor, wherein the crystallization is performed also in the heat treatment step instead of performing the crystallization in the crystallization step, It is preferable that a thin film transistor having an LDD structure be formed.

In the active matrix array for a liquid crystal display device, it is preferable that the thin film transistor having the LDD structure is formed by a method of manufacturing a thin film transistor using the ion doping method for the impurity implantation.

In the active matrix array for a liquid crystal display device, the thin film transistor having the LDD structure is formed by a method of manufacturing a thin film transistor using phosphorus (P) and arsenic (As) as the two different impurities. Is preferred.

Further, in the active matrix array for a liquid crystal display device, it is preferable that the thin film transistor having the LDD structure is formed by a method of manufacturing a thin film transistor in which laser annealing is performed using argon or excimer laser for the heat treatment. .

In the active matrix array for a liquid crystal display device, it is preferable that the thin film transistor having the LDD structure is formed by a method of manufacturing a thin film transistor in which the heat treatment is performed by laser annealing from the back surface of a glass substrate.

Next, a liquid crystal display device according to the present invention is a liquid crystal display device comprising an active matrix array substrate provided with a thin film transistor, and a counter substrate facing the active matrix array substrate, wherein at least one of the thin film transistors is provided. A thin film transistor for driving a pixel electrode, a deposition step of a silicon thin film for depositing an amorphous silicon thin film on a glass substrate, and a crystallization step of crystallizing the amorphous silicon thin film by a laser,
A gate insulating film depositing step of depositing a gate insulating film on the silicon thin film, a gate electrode depositing and patterning step of depositing and patterning a gate electrode on the gate insulating film, and passing through the gate insulating film and the gate electrode. An impurity implantation step of implanting two types of different impurities into the silicon thin film; and a heat treatment step of heat-treating the silicon thin film after the implantation of the impurity, wherein the heat treatment step includes a step between the source region and the channel region of the silicon thin film. And L between the drain region and the channel region.
The thin film transistor has an LDD region formed by a method for manufacturing a thin film transistor that forms a DD region.

In the liquid crystal display device, a color filter layer, a black matrix, and a transparent conductive layer made of an ITO thin film formed on the color filter layer and the black matrix are provided on the counter substrate. Is preferred.

In the liquid crystal display device, instead of performing the crystallization in the crystallization step, in the heat treatment step, the LDD region is formed by a method of manufacturing a thin film transistor in which the crystallization also serves as a heat treatment. Is preferably formed.

In the liquid crystal display device, it is preferable that the thin film transistor having the LDD region is formed by a method of manufacturing a thin film transistor using the ion doping method for the impurity implantation.

Further, in the liquid crystal display device,
It is preferable that the thin film transistor having the LDD region is formed by a method of manufacturing a thin film transistor using phosphorus (P) and arsenic (As) as different kinds of impurities.

Further, in the liquid crystal display device, a method of manufacturing a thin film transistor in which laser annealing is performed using argon or excimer laser for the heat treatment,
Preferably, a thin film transistor having the LDD region is formed.

In the liquid crystal display device, it is preferable that the thin film transistor having the LDD region is formed by a method of manufacturing a thin film transistor in which the heat treatment is performed by laser annealing from the back surface of the glass substrate.

According to the active matrix array for a liquid crystal display device or the liquid crystal display device as described above, the LDD
Since the entire region is formed under the gate electrode, the gate can be controlled with respect to injection of hot carriers generated during operation, so that reliability is improved. That is,
Even if hot carriers are injected, since the LDD region is entirely contained below the gate electrode, the hot carriers can be released (detrapped) again by the Coulomb force due to the voltage applied to the gate.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

(Embodiment 1) FIGS. 1 (a) to 1 (f)
1 is a cross-sectional view of a thin film transistor according to Embodiment 1 shown in the order of manufacturing steps.

FIG. 1A shows a step of depositing an amorphous silicon thin film. As shown in FIG. 1A, an amorphous silicon thin film 12 is formed on a glass substrate 10 via a coating layer 11 made of SiO ₂ . The amorphous silicon thin film 12 has a thickness of 85 nm and is formed by a plasma CVD method.

FIG. 1B shows a crystallization step of the amorphous silicon thin film 12. In this crystallization step, a polycrystalline silicon thin film 13 is formed. In forming the polycrystalline silicon thin film 13, first, the amorphous silicon thin film 12 is subjected to a heat treatment at 450 ° C. for 90 minutes in nitrogen to reduce the hydrogen concentration in the film. After that, excimer laser light
Irradiation was performed in eight directions to melt and crystallize the amorphous silicon thin film 12. A XeCl excimer laser having a wavelength of 308 nm was used as a light source for the excimer laser, and the energy density was 350 mJ / cm ² . Next, the formed polycrystalline silicon thin film 13 is processed into a thin film transistor shape.

FIG. 1C shows a step of depositing a gate insulating film,
This shows a state after a gate electrode deposition and patterning process. The gate insulating film 14 is made of a silicon oxide thin film and is formed by using a plasma CVD method. In the first embodiment, the film thickness is 100 nm. Gate insulating film 1
After forming 4, a gate electrode 15 is formed in a gate electrode deposition and patterning process.

From the state shown in FIG. 1C, the process shifts to an impurity implantation step. FIG. 1D shows a state after an impurity implantation step and a heat treatment step. In the impurity implantation step, phosphorus (P) ions and arsenic (As) ions are continuously implanted in the direction of arrow 28 shown in FIG. At this time, the phosphorus concentration in the polycrystalline silicon thin film 13 in the source and drain regions,
The arsenic concentration is implanted at an acceleration voltage that maximizes the arsenic concentration. In the first embodiment, the acceleration voltage of P ions and As ions is set to 9
0 kV and the injection amount was 1 × 10 ¹⁵ cm ⁻² . After the impurity implantation step, the process proceeds to a heat treatment step. In the heat treatment step, heat treatment is performed by irradiating an excimer laser beam in the direction of arrow 28 in FIG. Excimer laser energy density is 400
mJ / cm ² .

In this heat treatment step, the implanted impurities are activated, and the diffusion rate of P ions having a small molecular weight is higher than that of As ions having a large molecular weight. Therefore, only P ion molecules diffuse into the channel. To go.
As a result, the LDD regions 13b and A
A diffusion layer region 13c is formed by s ions.

Next, an interlayer insulating film 17 made of silicon oxide shown in FIG. 1E is formed. Further, FIG.
As shown in (1), a contact hole is opened and a source electrode 18 and a drain electrode 19 made of Al are formed to complete a thin film transistor.

As shown in FIG. 1F, the thin film transistor has an LDD region 13b between the source region and the channel region 13a of the diffusion layer region 13c and between the drain region and the channel region 13a of the diffusion layer region 13c. Is formed.

In this embodiment, P ions and As ions are continuously implanted. However, a method may be used in which two types of impurities are mixed in advance in a silicon thin film and then implanted.

In the first embodiment, in the heat treatment step, the heat treatment by the excimer laser is performed from the front surface of the substrate, but may be performed from the back surface of the substrate.

(Embodiment 2) FIGS. 2 (a) to 2 (e)
1 is a cross-sectional view of a thin film transistor according to Embodiment 2 shown in the order of manufacturing steps.

FIG. 2A shows a step of depositing an amorphous silicon thin film. As shown in this figure, an amorphous silicon thin film 12 is formed on a glass substrate 10 via a coating layer 11 made of SiO ₂ . Amorphous silicon thin film 1
Reference numeral 2 has a thickness of 85 nm and is formed by a plasma CVD method. The amorphous silicon thin film 12 is heat-treated at 450 ° C. for 90 minutes in nitrogen to reduce the hydrogen concentration in the film, and then processed into a thin film transistor shape. The deposition process of the amorphous silicon thin film of the second embodiment is the same as that of the first embodiment.

FIG. 2B shows a step of depositing a gate insulating film,
This shows a state after a gate electrode deposition and patterning process. The gate insulating film 14 is made of a silicon oxide thin film and is formed by using a plasma CVD method. In the second embodiment, the film thickness is 100 nm. Gate insulating film 1
After forming 4, a gate electrode 15 is formed in a gate electrode deposition and patterning process. The steps of depositing the gate insulating film, depositing and patterning the gate electrode of the second embodiment are the same as those of the first embodiment.

In the first embodiment, the process proceeds to the step of depositing the gate insulating film, the step of depositing the gate electrode, and the step of patterning through the crystallization step of the amorphous silicon thin film. The second embodiment is different from the first embodiment in that the crystallization step is omitted, and the process shifts directly from the step of depositing the amorphous silicon thin film to the step of depositing the gate insulating film, and the step of depositing and patterning the gate electrode.

Next, the process moves from the state shown in FIG. 2B to the impurity implantation step. FIG. 2C shows a state after an impurity implantation step and a heat treatment step. In the impurity implantation step,
P ions and As ions are continuously implanted in the direction of arrow 28 shown in FIG. At this time, implantation is performed at an acceleration voltage that maximizes the phosphorus concentration and the arsenic concentration in the polycrystalline silicon thin film 13 in the source and drain regions. In the second embodiment, the accelerating voltage of phosphorus ions and arsenic ions is 90 kV, and the implantation amount is 1 × 10 ¹⁵ cm ⁻² . After the impurity implantation step, the process proceeds to a heat treatment step. In the heat treatment step, the arrow 29 in FIG.
In the direction, heat treatment with an excimer laser is performed from the back surface of the substrate. The energy density was 400 mJ / cm ² .

In this heat treatment step, the implanted impurities are activated, and the amorphous silicon thin film portion of the channel region 13a is melted and crystallized. As in the first embodiment, since the diffusion rate of P ion molecules is faster than that of As ions, only P ion molecules diffuse into the channel. Thus, an LDD region 13b made of P ions and a diffusion layer region 13c made of As ions are formed.

In the second embodiment, the method of forming the LDD region and the diffusion layer region by the impurity implantation step and the heat treatment step is the same as that of the first embodiment. However, in the second embodiment, the amorphous silicon thin film portion is melted in the heat treatment step. This is different from the first embodiment in that the crystallization is also performed.

The steps shown in FIGS. 2D and 2E are the same as in the first embodiment. That is, as shown in FIG. 2D, an interlayer insulating film 17 made of silicon oxide is formed, and a contact hole is opened as shown in FIG.
Then, a source electrode 18 and a drain electrode 19 made of 1 are formed to complete a thin film transistor.

In the second embodiment, P ions and As ions are continuously implanted. However, a method in which two kinds of impurities are mixed in advance in a silicon thin film and then implanted may be used.

Embodiment 3 In Embodiment 3, a thin film transistor having an LDD structure is applied to an active matrix array for a liquid crystal display device.

FIGS. 3A to 3D show sectional views of the active matrix array for a liquid crystal display device according to the third embodiment in the order of manufacturing steps.

FIG. 3A shows a state after a deposition step of an amorphous silicon thin film, a crystallization step, and a deposition step of a gate insulating film. In addition, the p-channel thin film transistor section 30 described later shows an impurity implantation step after a gate electrode deposition and patterning step. Hereinafter, description will be made in the order of steps.

First, in the step of depositing an amorphous silicon thin film, a coating layer 1 made of SiO _{2 is formed} on a glass substrate 10.
1 to form an amorphous silicon thin film (not shown). The amorphous silicon thin film has a thickness of 50 nm, and the plasma C
It is formed by the VD method. Next, in the crystallization step, the amorphous silicon thin film is crystallized to form a polycrystalline silicon thin film 13.
To form In the third embodiment, the polycrystalline silicon thin film 1
In the formation of No. 3, a heat treatment was first performed at 450 ° C. for 90 minutes in nitrogen to reduce the hydrogen concentration in the film. Thereafter, an excimer laser beam having an energy density of 350 mJ / cm ² was irradiated to melt and crystallize the amorphous silicon thin film, thereby forming a polycrystalline silicon thin film 13.

Next, after processing the polycrystalline silicon thin film 13 into the shape of a thin film transistor, in the gate insulating film deposition step, the gate insulating film 14 is formed by plasma CVD.
To form The gate insulating film 14 was made of a silicon oxide thin film and had a thickness of 100 nm.

After the gate insulating film 14 is formed, in the step of depositing and patterning the gate electrode, the gate electrode 15 is formed on the p-channel thin film transistor portion 30 of the first conductivity type. At this time, the n-channel thin film transistor portion 31 and the pixel transistor 32 of the second conductivity type are covered with the covering portion 14a of the gate electrode material.

Next, in the impurity implantation step, B ions of the first conductivity type are implanted in the direction of arrow 28 in FIG. 3A using the gate electrode 15 on the p-channel thin film transistor section 30 as a mask. B ions are 95% hydrogen diluted B
₂ H ₆ gas was plasma-decomposed to generate ions, and the generated ions were accelerated and injected into the substrate without performing a mass separation step. The injection was performed at an acceleration voltage of 80 kV and an injection amount of 2 × 1.
It was set to 0 ¹⁵ cm ^-2 . By this step, B ions are implanted only into the p-channel thin film transistor section 30 to form source and drain regions.

FIG. 3B shows an impurity implantation step in the n-channel thin film transistor section 31 and the pixel driving transistor section 32. In order to form the gate electrode 15 on the n-channel thin film transistor portion 31 of the second conductivity type and to form the n-channel thin film transistor portion 31 of the second conductivity type, P ions and As ions are moved by arrows 2
Continuous injection in eight directions.

P ions and As ions are implanted at an accelerating voltage of 9
0 kV, and the injection amount was 2 × 10 ¹⁵ cm ⁻² . After the impurity implantation, heat treatment was performed with an excimer laser at an energy density of 400 mJ / cm ² . The impurities implanted by this heat treatment are activated, and the diffusion rate of P ion molecules is faster than the diffusion rate of As ion molecules, so that only P ion molecules diffuse into the channel. Thus, an LDD region 13b made of P ions and a diffusion layer region 13c made of As ions were formed.

Therefore, the pixel driving transistor section 3
2, the LDD region 13b is formed between the source region and the channel region 13a of the diffusion layer region 13c and between the drain region and the channel region 13a of the diffusion layer region 13c.

Next, as shown in FIG. 3D, an interlayer insulating film 17 made of silicon oxide and having a thickness of 400 nm is formed. After the formation of the interlayer insulating film 17, contact holes are opened on the source and drain regions of the first and second conductivity type thin film transistors. After the opening of the contact hole, a transparent conductive film (IT
O) to form the pixel electrode 20. After forming the pixel electrode 20, the source electrode 18 and the drain electrode 1 made of Al are formed.
9 to form a protective insulating film 22 made of a silicon nitride thin film.
To form After forming the protective insulating film 22, the thin film transistor array is completed by selectively removing the protective insulating film 22 on the pixel electrode.

In the third embodiment, P ions and As ions are continuously implanted. However, a method in which two kinds of impurities are mixed in advance in a silicon thin film and then implanted may be used.

In the third embodiment, the case where the pixel driving thin film transistor has the LDD structure is described. However, the LDD structure may be used as a part of the n-channel thin film transistor in the driving circuit portion. This case is particularly effective for improving reliability.

(Embodiment 4) In Embodiment 4, a liquid crystal display device is manufactured using the active matrix array of the present invention. This display device has a glass substrate 10
An active matrix array substrate having a thin film transistor formed thereon and a counter substrate facing the active matrix array substrate are provided. In this counter substrate,
Color filter layer 23 and black matrix 24
And a transparent conductive film 21 made of an ITO thin film formed on the color filter layer 23 and the black matrix 24. Liquid crystal 26 is injected between the active matrix array substrate and the opposing substrate. The liquid crystal 26 was injected after applying the alignment film 25, performing a rubbing process, and bonding both substrates.
Further, a polarizing plate 27 is provided on the glass substrate 10. The present liquid crystal display device performs image display by charging the liquid crystal by driving the pixel electrode 20 using the thin film transistor as a switching element.

Although the fourth embodiment has described the case where the pixel driving thin film transistor has the LDD structure, the LDD structure may be used as a part of the n-channel thin film transistor of the driving circuit portion. This case is particularly effective for improving reliability.

[0067]

As described above, according to the method of manufacturing a thin film transistor of the present invention, in the heat treatment step, different atoms in the silicon thin film have different diffusion rates due to external heat treatment. That is, a substance having a large molecular weight has a lower diffusion rate than a substance having a small molecular weight. For this reason, regions having different concentrations can be formed in the silicon thin film, and the number of steps can be increased in a self-aligned manner without increasing the number of steps.
DD regions and diffusion layer regions can be formed.

According to the active matrix array for a liquid crystal display device or the liquid crystal display device of the present invention, the LDD
Since the entire region is formed under the gate electrode, the gate can be controlled with respect to injection of hot carriers generated during operation, so that reliability is improved. That is,
Even if hot carriers are injected, since the LDD region is entirely contained below the gate electrode, the hot carriers can be released (detrapped) again by the Coulomb force due to the voltage applied to the gate.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a thin film transistor according to Embodiment 1 of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the thin film transistor according to Embodiment 2 of the present invention.

FIG. 3 is a sectional view showing a manufacturing process of an active matrix array for a liquid crystal display according to a third embodiment of the present invention.

FIG. 4 is a sectional view showing an embodiment of the liquid crystal display device of the present invention.

FIG. 5 is a cross-sectional view illustrating an example of a manufacturing process of a conventional thin film transistor having an LDD structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Glass substrate 11 Coat layer 12 Amorphous silicon thin film 13 Polycrystalline silicon thin film 13a Channel region 13b LDD region 13c Diffusion layer region 14 Gate insulating film 14a Covering portion 15 Gate electrode 16 Photoresist mask 17 Interlayer insulating film 18 Source electrode 19 Drain electrode Reference Signs List 20 pixel electrode 21 transparent conductive film 22 protective insulating film 23 color filter 24 black matrix 25 alignment film 26 liquid crystal 27 polarizing plate 28 laser irradiation direction or ion implantation direction 29 laser irradiation direction 30 p-channel thin film transistor section 31 n-channel thin film transistor section 32 pixel drive Thin film transistor part

Claims (19)

[Claims] A step of depositing an amorphous silicon thin film on a glass substrate; and a step of crystallizing the amorphous silicon thin film by a laser.
A gate insulating film depositing step of depositing a gate insulating film on the silicon thin film, a gate electrode depositing and patterning step of depositing and patterning a gate electrode on the gate insulating film, and passing through the gate insulating film and the gate electrode. An impurity implantation step of implanting two types of different impurities into the silicon thin film; and a heat treatment step of heat-treating the silicon thin film after the implantation of the impurity, wherein the heat treatment step includes a step between the source region and the channel region of the silicon thin film. And forming a low-concentration impurity implantation region (LDD region) between the drain region and the channel region. 2. The method according to claim 1, wherein, instead of performing the crystallization in the crystallization step, in the heat treatment step, the crystallization is performed also as a heat treatment. 3. The method according to claim 1, wherein an ion doping method is used for the impurity implantation. 4. The method according to claim 1, wherein the two different impurities are phosphorus (P).
3. The method of manufacturing a thin film transistor according to claim 1, wherein said thin film transistor uses arsenic (As). 5. The method for manufacturing a thin film transistor according to claim 1, wherein laser annealing is performed using argon or excimer laser for the heat treatment. 6. The method according to claim 1, wherein the heat treatment is performed by laser annealing from the back surface of the glass substrate. 7. An active matrix array for a liquid crystal display device including a thin film transistor, wherein at least one of the thin film transistors for driving a pixel electrode is formed by depositing an amorphous silicon thin film on a glass substrate. A crystallization step of crystallizing the amorphous silicon thin film with a laser,
A gate insulating film depositing step of depositing a gate insulating film on the silicon thin film, a gate electrode depositing and patterning step of depositing and patterning a gate electrode on the gate insulating film, and passing through the gate insulating film and the gate electrode. An impurity implantation step of implanting two types of different impurities into the silicon thin film; and a heat treatment step of heat-treating the silicon thin film after the implantation of the impurity, wherein the heat treatment step includes a step between the source region and the channel region of the silicon thin film. And L between the drain region and the channel region.
An active matrix array for a liquid crystal display device, which is a thin film transistor having an LDD region formed by a method for manufacturing a thin film transistor forming a DD region. 8. The thin film transistor having the LDD region is formed by a method of manufacturing a thin film transistor in which the crystallization is also performed in the heat treatment step instead of performing the crystallization in the crystallization step. The active matrix array for a liquid crystal display device according to claim 7. 9. The method of manufacturing a thin film transistor according to claim 1, wherein the method comprises the steps of:
9. The active matrix array for a liquid crystal display device according to claim 7, wherein a thin film transistor having a region is formed. 10. The phosphor as the two different impurities
9. The active matrix array for a liquid crystal display device according to claim 7, wherein the thin film transistor having the LDD region is formed by a method of manufacturing a thin film transistor using (P) and arsenic (As). 11. The active matrix array for a liquid crystal display device according to claim 7, wherein the thin film transistor having the LDD region is formed by a method of manufacturing a thin film transistor in which laser annealing is performed using argon or excimer laser for the heat treatment. . 12. The active matrix array for a liquid crystal display device according to claim 7, wherein the thin film transistor having the LDD region is formed by a method of manufacturing a thin film transistor in which the heat treatment is performed by laser annealing from the back surface of the glass substrate. 13. A liquid crystal display device comprising: an active matrix array substrate having a thin film transistor; and a counter substrate facing the active matrix array substrate, wherein at least one of the thin film transistors that drives at least a pixel electrode is a non-transistor. A silicon thin film deposition step of depositing a crystalline silicon thin film on a glass substrate, a crystallization step of crystallizing the amorphous silicon thin film with a laser, and a gate insulating film for depositing a gate insulating film on the silicon thin film. A deposition step; a gate electrode deposition and patterning step of depositing and patterning a gate electrode on the gate insulating film; and an impurity implantation step of implanting two different impurities into the silicon thin film through the gate insulating film and the gate electrode. And after the implantation of the impurity, A heat treatment step of heat-treating the silicon thin film, wherein the heat treatment step forms the LDD region between the source region and the channel region and between the drain region and the channel region of the silicon thin film by a method of manufacturing a thin film transistor. A liquid crystal display device comprising a thin film transistor having an LDD region. 14. A color filter layer, a black matrix, and an IT formed on the color filter layer and the black matrix on the counter substrate.
14. The liquid crystal display device according to claim 13, comprising a transparent conductive layer made of an O thin film. 15. A method of manufacturing a thin film transistor, wherein the crystallization is performed in the heat treatment step instead of performing the crystallization in the crystallization step,
15. The liquid crystal display device according to claim 13, wherein a thin film transistor having the LDD region is formed. 16. The method according to claim 16, further comprising the step of:
16. The liquid crystal display device according to claim 13, wherein a thin film transistor having a D region is formed. 17. The method according to claim 17, wherein the two different impurities are phosphorous.
16. The liquid crystal display device according to claim 13, wherein the thin film transistor having the LDD region is formed by a method of manufacturing a thin film transistor using (P) and arsenic (As). 18. The thin film transistor having the LDD region is formed by a method of manufacturing a thin film transistor in which laser annealing is performed using argon or excimer laser for the heat treatment.
6. The liquid crystal display device according to 5. 19. The liquid crystal display device according to claim 13, wherein the thin film transistor having the LDD region is formed by a method of manufacturing a thin film transistor in which the heat treatment is performed by laser annealing from the back surface of the glass substrate.