JPH10154710A - Semiconductor device and production thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a semiconductor fine and highly integrated by making a wiring member thin. SOLUTION: A Ti film 2, TiN film 3, Al alloy film 4, Ti film 5, and TiN film 6 are piled up in order on a silicon substrate 1, and boron ions are implanted to the entire surface of a device through an ion implantation method. Thus, a TiB2 compound phase is formed in the Ti film 5 and the wiring resistance is lowered. Therefore, the Ti film 5 can be made thinner, resulting in thinner wiring member entirely.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a technique for forming a multilayer wiring.

[0002]

2. Description of the Related Art In recent years, in a multilayer wiring structure employed in a highly integrated semiconductor device, there is a demand for a reduction in resistance of a wiring contact (via contact) and an improvement in wiring reliability. 12 to 14 are cross-sectional views showing a conventional process for manufacturing a multilayer wiring, taking a two-layer wiring as an example. Hereinafter, the manufacturing process will be sequentially described.

Step A (see FIG. 12): A silicon oxide film 52 as an insulating film is deposited on the surface of a single-crystal silicon substrate 51 to a suitable thickness by a CVD (chemical vapor deposition) method. Next, a titanium (Ti) thin film 53, a titanium nitride (TiN) thin film 54, an aluminum alloy thin film 55, and a titanium nitride thin film 56 are sequentially deposited on the surface of the Si oxide film 52 by sputtering.

Subsequently, wiring patterning is performed by using ordinary photolithography technology. Then, a wiring pattern of the first wiring layer is formed by dry etching. Here, the aluminum alloy thin film 55 is obtained by adding another metal or a high melting point metal to pure aluminum (for example,
Al-Si (1%)-Cu (0.5%), Al-Cu,
Al-Mg). As described above, by using not only pure aluminum but also an aluminum alloy, wiring failure due to electromigration (a phenomenon of disconnection due to movement of aluminum atoms due to electron flow) and stress migration (a phenomenon of disconnection due to stress only by heat) is prevented. Can be prevented.

Further, the titanium thin film 53 and the titanium nitride thin film 54 are formed under the aluminum alloy thin film 55 because Al and Si react at a contact portion (not shown) between the aluminum alloy thin film 55 and the substrate 51. This is to prevent the joint from being destroyed. Without these films, when heat treatment is performed after the formation of the first layer wiring, the aluminum alloy thin film 55
The aluminum contained therein reacts with the single crystal Si substrate 51. Then, Al and Si form a eutectic, and the Si
Is supplied from the Si substrate 51, so that the junction is broken. Therefore, by forming the titanium thin film 53 and the titanium nitride thin film 54 below the aluminum alloy thin film 55, the reaction at such an interface is prevented.

Further, the reason why the titanium thin film 53 is formed under the titanium nitride thin film 54 is that the contact resistance is increased if only the titanium nitride thin film 54 is used. Thus, the titanium nitride thin film 54 and the titanium thin film 53 function as a barrier metal. The reason why the titanium nitride thin film 56 is formed on the aluminum alloy thin film 55 is to prevent reflection from the aluminum alloy thin film 55 during exposure in photolithography. That is, the titanium nitride thin film 5
Reference numeral 6 also functions as an antireflection film (cap metal).

Step B (see FIG. 13):
On the surface of the titanium nitride thin film 56 of the first layer wiring, an Si oxide film 57 as an interlayer insulating film is deposited by an appropriate thickness. Next, patterning of the contact hole is performed by using a normal photolithography technique. Then, a contact hole 58 is formed by dry etching. Step C (see FIG. 14): inert gas (for example, argon)
The etching scum in the contact hole 58 and the contact hole 58
The oxide film and the like on the surface of the titanium nitride thin film 56 of the first wiring layer in the above is removed.

Next, a titanium nitride thin film 59, an aluminum alloy thin film 60, and a titanium nitride thin film 6 are formed on the surface of the Si oxide film 57 and in the contact hole 58 by sputtering.
1 are sequentially deposited. Subsequently, patterning of the wiring is performed using a normal photolithography technique. And
The wiring pattern of the second wiring layer is formed by dry etching, and the manufacturing process of the two-layer wiring is completed.

The aluminum alloy thin film 60 is made of the same material as the aluminum alloy thin film 55. The titanium nitride thin film 61 on the aluminum alloy thin film 60 functions as an anti-reflection film similarly to the titanium nitride thin film 56. Furthermore,
The reason for forming the titanium nitride thin film 59 under the aluminum alloy thin film 60 is to suppress the growth of hillocks caused by heat treatment such as sintering. That is, since the short-circuit of the wiring is induced by the growth of the hillock, the growth of the hillock is suppressed by forming the titanium nitride thin film 54 below the aluminum alloy thin film 60.

However, in this conventional example, for example,
In the step A, the formation of the titanium thin film 53 under the titanium nitride thin film 54 suppresses the increase in the contact resistance, but the contact portion between the first layer wiring and the second layer wiring has a nitrided layer. Only the titanium thin films 56 and 59 are interposed. In recent years, high integration of semiconductor devices has been further advanced, and it has been required to reduce the diameter of the contact hole 58. The contact resistance between the first layer wiring and the second layer wiring in this contact hole has been increased. Prevention is an important issue.

In Japanese Patent Application Laid-Open No. 7-142580 (H01L21 / 768), a laminated structure composed of a titanium nitride thin film / titanium thin film is adopted for a contact portion between a first layer wiring and a second layer wiring. While maintaining the function as an anti-reflection film, lower the value of contact resistance,
In addition, the electromigration resistance is improved.

[0012]

In the conventional example, both the contact resistance and the electromigration resistance are good. However, as compared with the case of a single layer of a titanium nitride thin film, the provision of a titanium thin film makes the device finer and higher. It is slightly inferior in that it corresponds to integration. The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and aims at realizing miniaturization and high integration as a semiconductor device by thinning a wiring layer while maintaining a good function as an antireflection film. And

[0013]

According to a first aspect of the present invention, there is provided a semiconductor device having a first metal wiring member containing an impurity for reducing specific resistance. According to a second aspect of the present invention, there is provided a semiconductor device having a first metal wiring member formed on a semiconductor substrate and containing an impurity for reducing specific resistance.

According to a third aspect of the present invention, the semiconductor device includes the first metal wiring member and the second metal wiring member connected to each other through a contact hole, and the first metal wiring member has a reduced specific resistance. Contains impurities to be added.
According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the first metal wiring member has a laminated structure in which a titanium film is formed on a main wiring member. It is.

[0015] The semiconductor device of claim 5 is a semiconductor device of claim 1.
4. The method according to claim 1, wherein the first
The metal wiring member has a laminated structure in which a titanium film and a titanium nitride film are sequentially formed on the main wiring member. According to a sixth aspect of the present invention, in the semiconductor device according to the fourth or fifth aspect, the main wiring member is made of aluminum alone or an aluminum alloy.

Further, the semiconductor device according to claim 7 is a semiconductor device according to claim 4.
7. In the invention according to any one of Items 6 to 6, the impurity is introduced into at least the titanium film and the main wiring member, and the profile of the impurity is continuous between the titanium film and the main wiring member. The peak value of this profile exists in other than the main wiring member. An eighth aspect of the present invention is the semiconductor device according to any one of the first to seventh aspects, wherein boron is used as the impurity.

According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device, a first metal wiring member is formed on a substrate, and an impurity is introduced into the first metal wiring member. Further, in the method of manufacturing a semiconductor device according to the present invention, the first
Forming a metal wiring member, forming an interlayer insulating film on the first metal wiring member, and forming a second metal wiring member connected to the first metal wiring member via a contact hole. And introducing an impurity into the first metal wiring member before forming the second metal wiring portion.

According to a twelfth aspect of the present invention, in the method of manufacturing a semiconductor device according to the ninth or tenth aspect, there is provided a method of manufacturing a semiconductor device, comprising:
The metal wiring member has a laminated structure in which a titanium film is formed on the main wiring member. According to a twelfth aspect of the present invention, in the method for manufacturing a semiconductor device according to the ninth or tenth aspect, the first metal wiring member has a laminated structure in which a titanium film and a titanium nitride film are sequentially formed on a main wiring member. It has.

According to a thirteenth aspect of the present invention, in the semiconductor device manufacturing method according to the eleventh or twelfth aspect, the main wiring member is made of aluminum alone or an aluminum alloy. According to a fourteenth aspect of the present invention, in the method for manufacturing a semiconductor device according to the thirteenth aspect, the impurity is introduced under a condition that the titanium film has a peak.

According to a fifteenth aspect of the present invention, in the semiconductor device manufacturing method according to the thirteenth aspect, the impurity is introduced under conditions such that the titanium nitride film has a peak. According to a sixteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to any one of the ninth to fifteenth aspects, wherein a substance that lowers the specific resistance of the first metal wiring member is used as the impurity. is there.

According to a seventeenth aspect of the present invention, in the method of manufacturing a semiconductor device, boron is used as the impurity in the invention according to any one of the ninth to sixteenth aspects. In a eighteenth aspect of the present invention, in the method of the sixteenth or seventeenth aspect, the impurity is introduced by applying kinetic energy using an ion implantation method or the like.

That is, by introducing an impurity such as boron into a wiring member such as titanium, the wiring resistance is reduced, and as a result, the film thickness of the wiring member can be reduced. In addition, when an impurity is introduced into a main wiring member such as an aluminum alloy, the average disconnection time may be shortened. However, in the invention according to claim 7, 14 or 15, the impurity is introduced mainly into the titanium film, Since the impurity is not introduced into the main wiring member such as an aluminum alloy as compared with the titanium film or the titanium nitride film, the shortening of the average disconnection time can be prevented.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing method according to an embodiment of the present invention will be described with reference to the drawings. 1 to 9 are cross-sectional views showing the manufacturing process of the semiconductor device according to the present embodiment. Step 1 (see FIG. 1): A Ti film 2 (50 nm thick) is formed on a single crystal silicon substrate 1 by magnetron sputtering.
m), TiN film 3 (film thickness 100 nm), Al alloy film (A
l-Si (1%)-Cu (0.5%)) 4 (film thickness 600
nm), a Ti film 5 (thickness: 20 nm) and a TiN film 6 (thickness: 100 nm) are stacked in this order.

Although not shown, the surface of the silicon substrate 1 is in a state where active elements such as MOS transistors are previously covered with an insulating film made of a silicon oxide film. Step 2 (see FIG. 2): Boron ions (B ⁺ ) are implanted over the entire surface of the device by using an ion implantation method. Conditions for ion implantation are as follows: acceleration energy: 40 KeV, dose amount: 1
× 10 ¹⁵ ions / cm ² . These conditions are set so that the peak of the ion concentration distribution exists in the Ti film 5.

FIG. 10 shows the results of measuring the average disconnection time when various ions are implanted into the Al alloy film 4.
It can be seen that the average disconnection time becomes shorter (particularly when argon (Ar), fluorine (F) and boron fluoride (BF ₂ ) are used, the result is remarkable). In view of this result, in this embodiment, the ion implantation conditions are set such that the peak of the ion concentration distribution is present in the Ti film 5 as shown in FIG. By preventing this, the average disconnection time of the Al alloy film 4 itself is suppressed from being shortened. In addition, T described later
Although the effect of lowering the resistance of the i film 5 is slightly inferior, in this case, the peak of the ion concentration distribution may be present in the TiN film 6.

Then, by introducing boron ions into the Ti film 5, a TiB ₂ compound phase is formed in the Ti film 5,
Wiring resistance decreases. Table 1 shows the measured specific resistance of various Ti-based metals, and it can be seen that TiB ₂ has an extremely low specific resistance as compared with other metals.

[0027]

[Table 1]

Step 3 (see FIG. 3): The wiring layer composed of the Ti film 2, TiN film 3, Al alloy film 4, Ti film 5, and TiN film 6 is formed by photolithography and dry etching. It is processed as one metal wiring 7.
At this time, the laminated structure including the Ti film 2 and the TiN film 3 functions as a barrier metal, and the Ti film 5 and the TiN film 6
Functions as a cap metal.

Step 4 (see FIG. 4): TEOS (Tetra-eth
oxy Silane: Plasma T is deposited on the first metal wiring 7 by a plasma CVD method using Si (OC ₂ H ₅ ) ₄ and oxygen.
An EOS oxide film 8 (film thickness 100 nm) is formed. The film thickness of the plasma TEOS oxide film 8 is adjusted to be thicker when the step is large and to be thin when the step is small, according to the base step.

Step 5 (see FIG. 5): An organic SOG film 9 is formed on the plasma TEOS oxide film 8. Here, after applying 200 nm of organic SOG, the organic SOG is further
And then baked at a temperature of about 450 ° C. to a total film thickness of 400 when no underlying pattern exists.
nm. This organic SOG is a silicon oxide material containing 1% or more of carbon (C).

Step 6 (see FIG. 6): Boron ions are implanted into the organic SOG film 9 using an ion implantation method.
By implanting ions into the organic SOG film 9 in this manner,
The organic components are decomposed, and the water and hydroxyl groups contained in the organic SOG film 9 decrease. As a result, the organic SOG film 9
SOG film containing only a small amount of water and hydroxyl groups (hereinafter referred to as SOG film)
(Referred to as a modified SOG film) 10.

Step 7 (see FIG. 7): A plasma TEOS oxide film 11 (thickness: 200 nm) is formed on the modified SOG film 10 by using a plasma CVD method. The conditions for forming the silicon oxide film 11 are the same as those for the plasma TEOS oxide film 8. Step 8 (see FIG. 8): Anisotropic etching using a mixed gas system of carbon tetrafluoride and hydrogen as an etching gas to form a via hole 12 in each of the films 8, 10 and 11 to communicate with the first metal wiring 7. I do.

Step 9 (see FIG. 9): After cleaning the inside of the via hole 12 by sputter etching using an inert gas (for example, Ar), the inside of the via hole 12 and the plasma TEO are removed by magnetron sputtering.
On the S oxide film 11, an Al alloy film (Al-Si (1%)
-Cu (0.5%)) (film thickness 500 nm), a Ti film (film thickness 50 nm), and a TiN film (film thickness 20 nm) are sequentially formed from below.

Then, the aluminum alloy film, the Ti film and the TiN film are patterned into a predetermined shape by applying a resist (not shown), exposing, and etching by a usual lithography technique and a dry etching technique (RIE method or the like). Then, the upper metal wiring 13 is formed. As described above, in the present embodiment, the plasma TEOS oxide film 8 and the modified SOG
The film 10 and the plasma TEOS oxide film 11 form an interlayer insulating film having a three-layer structure. Like the organic SOG film 9, the modified SOG film 10 can have a thickness of about 0.5 to 1 μm.

Therefore, if the modified SOG film 10 is used, the thickness of the interlayer insulating film can be increased, and sufficient flatness can be ensured even for a large step on the substrate 1. The reason why the sandwich structure in which the modified SOG film 10 is sandwiched between the plasma TEOS oxide films 8 and 11 is adopted also in order to increase the insulating property and mechanical strength of the entire interlayer insulating film.

Further, since the modified SOG film 10 does not contain an organic component, the etching for forming the via hole 12 can be performed in an atmosphere of a mixed gas of carbon tetrafluoride and hydrogen. Therefore, in this etching, even if a photoresist is used as an etching mask, the photoresist is not affected,
Modified SOG film 1 masked with the photoresist
0 is not etched. Therefore, fine via holes 12 can be accurately formed.

Further, since the modified SOG film 10 does not contain an organic component, the etching rate of the modified SOG film 10 is the same as that of each of the plasma TEOS oxide films 8 and 11, and is used as an etching mask. The modified SOG film 10 does not shrink during the ashing process for removing the photoresist. Therefore, cracks do not occur in the modified SOG film 10 and no recess occurs when the via holes 12 are formed. Therefore, via hole 12
The upper metal wiring 13 can be sufficiently buried therein.

Since the modified SOG film 10 does not contain organic components and contains only a small amount of water and hydroxyl groups, one or both of the plasma TEOS oxide films 8 and 11 are omitted and the modified SOG film 10 is omitted. 10 may be used in a single layer or two layers. As described above, in the present embodiment, the impurity (boron: B) is added to the Ti film 5 by ion implantation, so that the wiring resistance is reduced. Therefore, the thickness of the Ti film 5 itself can be reduced. In general, the thickness of the first metal wiring 7 can be reduced. In addition, the contact resistance and the electromigration resistance can maintain the same or better characteristics as those of the related art.

Therefore, not only the miniaturization and high integration of the semiconductor device can be realized, but also the parasitic capacitance between the wirings is reduced because the wiring thickness is small, which contributes to the high-speed operation of the device. Can be. It should be noted that the present invention is not limited to the above embodiment, and the same effects can be obtained even if the present invention is implemented as follows.

1) Instead of the organic SOG film 9, a polyimide or a siloxane-knit polyimide is used. 2) Instead of the plasma TEOS oxide films 8 and 11, a method other than the plasma CVD method (normal pressure CVD method, low pressure CVD method)
Method, ECR plasma CVD method, photo-excited CVD method, TEO
A silicon oxide film formed by an S-CVD method, a PVD method, or the like is used. In this case, the gases used in the normal pressure CVD method are monosilane and oxygen (SiH ₄ + O ₂ ).
The film forming temperature is 400 ° C. or less. The gas used in the low pressure CVD method is monosilane and nitrous oxide (SiH ₄ +
N ₂ O), and the film formation temperature is 900 ° C. or less.

3) Each plasma TEOS oxide film 8, 11
Is replaced by another insulating film (such as a silicon nitride film or a silicate glass film) having a property of high mechanical strength in addition to a property of blocking moisture and a hydroxyl group. The insulating film is CVD
It may be formed by any method such as a method or a PVD method. 4) The Al alloy film in the first metal wiring 7 and the second metal wiring 13 is formed of a conductive material other than aluminum (copper, gold, silver, silicide, high melting point metal, doped polysilicon, titanium nitride (TiN), tungsten titanium). (An alloy such as (TiW)) and a laminated structure thereof.

5) The modified SOG film 10 is subjected to a heat treatment. In this case, dangling bonds in the modified SOG film 10 are reduced, so that the hygroscopicity is further reduced and the permeation of moisture is further reduced. 6) The modified SOG film 10 is also used as a passivation film. In this case, an excellent passivation film that can reliably protect the device mechanically and chemically can be obtained.

7) In the above embodiment, boron ions are used as ions to be implanted into the Ti film 5, but as a result,
Any ion may be used as long as the specific resistance of the i-film 5 is reduced. 8) In the above embodiment, ions are implanted into the Ti film 5. However, the ions are not limited to ions, but may be atoms, molecules, or particles (in the present invention, these are collectively referred to as impurities).

9) As a sputtering method, besides magnetron sputtering, a method such as diode sputtering, high-frequency sputtering, quadrupole sputtering or the like may be used. 10) As a method of sputter etching, besides using an inert gas, reactive ion beam etching (also called RIBE or reactive ion milling) using a reactive gas (for example, CCl ₄ or SF ₆ ) may be used. .

11) The plasma TEOS oxide film 11 is omitted. 12) As a method of introducing ions into the Ti film 5, an ion implantation method is used, but an ion shower doping method or another insulating film (in the above embodiment, a BSG film is appropriate because boron ions are used) May be used.

[0046]

According to the present invention, the thickness of the wiring member can be reduced while maintaining characteristics equal to or higher than those of the prior art, which can greatly contribute to miniaturization and high integration of a semiconductor device.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to one embodiment of the invention.

FIG. 2 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to one embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing a process of manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to one embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to one embodiment of the invention;

FIG. 7 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to one embodiment of the present invention;

FIG. 8 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to one embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to one embodiment of the present invention;

FIG. 10 is a characteristic diagram for explaining the embodiment of the present invention.

FIG. 11 is a characteristic diagram for explaining the embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device in a conventional example.

FIG. 13 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device in a conventional example.

FIG. 14 is a schematic sectional view showing a manufacturing process of a semiconductor device in a conventional example.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 Ti film (first metal wiring member) 3 TiN film (first metal wiring member) 4 Al alloy film (main wiring member, first metal wiring member) 5 Ti film (first metal wiring member) 6 TiN Film (first metal wiring member) 7 First metal wiring (first metal wiring member) 12 Contact hole 13 Upper metal wiring (second metal wiring member)

Continuation of the front page (72) Inventor Yasuyuki Inoue 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd.

Claims (18)

[Claims] 1. A semiconductor device comprising a first metal wiring member containing an impurity for lowering specific resistance. 2. A semiconductor device comprising a first metal wiring member formed on a semiconductor substrate and containing an impurity for lowering specific resistance. 3. The semiconductor device according to claim 1, further comprising: a first metal wiring member and a second metal wiring member connected to each other via a contact hole, wherein the first metal wiring member contains an impurity that reduces specific resistance. Semiconductor device. 4. The semiconductor device according to claim 1, wherein the first metal wiring member has a laminated structure in which a titanium film is formed on a main wiring member. 5. The first metal wiring member according to claim 1, wherein the first metal wiring member has a laminated structure in which a titanium film and a titanium nitride film are sequentially formed on a main wiring member.
13. The semiconductor device according to item 9. 6. The semiconductor device according to claim 4, wherein said main wiring member is made of aluminum alone or an aluminum alloy.
Or the semiconductor device according to 5. 7. The impurity is introduced into at least the titanium film and the main wiring member, and the profile of the impurity is continuous between the titanium film and the main wiring member. The semiconductor device according to claim 4, wherein the semiconductor device is provided other than the member. 8. The semiconductor device according to claim 1, wherein said impurity is boron. 9. A method for manufacturing a semiconductor device, comprising: forming a first metal wiring member on a substrate; and introducing an impurity into the first metal wiring member. 10. A step of forming a first metal wiring member on a semiconductor substrate, a step of forming an interlayer insulating film on the first metal wiring member, and a step of contacting the first metal wiring member through a contact hole. Forming a second metal wiring member to be connected, and introducing an impurity into the first metal wiring member before forming the second metal wiring portion. 11. The method according to claim 9, wherein the first metal wiring member has a laminated structure in which a titanium film is formed on a main wiring member. 12. The semiconductor device according to claim 9, wherein the first metal wiring member has a laminated structure in which a titanium film and a titanium nitride film are sequentially formed on a main wiring member. Method. 13. The method of manufacturing a semiconductor device according to claim 11, wherein said main wiring member is made of aluminum alone or an aluminum alloy. 14. The method according to claim 1, wherein the impurity is introduced under conditions such that the titanium film has a peak.
4. The method for manufacturing a semiconductor device according to item 3. 15. The method of manufacturing a semiconductor device according to claim 13, wherein the impurity is introduced under conditions such that the titanium nitride film has a peak. 16. The method of manufacturing a semiconductor device according to claim 9, wherein a substance that lowers the specific resistance of the first metal wiring member is used as the impurity. 17. The method of manufacturing a semiconductor device according to claim 9, wherein boron is used as the impurity. 18. The method of manufacturing a semiconductor device according to claim 16, wherein the impurity is introduced by applying kinetic energy using an ion implantation method or the like.