JPH10150146A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To thin an insulating film used for a capacitive element so as to enhance the capacitive element in capacitance, and to manufacture a semiconductor device of high withstand voltage through a smaller number of processes. SOLUTION: An Al film is formed on a second interlayer insulating film 7 and then selectively etched, whereby an upper electrode 8 is formed at a position corresponding to a lower electrode 2, and an upper wiring 9 is formed on a wiring region 12. As mentioned above, a second interlayer insulating film 7 is sandwiched in between the upper electrode 8 and the lower electrode 2 to constitute a capacitive element 10 of required capacitance. The capacitance of the capacitive element 10 is determined by multiplying the area of a region conductive to capacitance by an inverse number of a space between the electrodes 8 and 2, and the interlayer insulating film 7 can be thinned, so that the capacitive element 10 of required capacitance can be lessened in area. By this setup, a semiconductor device of this constitution can be thinned in size.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a capacitive element integrally.

[0002]

2. Description of the Related Art For example, a MOS LSI for handling analog signals
In such a case, it is necessary to form a capacitance element (capacitor), and a capacitance element having an interlayer film between a polysilicon film and an Al film or between an Al film and an Al film formed as a parallel electrode has been formed.

[0003]

In recent years, device miniaturization has progressed, and the interlayer film has been flattened to facilitate microfabrication. As a result, the thickness of the interlayer film tends to increase. In the capacitive element, the capacitance per unit area is small. Further, in order to prevent a decrease in operation speed, a device structure using a film that reduces the capacitance between layers has been developed.

For this reason, when a device having the above-described capacitance element is formed, a capacitance element having a larger area is required to secure a desired capacitance, and the electrode size of the capacitance element increases. The result is.

[0005] An example of a method of manufacturing a semiconductor device in which a capacitor is formed as described above will be described below. As shown in FIG. 4A, after a lower wiring layer 32 made of Al or the like and a lower electrode 33 serving as one electrode of a capacitor are formed on an insulating layer 31 covering the surface of the semiconductor substrate 30, the lower electrode 33 is covered. And S
An interlayer insulating film 34 for flattening by OG (spin-on glass) or the like is applied and formed. At this time, another insulating film may be deposited and formed as a base of the interlayer insulating film.

Next, as shown in FIG. 4B, an interlayer insulating film 3 is formed.
A resist 35 is formed on the substrate 4, and then a hole 36 is formed in the capacitor element forming region. Then, as shown in FIG. 4C, selective etching is performed using the resist 35 as a mask to form a contact hole 37 corresponding to the hole 36 in the interlayer insulating film 34, and the surface of the lower electrode 33 is exposed.

After removing the resist 35, as shown in FIG. 5D, an insulating film 38 is formed so as to cover the whole. And
As shown in FIG. 5E, the insulating film 3 is anisotropically etched.
Then, the insulating film 38 is etched back to form a portion (so-called sidewall) 3 along the inner wall of the contact hole 37.
Leave only 8a.

Next, as shown in FIG. 5F, an insulating film 39 is formed on the entire surface covering the surface. At this time, the insulating film 38
Due to the remaining portion 38a, the contact hole 37 gradually increases in the upward direction, and the steepness of the step is alleviated. Therefore, there is an effect of preventing the insulation film 39 from deteriorating withstand voltage and the like.

Thereafter, after a contact hole 40 for a wiring layer is opened, an Al film or the like is formed so as to cover the surface, and the Al film or the like is subjected to pattern etching, thereby forming a lower wiring 32.
An upper wiring 41 is formed thereon, and an upper electrode 42 serving as the other electrode of the capacitor is formed on the lower electrode 33. The lower electrode 33 and the upper electrode 42 thus formed, and the insulating film 39 between them constitute a capacitive element 45.

According to the above-described manufacturing method, the contact hole 37 gradually increases upward due to the remaining portion 38a of the insulating film 38, and the steepness of the step is reduced. Even with a small thickness, the withstand voltage of the capacitor 45 can be ensured. However, in the above-described manufacturing method, the number of steps increases because the insulating film 38 is left.

In order to solve the above-mentioned problems, the present invention relates to a semiconductor device having a capacitance element, wherein the insulation film of the capacitance element is thinned to increase the capacitance value, and the withstand voltage is sufficiently secured. To provide a method of manufacturing a semiconductor device which can be manufactured with fewer steps.

[0012]

According to a method of manufacturing a semiconductor device of the present invention, a resist layer is formed on a first interlayer insulating film formed covering a lower electrode except for a lower electrode portion.
Etch-back is performed, and an upper electrode facing the lower electrode is formed through the second interlayer insulating film or the remaining first interlayer insulating film to form a capacitor.

According to the present invention described above, the distance between the upper electrode and the lower electrode of the capacitive element can be shortened and the capacitance of the capacitive element can be further increased because the interlayer insulating film in the capacitive element can be formed thin. Can be.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention comprises a step of forming a first interlayer insulating film covering a lower electrode on a substrate, and a step of forming a resist layer on the first interlayer insulating film except for a portion corresponding to the lower electrode. Is formed, and then a step of performing an etch-back and a step of forming an upper electrode opposed to the lower electrode with a second interlayer insulating film interposed therebetween to form a capacitor element.

Further, according to the present invention, a step of forming a first interlayer insulating film covering a lower electrode on a substrate, and forming a resist layer on the first interlayer insulating film except for a portion corresponding to the lower electrode. Thereafter, a step of performing etch-back so that a portion of the first interlayer insulating film corresponding to the lower electrode remains at a required film thickness, and forming an upper electrode facing the lower electrode via the remaining first interlayer insulating film. 5 is a method for manufacturing a semiconductor device including a step of forming a capacitor to form a capacitor.

An embodiment of the method of manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings. First, as shown in FIG. 1A, an insulating film 2 such as SiO ₂ is formed on a surface of a semiconductor substrate 21 on which elements such as MOS transistors are formed.
A lower electrode 2 for forming, for example, a parallel plate type capacitive element is formed of Al or the like on a base region 1 formed with 2. Along with the formation of the lower electrode 2, the lower wiring 3 is formed on the wiring region. The lower electrode 2 and the lower wiring 3 are simultaneously formed by selective etching after forming the Al layer.

Next, as shown in FIG. 1B, an interlayer insulating film 4 is formed on the entire surface covering the lower electrode 2 and the lower wiring 3 by CVD or the like. Subsequently, as shown in FIG. 1C, a resist 5 for flattening by an etch-back method is formed on the entire surface so as to cover the interlayer insulating film 4.

Next, as shown in FIG. 2D, a mask pattern is printed on the resist 5 using a stepper or the like.
The window 6 is opened in the capacitance element formation region 11.

Next, as shown in FIG. 2E, the resist 5 and the interlayer insulating film 4 are etched back at the same time, the interlayer insulating film 4 is shaved, and the interlayer insulating film 4 is flattened. At this time, since the capacitive element forming region 11 in which the window 6 has been opened earlier is shaved from the beginning of the interlayer insulating film 4, the interlayer insulating film 4 becomes thinner than the wiring region 12. In the example of FIG. 2E, all of the interlayer insulating film 4 on the lower electrode 2 is removed. By this etch back, a step between the lower electrode 2 and the interlayer insulating film 4 around the lower electrode 2 is reduced.

Subsequently, as shown in FIG. 2F, a second interlayer insulating film 7 is formed so as to cover the entire surface by CVD or the like. This second interlayer insulating film 7 becomes a dielectric film constituting a capacitive element.

Next, as shown in FIG. 3, an Al film is formed on the second interlayer insulating film 7 and is selectively etched to form an upper electrode 8 at a position corresponding to the lower electrode 2. Then, the upper wiring 9 is formed in the wiring region 12. In this way, a capacitance element 10 having a required capacitance between the upper electrode 2 and the lower electrode 8 with the second interlayer insulating film 7 interposed therebetween is formed.

Thus, a semiconductor device having the capacitor 10 formed thereon can be manufactured. Since the capacitance of the capacitor depends on the product of the area of the region contributing to the capacitance and the reciprocal of the electrode interval, the thickness of the interlayer insulating film 7 can be reduced as described above. The area for formation can be reduced accordingly. Accordingly, the size of the device can be reduced.

Further, the thickness of the interlayer insulating film that defines the capacitance can be determined by the thickness of the second interlayer insulating film that is formed last, so that the thickness of the interlayer insulating film of the capacitive element varies. Factors are reduced. Since the step between the lower electrode 2 and the surrounding interlayer insulating film 4 can be reduced, the step of the second interlayer insulating film 7 formed thereon is reduced, and the withstand voltage of the second interlayer insulating film 7 is reduced. Can be prevented.

Further, since the contact hole can be formed in the capacitive element portion in the same step as the planarization between the layers, the number of steps can be reduced as compared with the conventional manufacturing method shown in FIGS. Can be. Further, the edge shape of the insulating film between the electrodes of the capacitor is also processed in the step of etching back the resist, so that the edge shape can be processed without adding a new step.

In the above example, in FIG. 2E, the capacitor element forming region 11 is shaved while performing etch-back. It may be thinned. Further, in FIG. 2F, the second interlayer insulating film 7 is further formed after the etch back. However, it is also possible to control the amount of the etch back to leave the interlayer insulating film 4 on the lower electrode 2. .

In order to reduce the variation in the thickness of the interlayer insulating film between the capacitor electrodes, the interlayer insulating film is not left on the lower electrode after the etch back, and the second interlayer insulating film to be formed next is formed. It is effective to adjust the film thickness so as to obtain a withstand voltage between the electrodes.

In the above example, the capacitive element 1
Although the example in which 0 is formed is used, the manufacturing method of the present invention can be similarly applied to a semiconductor device having another configuration having a capacitor.

The method of manufacturing a semiconductor device according to the present invention is not limited to the above-described example, but may take various other configurations without departing from the gist of the present invention.

[0029]

According to the method of the present invention described above, the thickness of the interlayer insulating film in the capacitor element forming region can be reduced, so that the area for forming the capacitor element can be reduced accordingly, and the device can be downsized. Can be achieved.

Further, according to the present invention, the thickness of the interlayer insulating film for determining the capacitance can be determined by the thickness of the insulating film to be formed last, and the cause of the variation in the thickness of the interlayer insulating film is reduced. In addition, the controllability of the capacitance value can be improved.
Therefore, according to the present invention, the reliability of a semiconductor device having a capacitor can be improved.

Further, a semiconductor device having a capacitance element can be manufactured with fewer steps than in the conventional case.

[Brief description of the drawings]

1A to 1C are process diagrams of a manufacturing process of an embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIGS. 2A to 2F are process diagrams of a manufacturing process of an embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 3 is a process chart of a manufacturing process of an embodiment of a method of manufacturing a semiconductor device according to the present invention.

4A to 4C are manufacturing process diagrams of a conventional manufacturing method.

5A to 5F are manufacturing process diagrams of a conventional manufacturing method.

FIG. 6 is a manufacturing process diagram of a conventional manufacturing method.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 base region, 2 lower electrode, 3 lower wiring, 4 interlayer insulating film, 5 resist, 6 window, 7 second interlayer insulating film, 8 upper electrode, 9 upper wiring, 10 capacitive element, 1
DESCRIPTION OF SYMBOLS 1 Capacitance element formation area, 12 wiring area, 21 semiconductor substrate, 22 insulating film, 30 semiconductor substrate, 31 insulating layer, 32 lower wiring, 33 lower electrode, 34 interlayer insulating film, 35 resist, 36 hole, 37, 40 contact hole , 38, 39 Insulating film, 41 Upper wiring, 42
Upper electrode, 45 capacitive element

Claims (2)

[Claims] A step of forming a first interlayer insulating film covering the lower electrode on the substrate; and forming a resist layer on the first interlayer insulating film except for a portion corresponding to the lower electrode. A method of manufacturing a semiconductor device, comprising: a step of performing an etch-back; and a step of forming an upper electrode facing the lower electrode via a second interlayer insulating film to form a capacitive element. A step of forming a first interlayer insulating film on the substrate so as to cover the lower electrode; and a step of forming a resist layer on the first interlayer insulating film except for a portion corresponding to the lower electrode. Performing an etch-back so that a portion of the first interlayer insulating film corresponding to the lower electrode remains at a required thickness; and opposing the lower electrode via the remaining first interlayer insulating film. A method for manufacturing a semiconductor device, comprising a step of forming a capacitor by forming an upper electrode.