JPH10144914A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce junction capacitance of source and drain regions, while suppressing short channel effects. SOLUTION: This device has an epitaxial layer 11 on a substrate 2 and source and drain regions 8a, 8b respectively reaching an interface with at least the substrate 2 from the surface of the epitaxial layer 11, and between the regions 8a, 8b and the reverse conductive type substrate region 2, low concentration regions 12a, 12b having the same conductivity type and a conductive degree lower than in this substrate region 2 are made to reside. Thereby, the source and drain regions and substrate are close to an inclined junction, and the capacitance is reduced. On the other hand, an insulating layer which is brought into contact from a depth side in a depth direction of the substrate for the source and drain regions is provided, thereby attempting to reduce the junction capacitance. In the low concentration regions 12a, 12b, by setting a concentration profile so as to be formed concurrently at the time of ion implantation, the insulating layers can respectively and readily be formed by a SIMOX(separation by inplanted oxygen) method.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a fine insulated gate field effect transistor and a method of manufacturing the same, and more particularly, to a technique for suppressing a short channel effect accompanying miniaturization and reducing an impurity diffusion capacity.

[0002]

2. Description of the Related Art In recent years, MOSFETs (Metal-Oxide
-Semiconductor Field-Effect Transistor) has been remarkably miniaturized. For example, DRAM (Dynamic R
andom-Access Memory) is now in mass production.

[0003] By the way, what are considered as factors that hinder the progress of miniaturization of such a MOS type LSI include a problem caused by a so-called short channel effect and a problem caused by the parasitic capacitance not being reduced with miniaturization. There is.

In the so-called short channel effect, the gate length is shortened, for example, the depletion layers of the source region and the drain region protrude and the ability of the gate electrode to control the channel is weakened. First, it appears remarkably as a roll off effect. Further, as the gate length is further reduced, a depletion layer extends from the drain region and approaches the depletion layer from the source region, causing punch-through in which current flows through the channel even when no gate voltage is applied. Easier to do.
If the withstand voltage between the source and the drain decreases and punch-through occurs, the operation limit of the MOSFET is determined by these factors.

In addition, a so-called hot electron effect occurs, which changes the gate threshold voltage Vth,
Phenomenon transconductance g _m is reduced are also considered as category of broadly short channel effect. That is, when the gate is shortened and a high electric field is applied to the pinch-off region generated particularly near the drain end, as a result, the velocity of electrons flowing through the channel under the gate oxide film increases near the drain end, The electrons become hot (excited) and have high energy. When the electrons are in a hot state, part of the electrons enter the gate oxide film without flowing into the drain, and increase the amount of negative charges in the film. As a result, it becomes difficult current flows together with the operation time, and to cause variation and g _m decrease in Vth.

On the other hand, as is well known, the junction capacitance of a pn junction increases as the dopant concentration difference increases,
The increase in the junction capacitance causes a problem in characteristics such as a decrease in the switching speed of the element.

[0007] As one method of preventing the short channel effect, particularly the decrease of the gate threshold voltage Vth, the simplest method is to increase the concentration of the channel formation region to suppress the extension of the depletion layer at the drain end to the channel side. It is conceivable that the electric field is alleviated to increase the control ability of the gate electrode. However, when the concentration of the channel formation region is increased, a reduction in the breakdown voltage between the source and the drain, an increase in the junction capacitance, a reduction in the carrier mobility become apparent, and the substrate is more easily affected by the substrate bias effect.

Therefore, in order to suppress the short channel effect and reduce the junction capacitance without increasing the concentration of the channel formation region, a channel is formed in the epitaxial layer on the semiconductor substrate to spatially connect with the substrate side. There has been proposed a fine MOS • FET structure which is separated and has a high concentration only on the semiconductor substrate surface side.

As shown in FIGS. 5A to 5C, the fine M
The method of manufacturing the OS • FET structure will be described with reference to FIG.
First, a p-type silicon wafer 100 is prepared, a field oxide film 101 is selectively formed on the silicon wafer 100 by using the LOCOS method, and the surface of the active region where the field oxide film 101 is not formed is formed. , A shallow high-concentration impurity region 102 is formed by ion implantation. Then, a non-doped silicon epitaxial layer 103 is formed on the high-concentration impurity region 102.
For example, it is deposited and grown to a thickness of about 40 to 50 nm. After growing the silicon epitaxial layer 103, for example, SIMOX (Separation by Implanted Oxyge
The field oxide film 101 may be formed by the n) method, and thereafter, boron or the like may be introduced by the ion implantation method to form the high concentration impurity region 102 on the substrate surface side below the silicon epitaxial layer 103.

Then, the silicon epitaxial layer 103
In addition, micro MOS / LDD (Lightly Doped Drain) structure
Form an FET. That is, in FIG. 5B, a gate electrode 104 is formed on the silicon epitaxial layer 103 with a gate insulating film 105 interposed therebetween.
The n-type low-concentration impurity regions 106a and 106b are formed in the non-doped silicon epitaxial layer 103 by ion implantation using the mask 05 as a mask. Thereafter, spacer layers 107 are formed on both sides of the gate electrode 105, respectively, and a relatively high concentration of n is formed by ion implantation using the spacer layer 107 and the gate electrode 105 as a mask.
By introducing a type impurity from the surface of the silicon epitaxial layer 103 into the semiconductor substrate 100 below the high-concentration impurity region 102, a source region 108a and a drain region 108b are formed.

FIG.
In the fine MOS-FET having the structure shown in FIG. 1C, the channel is formed in the non-doped silicon epitaxial layer 103 during operation, the LDD structure is employed, and the high-concentration impurity region 102 is provided. The structure is such that the short channel effect is unlikely to occur.

[0012]

However, in the conventional semiconductor device having such a structure, although the short channel effect is suppressed to some extent, the junction capacitance between the source region 108a or the drain region 108b and the substrate 100 is reduced. There is a problem that the operation is insufficient, which hinders high-speed operation. That is, the epitaxial layer 103, L
Although the use of the LD structure and the high-concentration region 102 can provide a certain short-channel effect suppressing effect, the high-concentration source region 108a or the high-concentration source region 108b
However, since it is partially in contact with the high-concentration region 102 of the opposite conductivity type and also in contact with the substrate 100 at a wide portion, the junction capacitance at these portions is large, and in the case of a MOS. The structure could not be adopted.

The present invention has been made in view of the above circumstances, and a semiconductor device having a structure suitable for high-speed operation with a small junction capacitance between a source region and a drain region and a substrate, while solving the problem caused by the short channel effect. It is intended to provide a manufacturing method.

[0014]

In order to solve the above-mentioned problems of the prior art and achieve the above object, a semiconductor device according to the present invention comprises an epitaxial layer in contact with a semiconductor substrate and a surface of the epitaxial layer. A source region and a drain region that respectively reach at least the interface between the epitaxial layer and the semiconductor substrate and are separated from each other, wherein the source region and the drain region, and the source region and the drain region On the other hand, a low-concentration region having the same conductivity type as the substrate region and an impurity concentration lower than that of the substrate region is interposed between the region of the semiconductor substrate having the opposite conductivity type. .

In another semiconductor device according to the present invention, an epitaxial layer in contact with a semiconductor substrate, and a source reaching at least an interface between the epitaxial layer and the semiconductor substrate from a surface of the epitaxial layer and separated from each other. A semiconductor device having a region and a drain region, wherein the semiconductor substrate has an insulating layer in contact with the source region and the drain region from the back side in the substrate depth direction. This insulating layer
For example, it is composed of a deep insulating film formed by a SIMOX method.

In the semiconductor device of the present invention, since the channel is formed in the epitaxial layer, a surface channel is easily formed, which is effective for suppressing the short channel effect, and has good crystallinity and lowers carrier mobility. Is prevented.
Therefore, it is possible to obtain a high transconductance g _m, also relatively unaffected by the substrate bias.

Further, in the semiconductor device of the present invention, the junction capacitance between the source and the drain is reduced, and the structure is suitable for high-speed operation. That is, in the former semiconductor device described above, since the impurity concentration of the low-concentration region is lower than that of the substrate region, the junction between the source region or the drain region and the substrate region interposed therebetween is close to the inclined junction. And the capacitance is reduced as compared with the conventional case where no low concentration region is interposed. Further, since there is no high-concentration region which causes an increase in junction capacitance as in the related art, as a result, the junction capacitance of the source region and the drain region is significantly reduced. On the other hand, in the latter other semiconductor device, since the source region and the drain region are opposed to the substrate via the insulating layer, the junction capacitance can be made almost negligible in the substrate depth direction.

In the method of manufacturing a semiconductor device according to the present invention, when a low-concentration region is interposed between the former source or drain region and the substrate, the concentration profile on the deep side of the concentration profile of the source and drain regions is reduced. It is preferable that the concentration be set in advance so as to be lower than the concentration of the impurity introduced into the region of the semiconductor substrate, since the low concentration region can be formed at the same time when the source region and the drain region are formed.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to the present invention and a method for manufacturing the same will be described in detail with reference to the drawings.

First Embodiment FIG. 1 is a schematic sectional view showing one configuration example of a semiconductor device according to the present embodiment. In the figure, reference numeral 1 denotes a semiconductor device according to the present embodiment, 2 denotes a p-type semiconductor substrate region (here, the p-type semiconductor substrate itself), 3 denotes a field oxide film, 4 denotes a gate insulating film, and 5 denotes a gate insulating film. Gate electrode, 6a, 6b
Denotes a relatively low-concentration n-type low-concentration region (hereinafter referred to as an LDD region), 7 denotes a spacer layer, 8a denotes a relatively high-concentration n-type source region, and 8b denotes a relatively high-concentration n-type region. A drain region 9; an interlayer insulating film 9; and an electrode wiring layer 10 connected to the source region 8a and the like via a contact hole 9a. As described above, in the present invention, the region on the substrate surface side having the p-type for the nMOS and the n-type for the pMOS and the opposite conductivity type to the channel is defined as the “substrate region”.

The semiconductor device of the present invention has an epitaxial layer in contact with a semiconductor substrate. In the semiconductor device 1 illustrated in FIG. 1, almost the entire surface (active region) of the semiconductor substrate on which the field oxide film 3 is not formed,
Epitaxial layer 11 is formed selectively with respect to field oxide film 3.

In FIG. 1, the gate insulating film 4 is formed on the epitaxial layer 11, the gate electrode 5 is formed on the gate insulating film 4, and the spacer layers 7 are formed on both side walls thereof. ing. The LDD regions 6a and 6b are formed by introducing an n-type impurity at a relatively low concentration into the portion of the epitaxial layer 11 outside from below both edges of the gate electrode 5. As a result, the gate insulating film 4 is sandwiched between the LDD regions 6a and 6b.
Layer 11 opposed to gate electrode 5 through
The portion becomes a channel formation region of the semiconductor device.

Further, from the surface of the epitaxial layer 11 outside the one spacer layer 7 toward the substrate depth direction,
The source region 8a penetrates the interface between the epitaxial layer 11 and the semiconductor substrate region 2 and further reaches the inside of the semiconductor substrate region 2. Similarly, outside the other spacer layer 7, the drain region 8b is
One surface penetrates the interface and reaches the inside of the semiconductor substrate region 2.

In the semiconductor device 1 of the present invention according to this embodiment, the source region 8a or the drain region 8b and a substrate region of the opposite conductivity type (in FIG. 1, the p-type semiconductor substrate 2
Itself), has the same conductivity type as the substrate region 2,
The low-concentration regions 12a and 12b whose conductivity type is lower than that of the substrate region 2 are interposed. This low concentration area 12
With the interposition of a and 12b, the junction capacitance of the source region 8a and the drain region 8b is reduced. This is because a two-stage junction having a small impurity concentration difference is formed on both sides in the thickness direction of the low-concentration regions 12a and 12b. This is because it is reduced.

On the other hand, as described above, the semiconductor device 1 of the present invention is provided with the epitaxial layer 11 and the channel is formed in the epitaxial layer 11 because the crystallinity is good and the decrease in carrier mobility is prevented. from Rukoto, drivability, in particular in order to improve the mutual conductance g _m. The epitaxial layer 11 in the present invention may be p-type in the above example, but is preferably non-doped as described above. This is because a surface channel effective for suppressing the short channel effect is easily formed, and a reduction in withstand voltage and occurrence of punch-through in this portion can be effectively prevented. Further, a reduction in the junction capacitance at this portion can be expected, and it is hardly affected by the substrate bias.

Further, the reason why the LDD structure is adopted is that, as is well known, this structure prevents generation of hot electrons and is effective in suppressing a short channel effect. That is, the presence of the low-concentration LDD region 6b below the edge of the gate electrode 5, particularly on the drain side, makes it easy for the depletion layer to extend to the side opposite to the channel, thereby reducing the electric field. As a result, preventing a decrease of the mutual conductance g _m due to hot electron generation is achieved, and by the depletion layer hardly extends in the channel side, even complete the gate length of the dominant capacity of the gate electrode 5 is maintained Therefore, a decrease in the gate threshold voltage Vth is suppressed.

Next, a method of manufacturing a semiconductor device according to the present invention will be described by taking the semiconductor device 1 shown in FIG. 1 as an example. Here, FIGS. 2A to 2C are schematic cross-sectional views showing respective manufacturing steps of the semiconductor device 1. FIG. In FIG. 2A, first,
A semiconductor substrate 2 such as a silicon wafer is prepared. This semiconductor substrate 2 has an impurity species of, for example, boron (B).
A p-type substrate having a concentration of 1 × 10 ¹⁸ / cm ² or more is desirable. The semiconductor substrate 2 is not limited to this, and may have a configuration having a substrate region such as a p-well on the surface side.

Then, for example, L
The field oxide film 3 is selectively formed by using an OCOS (Local Oxidation of Silicon) method, and after removing an oxidation prevention film (not shown) used as a mask during the selective oxidation, the field oxide film 3 is formed. Epitaxial layer 11 selectively on the semiconductor substrate surface (active region) which is not
To form The selective formation of the epitaxial layer 11 is performed by, for example, Ultra-High Vacume CVD (Chemical Vapor D).
eposition) and molecular beam epitaxial growth. Preferably, it is undoped for the reasons described above. Next, when a thin insulating film is formed on the entire surface by using a thermal oxidation method or the like, the upper surface of the epitaxial layer 11 surrounded by the field oxide film 3 is coated with the gate oxide film 4. FIG. 2A shows the state after the oxidation.

In FIG. 2B, first, a gate electrode 5 is formed. The gate electrode 5 is formed by depositing a polysilicon film or the like over the entire surface by using, for example, a CVD method, and then doping the polysilicon film or the like with P (phosphorus) or the like to make it conductive.
Then, when the conductive polysilicon film is patterned into a predetermined shape by using the photolithography technique and the etching technique, the gate electrode 5 is formed as shown in FIG. Note that the gate oxide film 4 in this case is left on the entire surface of the epitaxial layer 11 to be used as a through film at the time of subsequent ion implantation, but is processed together with the gate electrode 5 and the gate oxide film 4 around the electrode is removed. Is also good.

Next, LDD regions 6a and 6b are formed in epitaxial layer 11 by ion implantation using gate electrode 5 and field oxide film 3 as a mask.
Specifically, after implanting, for example, arsenic (As) ions, a heat treatment for electrically activating the implanted ions is performed. Thus, the two LDD regions 6a and 6b opposed to each other with the channel formation region interposed therebetween are formed in the epitaxial layer 11.
Are formed in a self-aligned manner with respect to the gate electrode 5. FIG. 2B shows a state after the LDD regions 6a and 6b are formed.

In FIG. 2C, first, the spacer layer 7 is formed. Specifically, for example, a silicon oxide film or the like is formed on the entire surface, and anisotropic etching is performed by, for example, RIE (Reactive Ion Etching). Thereby, the spacer layers 7 are formed on both sides of the gate electrode 5 as shown. Subsequently, by ion implantation using the spacer layer 7, the gate electrode 5, and the field oxide film 3 as a mask,
The source region 8a and the drain region 8b are L
In the cross section, the LD region 6a, 6b
It is formed so as to reach the inside of the semiconductor substrate 2 deeper than the D regions 6a and 6b. Specifically, for example, after As ions or P ions are implanted at a relatively high concentration, a heat treatment for electrically activating the implanted ions is performed.

In the method of manufacturing a semiconductor device according to the present invention, the concentration profile of the second ion implantation is such that the deeper side in the semiconductor substrate 2 has at least partially a p-type substrate region 2.
Is set to be lower than the impurity concentration introduced. For this reason, in this embodiment, a relatively low-concentration n-type source region and a drain region are formed on the front surface side in the semiconductor substrate 2, and between the source region and the drain region and the substrate region 2. Then, the aforementioned p-type low concentration regions 12a and 12b are formed. Note that, depending on the concentration profile of the ion implantation, a relatively low concentration n-type source region and drain region may not be formed.

Thereafter, as shown in FIG.
Is formed on the entire surface, and contact holes 9 a are formed in the interlayer insulating film 9.
Is formed, the source region 8 is formed through the contact hole 9a.
The electrode wiring layer 10 is formed while being connected to a and the like, and is processed and formed. Then, although not particularly shown, the semiconductor device 1 is completed through formation of a protective layer, opening of a pad window, and the like.

According to the method of manufacturing a semiconductor device of the present invention,
As described above, the source region 8a and the drain region 8
Since the concentration profile at the time of the ion implantation for forming b is set at least partially lower than the concentration of the substrate region 2 inside the substrate, only by performing this ion implantation, the bonding between the substrate region 2 The low-concentration regions 12a and 12b that are effective in reducing the capacity can be formed. When it is desired to increase the thickness of the low-concentration regions 12a and 12b in the depth direction of the substrate, for example,
In setting the concentration profile when forming the a and drain regions 8b, such thick low concentration regions 12a, 12
When b cannot be obtained, a method may be employed in which low-concentration n-type impurity ions are deeply implanted, and then high-concentration n-type impurity ions are shallowly implanted to perform twice ion implantation. .

Second Embodiment This embodiment is a case where an insulating layer is provided to reduce the junction capacitance. FIG. 3 is a schematic cross-sectional view showing one configuration example of the semiconductor device according to the present embodiment. Here, the same components as those in the first embodiment described above are denoted by the same reference numerals.
The description is omitted.

In the semiconductor device of this embodiment, a semiconductor substrate having a lower concentration than that of the first embodiment can be used as the semiconductor substrate 2. The epitaxial layer 11 is formed on the semiconductor substrate 2. In the semiconductor device of the present embodiment, unlike the first embodiment, the insulating layer 13 is provided in the semiconductor substrate 2 below the epitaxial layer 11.
Is formed, and the source region 8a and the drain region 8b are in contact with the insulating layer 13. For this reason, the junction capacitance of the source region 8a and the drain region 8b in the substrate depth direction is so small as to be almost negligible.

The insulating layer 13 shown in FIG. 3 is formed in the middle of the substrate in the depth direction, but this is not essential in the present invention.
Substrate area (in this case, the semiconductor substrate 2 itself) immediately below
May be interposed. The reason why the insulating layer 13 is formed in the middle of the substrate in the depth direction is, for example, that the epitaxial layer 11
It is sufficient if the layer has a thickness enough to form a channel in the epitaxial layer 11, which is because the epitaxial growth cost can be reduced.

Such an SOI (Silicon On Insulator)
In the element type device structure, generally, in addition to the junction capacitance, the capacitance of the insulating film and the capacitance of the depletion layer beneath the insulating film constitute the capacitance of the source and drain diffusion layers that govern the high-speed performance of the device. Is added. As described above, the junction capacitance is so small as to be almost negligible, and the capacitance of the insulating film and the capacitance of the depletion layer have a normal element structure, that is, SOI.
Since the junction capacitance in the case of a non-type is orders of magnitude smaller, the impurity diffusion capacitance in the source region and the drain region is greatly reduced. The reason for introducing the epitaxial layer 11, the reason why it is non-doped, and the reason why the LDD composition is adopted are the same as those in the first embodiment.

Finally, a method of manufacturing a semiconductor device having the SOI element structure will be briefly described with reference to the drawings. Here, FIGS. 4A to 4C are schematic cross-sectional views showing respective manufacturing steps of the semiconductor device. In addition,
Also in the description here, the description of the formation and the like of the same configuration as the first embodiment described above is omitted. FIG.
2A is the same as FIG. 2A except that the semiconductor substrate 2 has a relatively low concentration.

In FIG. 4B, the insulating layer 13 is formed on the semiconductor substrate 2 in the depth direction. This insulating layer 13
Is formed by a SIMOX method. In the SIMOX method, after an oxidizing agent is supplied deep into a substrate, oxidation is advanced by heat treatment,
In a method of forming an oxide layer deep in a substrate, oxygen ions are usually used as an oxidizing agent, and an ion implantation method is used as a supply method.

The insulating layer 13 may be formed by the SIMOX method prior to the epitaxial growth shown in FIG. Generally, damage is likely to be introduced into the surface side of the semiconductor substrate during ion implantation for supplying an oxidant, and the crystallinity of epitaxial growth performed on the substrate after the introduction of the damage may be disturbed. On the other hand, if the insulating layer is formed by the SIMOX method after the formation of the epitaxial layer, damage is likely to be introduced into the epitaxial layer. Which of the epitaxial growth and the formation of the insulating layer by the SIMOX method is performed first is determined in consideration of these.

In FIG. 4C, a gate electrode 5 is formed on the gate insulating film 4 by the same method as in the first embodiment, and LDD regions 6a and 6b are formed using the gate electrode 5 and the field oxide film 3 as a mask. . Further, the spacer layer 7 shown in FIG. 3 is formed by the same method as in the first embodiment, and the spacer layer 7, the gate electrode 5, and the field oxide film 3 are formed.
Is used as a mask, ions of an n-type impurity are implanted at a relatively high concentration to form a source region 8a and a drain region 8b reaching the insulating layer 13 buried in the lower layer. Thereafter, the semiconductor device is completed through the formation of an interlayer insulating film (not shown), contact formation, electrode wiring, opening of a pad window, and the like.

In the method of manufacturing a semiconductor device according to the present embodiment,
Relatively simple SI such as one ion implantation and heat treatment
The insulating layer is formed deep in the substrate by the MOX method, so that the junction capacitance and the diffusion layer capacitance of the source and drain regions can be significantly reduced.

[0044]

As described above, according to the semiconductor device and the method of manufacturing the same according to the present invention, the junction capacitance between the source and drain regions and the substrate is reduced while eliminating the adverse effects caused by the short channel effect. It is possible to provide a semiconductor device having a structure suitable for integration and a method for manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing one configuration example of a semiconductor device according to a first embodiment of the present invention.

2 (a) to 2 (c) are schematic cross-sectional views showing respective manufacturing steps of the semiconductor device of FIG.

FIG. 3 is a schematic cross-sectional view illustrating one configuration example of a semiconductor device according to a second embodiment of the present invention.

4 (a) to 4 (c) are schematic cross-sectional views showing respective manufacturing steps of the semiconductor device of FIG.

FIG. 5 is a schematic cross-sectional view showing each process of manufacturing a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Semiconductor substrate (substrate area), 3 ... Field oxide film, 4 ... Gate insulating film, 5 ... Gate electrode,
6a, 6b: LDD region (other low concentration region), 7: spacer layer, 8a: source region, 8b: drain region, 9:
Interlayer insulating film, 9a: contact hole, 10: electrode wiring layer,
11: epitaxial layer, 12a, 12b: low concentration region, 13: insulating layer (deep oxide film).

Claims (9)

[Claims] An epitaxial layer in contact with a semiconductor substrate; a source region and a drain region reaching at least an interface between the epitaxial layer and the semiconductor substrate from a surface of the epitaxial layer and separated from each other;
A semiconductor device having the same conductivity type as the substrate region between the source region and the drain region, and a region of the semiconductor substrate having an opposite conductivity type to the source region and the drain region; A semiconductor device in which low-concentration regions each having a lower impurity concentration than the substrate region are interposed. 2. A low-concentration region having a lower impurity concentration than the source region and the drain region in a predetermined width from both sides in the opposing direction in the epitaxial layer within an opposing interval between the source region and the drain region. 2. The semiconductor device according to claim 1, wherein the semiconductor device extends inward. 3. An epitaxial layer in contact with a semiconductor substrate; a source region and a drain region reaching at least an interface between the epitaxial layer and the semiconductor substrate from a surface of the epitaxial layer and separated from each other;
A semiconductor device comprising: an insulating layer in the semiconductor substrate, the insulating layer being in contact with the source region and the drain region from a depth side in a substrate depth direction. 4. The semiconductor device according to claim 3, wherein said insulating layer is formed of a deep oxide film located halfway in a depth direction of said semiconductor substrate. 5. After forming an epitaxial layer on a first conductivity type region located on a surface side in a semiconductor substrate, when forming a source region and a drain region at a distance from each other, the surface of the epitaxial layer is A method of manufacturing a semiconductor device, wherein a second conductivity type impurity is introduced so as to reach an inside of the first conductivity type region, wherein the concentration profile of the second conductivity type impurity is a concentration deeper than the epitaxial layer. Is at least partially set to be lower than the impurity concentration introduced into the first conductivity type region. 6. The method according to claim 1, wherein after forming the epitaxial layer, a second impurity concentration is lower than that of the source region and the drain region.
6. The method according to claim 5, wherein the low-concentration regions of the conductivity type are formed at a distance from each other, and thereafter, the source region or the drain region is formed outside of the low-concentration region in the facing direction at a predetermined distance from each of the opposing surfaces. The manufacturing method of the semiconductor device described in the above. 7. A method for manufacturing a semiconductor device, comprising: forming an epitaxial layer on a semiconductor substrate; and forming a source region and a drain region at a distance from each other in a direction from the surface of the epitaxial layer toward the semiconductor substrate. Prior to the formation of the region and the drain region,
A method for manufacturing a semiconductor device, wherein an insulating layer is formed in advance in the semiconductor substrate, and thereafter, the source region and the drain region are formed from a surface of the epitaxial layer to an upper surface of the insulating layer. 8. The method of manufacturing a semiconductor device according to claim 7, wherein in forming the insulating layer, a heat treatment is performed after an oxidizing agent is supplied in the depth direction of the semiconductor substrate. 9. After forming the epitaxial layer, a second impurity concentration lower than that of the source region and the drain region.
A low-concentration region of conductivity type is formed in the epitaxial layer at a distance from each other, and thereafter, the source region or the drain region is formed outside the low-concentration region in a direction opposite to the low-concentration region at a predetermined distance from each of the opposing surfaces. The method of manufacturing a semiconductor device according to claim 7.