JPH10144825A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

Info

Publication number
JPH10144825A
JPH10144825A JP8303189A JP30318996A JPH10144825A JP H10144825 A JPH10144825 A JP H10144825A JP 8303189 A JP8303189 A JP 8303189A JP 30318996 A JP30318996 A JP 30318996A JP H10144825 A JPH10144825 A JP H10144825A
Authority
JP
Japan
Prior art keywords
resin
conductive bump
semiconductor device
semiconductor element
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP8303189A
Other languages
Japanese (ja)
Inventor
Satoyuki Ando
智行 安藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP8303189A priority Critical patent/JPH10144825A/en
Publication of JPH10144825A publication Critical patent/JPH10144825A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device and its manufacturing method, with which the semiconductor device can be manufactured at a high yield rate. SOLUTION: This semiconductor device is provided with a semiconductor element 6 where electrodes 6a are formed on one main surface, conductive bumps 7 which are connected to and arranged on the surface of the above- mentioned electrodes 6a, and a resin layer 8 which fills up the region where the above-mentioned conductive bumps 7 are provides and cover the tip face of the conductive bumps 7. In this manufacturing method, the conductive bumps 7 are provided on the surface of the electrodes 6a of the semiconductor element 6, the surface having the conductive bumps 7 is dipped into fludized resin 10, the resin 10 is adhered to the conductive bumps 7, and the adhered resin 10 is hardened.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は樹脂封止型の半導体
装置およびその製造方法の改良に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device and an improvement in a method of manufacturing the same.

【0002】[0002]

【従来の技術】電子回路機構のコンパクト化などを目指
し、図5に要部構成を断面的に示すような樹脂封止型の
半導体装置が開発されている。すなわち、インナーリー
ド1aおよびダイパッド1bを有するリードフレーム1と、
前記リードフレーム1のダイパッド1bに接着剤層2を介
してマウントされた半導体素子3と、前記半導体素子3
の一主面に配設された電極3aおよびインナーリード1aを
対応させて接続するボンディングワイヤ4と、前記ボン
ディングワイヤ4を含めて半導体素子3を被覆・封止す
るモールド樹脂層5を有する半導体装置が知られてい
る。
2. Description of the Related Art A resin-encapsulated semiconductor device whose main part is shown in cross section in FIG. That is, a lead frame 1 having an inner lead 1a and a die pad 1b,
A semiconductor element 3 mounted on a die pad 1b of the lead frame 1 via an adhesive layer 2;
Semiconductor device having a bonding wire 4 for connecting the electrode 3a and the inner lead 1a corresponding to each other disposed on one principal surface thereof, and a mold resin layer 5 for covering and sealing the semiconductor element 3 including the bonding wire 4 It has been known.

【0003】また、この種の樹脂封止型半導体装置は、
たとえば図6に示すフローチャートのような手順で、組
み立て・製造している。先ず、一主面に所要の電極3aを
設けた半導体素子3をウエハーからダイシング分離した
後、予め用意しておいた所定のリードフレーム1のダイ
パッド1b上に、接着剤層2を介してマウントする。
Further, this type of resin-sealed semiconductor device is
For example, assembling and manufacturing are performed according to the procedure shown in the flowchart of FIG. First, after dicing and separating a semiconductor element 3 having a required electrode 3a on one principal surface from a wafer, the semiconductor element 3 is mounted on a die pad 1b of a predetermined lead frame 1 prepared in advance via an adhesive layer 2. .

【0004】次いで、マウントした半導体素子3の電極
群と、リードフレーム1の対応するインナーリード1bと
をワイヤボンディングし、電気的に接続する。その後、
モールド用金型に装着し、トランスファーモールド成型
機にセットして、前記ボンディングワイヤ4およびイン
ナーリード1bの一部を含めて、マウントした半導体素子
3領域を樹脂モールドする。この樹脂モールド品につい
て、モールド樹脂層5に生じたバリを除去し、リードフ
レーム1に外装メッキなどを施してから、マーク付けす
ることにより封止型半導体装置を得ている。
Next, the electrode group of the mounted semiconductor element 3 is electrically connected to the corresponding inner lead 1b of the lead frame 1 by wire bonding. afterwards,
It is mounted on a molding die, set in a transfer molding machine, and resin-molded in the mounted semiconductor element 3 region, including the bonding wire 4 and a part of the inner lead 1b. With respect to this resin molded product, the encapsulation type semiconductor device is obtained by removing burrs generated in the mold resin layer 5, applying exterior plating to the lead frame 1, and then marking.

【0005】[0005]

【発明が解決しようとする課題】しかし、上記構成の半
導体装置は、外部環境からの保護および薄型化など容易
に図られ、また、取扱も容易であるという利点を有する
が、一方では、コンパクト化の点が十分でなく、かつ製
造工程が煩雑であるという問題がある。先ず、構造的な
面では、リードフレーム1にマウントし、かつインナー
リード1aを外周方向に延出させているため、必然的に、
平面的な広がりが大きくなり、コンパクト化が阻害され
る。
However, the semiconductor device having the above structure has advantages that it can be easily protected from the external environment and that it is made thin, and that it is easy to handle. Are not sufficient, and the manufacturing process is complicated. First, in terms of structure, since it is mounted on the lead frame 1 and the inner leads 1a extend in the outer peripheral direction,
The planar spread becomes large, and compactness is hindered.

【0006】次に、製造・組み立て工程では、工程数が
多く煩雑で、生産性が低くいだけでなく、工程ごとに専
用の装置、さらに、品種ごとに専用の金型などを必要と
するため、製造コストも大幅にアップするという問題が
ある。特に、多工程およびその煩雑性は、製品の信頼性
もしくは歩留まりなどを損なう要因となるので、製造面
では由々しいことである。
Next, in the manufacturing / assembly process, the number of processes is large and complicated, and not only is the productivity low, but also a dedicated device for each process and a dedicated mold for each product are required. However, there is a problem that the manufacturing cost is significantly increased. In particular, since the number of steps and the complexity of the steps are factors that impair the reliability or yield of the product, it is serious in terms of manufacturing.

【0007】本発明は上記事情に対処してなされたもの
で、薄型・コンパクトで、信頼性の高い半導体装置、お
よびこのような半導体装置を歩留まりよく製造できる製
造方法の提供を目的とする。
The present invention has been made in view of the above circumstances, and has as its object to provide a thin, compact, highly reliable semiconductor device and a manufacturing method capable of manufacturing such a semiconductor device with high yield.

【0008】[0008]

【課題を解決するための手段】請求項1の発明は、一主
面に電極が設けられた半導体素子と、前記各電極面に接
続配置された導電性バンプと、前記導電性バンプが設け
られた領域を充填し、かつ導電性バンプ先端面を被覆す
る樹脂層とを有することを特徴とする半導体装置であ
る。
According to a first aspect of the present invention, there is provided a semiconductor device having an electrode on one principal surface, a conductive bump connected to each of the electrode surfaces, and the conductive bump. And a resin layer that fills the exposed region and covers the front end surface of the conductive bump.

【0009】請求項2の発明は、半導体素子の電極面に
導電性バンプを設ける工程と、前記導電性バンプを設け
た面を流動性樹脂中に浸漬し、導電性バンプ領域に樹脂
を充填・付着させる工程と、前記充填・付着させた樹脂
を硬化させる工程とを有することを特徴とする半導体装
置の製造方法である。
According to a second aspect of the present invention, there is provided a step of providing a conductive bump on an electrode surface of a semiconductor element, immersing the surface provided with the conductive bump in a fluid resin, and filling the conductive bump region with the resin. A method of manufacturing a semiconductor device, comprising a step of adhering and a step of curing the filled and adhered resin.

【0010】請求項3の発明は、半導体素子の電極面に
導電性バンプを設ける工程と、前記導電性バンプを設け
た面を流動性樹脂中に浸漬し、導電性バンプ領域に樹脂
を充填・付着させる工程と、前記充填・付着させた樹脂
を硬化させた後、導電性バンプの先端面側を平坦面化加
工し、導電性バンプの先端部を露出させる工程とを有す
ることを特徴とする半導体装置の製造方法である。
According to a third aspect of the present invention, there is provided a step of providing a conductive bump on an electrode surface of a semiconductor element, immersing the surface provided with the conductive bump in a fluid resin, and filling the conductive bump region with the resin. And a step of, after curing the filled and adhered resin, flattening the front end side of the conductive bump to expose the front end of the conductive bump. 6 shows a method for manufacturing a semiconductor device.

【0011】請求項4の発明は、請求項2もしくは請求
項3記載の半導体装置の製造方法において、流動性樹脂
中に半導体素子を浸漬するとき、半導体素子の裏面側を
吸着パッドで保持することを特徴とする。
According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the second or third aspect, when the semiconductor element is immersed in the fluid resin, the back surface of the semiconductor element is held by a suction pad. It is characterized by.

【0012】請求項1の発明では、半導体装置の構成に
おいて、半導体素子の電極面上に導電性バンプを設け、
この導電性バンプを埋め込む形に樹脂を充填・被覆させ
る構成を骨子としている。そして、前記封止用樹脂の充
填・被覆によって、半導体素子の電極面から導出させた
導電性バンプ先端部を外部環境から保護し、さらに、そ
れら導電性バンプ間の絶縁・隔離を容易に確保する一
方、取扱易く、かつ薄型・コンパクト化などが図られ
る。
According to the first aspect of the present invention, in the configuration of the semiconductor device, a conductive bump is provided on an electrode surface of the semiconductor element.
The configuration in which the resin is filled and covered so as to embed the conductive bumps is the main point. The filling and coating of the sealing resin protects the tip of the conductive bump derived from the electrode surface of the semiconductor element from the external environment, and easily secures insulation and isolation between the conductive bumps. On the other hand, it is easy to handle, and thin and compact.

【0013】請求項2の発明では、ディップ法によって
導電性バンプを設けた領域が樹脂で充填・付着され、か
つ硬化によってモールド封止することを骨子としてい
る。このような手段を採ることによって、薄型・コンパ
クトで、導電性バンプの防錆などが行われ、保存可能で
取扱易いモールド封止型の半導体装置が量産的、かつ歩
留まりよく提供される。
According to the second aspect of the present invention, it is essential that a region provided with conductive bumps is filled and adhered with a resin by a dipping method, and is molded and cured by curing. By adopting such a means, a thin and compact mold-sealed semiconductor device that can prevent rust of the conductive bumps and is storable and easy to handle is provided in mass production and with high yield.

【0014】請求項3の発明では、ディップ法によって
導電性バンプを設けた領域が樹脂で充填・付着され、硬
化によってモールド封止した後、導電性バンプ側を平坦
面化させることを骨子としている。このような手段を採
ることによって、薄型・コンパクトで、信頼性の高い実
装が可能なモールド封止型の半導体装置が歩留まりよく
提供される。
According to the third aspect of the invention, the outline is to flatten the conductive bump side after filling and adhering the area where the conductive bump is provided with resin by the dipping method, and molding and curing the area by curing. . By employing such means, a thin and compact mold-sealed semiconductor device that can be mounted with high reliability is provided with high yield.

【0015】請求項4の発明では、前記請求項2もしく
は請求項3の半導体装置の製造方法が、より容易に達成
される。
According to a fourth aspect of the present invention, the method of manufacturing a semiconductor device according to the second or third aspect is more easily achieved.

【0016】[0016]

【発明の実施の形態】本発明において、半導体素子は、
一主面の周辺部もしくは全面に、多くの電極(接続端
子)が導出された IC 素子であり、その形状・大きさな
どは限定されない。また、前記電極面上に設けられた導
電性バンプは、たとえばInBi半田、InSn半田、InBiSn半
田もしくはAuなどを素材として形成され、その形状も円
柱状、鼓状、球状もしくは楕円状のいずれでもよい。
DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a semiconductor device
This is an IC element with many electrodes (connection terminals) led out on the periphery or the entire surface of one main surface, and its shape and size are not limited. Further, the conductive bumps provided on the electrode surface are formed using, for example, InBi solder, InSn solder, InBiSn solder or Au as a material, and the shape thereof may be a columnar shape, a drum shape, a spherical shape, or an elliptical shape. .

【0017】本発明において、半導体素子の導電性バン
プが設けられた領域を充填・付着する流動性樹脂として
は、室温もしくは加熱された状態で流動性を呈する熱硬
化性樹脂、たとえばエポキシ樹脂類、ポリイミド樹脂類
などが挙げられる。そして、流動性樹脂中に浸漬し、導
電性バンプ領域を充填・付着したときもしくは充填・被
覆したとき、半導体素子主面の周辺部にのみに導電性バ
ンプが設けられている場合は中央部が凹状に、また、半
導体素子主面の全面に導電性バンプが設けられている場
合は平坦状をそれぞれ採ることになる。しかし、いずれ
の場合も、導電性バンプが設けられた領域は、ほぼ一様
の高さの樹脂層によって充填・被覆され、各導電性バン
プは外部雰囲気から遮断されながら、導電性バンプ同士
の絶縁なども行われる。
In the present invention, the fluid resin that fills and adheres to the region of the semiconductor element where the conductive bumps are provided is a thermosetting resin that exhibits fluidity at room temperature or in a heated state, such as an epoxy resin. Examples include polyimide resins. When immersed in a fluid resin to fill / adhere or fill / cover the conductive bump region, if the conductive bump is provided only on the peripheral portion of the semiconductor element main surface, the center portion is When a conductive bump is provided on the entire surface of the semiconductor element main surface, the semiconductor element has a flat shape. However, in each case, the area where the conductive bumps are provided is filled and covered with a resin layer having a substantially uniform height, and each conductive bump is isolated from the external atmosphere while insulating the conductive bumps from each other. And so on.

【0018】次に、図1,図2 (a), (b),図3および
図4を参照して実施例を説明する。図1は半導体装置の
要部構成を断面的に示したものである。図1において、
6は一主面に電極6aが設けられた半導体素子、7は前記
半導体素子6の各電極6a面に接続配置された導電性バン
プ、8は前記導電性バンプ7が設けられた領域を充填
し、かつ導電性バンプ8先端面を被覆する樹脂層であ
る。ここで、半導体素子6はICチップ、導電性バンプ7
はInSn半田製の鼓形、樹脂層8はエポキシ樹脂で形成さ
れている。
Next, an embodiment will be described with reference to FIGS. 1 and 2 (a) and (b), FIG. 3 and FIG. FIG. 1 is a cross-sectional view illustrating a configuration of a main part of a semiconductor device. In FIG.
Reference numeral 6 denotes a semiconductor element having an electrode 6a provided on one main surface, 7 denotes a conductive bump connected to and disposed on each electrode 6a surface of the semiconductor element 6, and 8 denotes a region filling the area where the conductive bump 7 is provided. And a resin layer that covers the front end surface of the conductive bump 8. Here, the semiconductor element 6 is an IC chip, a conductive bump 7
Is a drum shape made of InSn solder, and the resin layer 8 is formed of epoxy resin.

【0019】この半導体装置の構成では、半導体素子6
の電極6aおよび導電性バンプ7が樹脂層8によって互に
隔絶し、かつ導電性バンプ7の先端部が樹脂層8で被覆
されているため、導電性バンプ7の酸化など防止され
る。そして、使用に先立って、導電性バンプ7領域を充
填・被覆する樹脂層8面をラッピングし、導電性バンプ
7の清浄面を露出させて接合することにより、電気的に
信頼性の高い接続・実装を行うことができる。
In the structure of this semiconductor device, the semiconductor element 6
The electrode 6a and the conductive bump 7 are isolated from each other by the resin layer 8, and the tip of the conductive bump 7 is covered with the resin layer 8, so that the conductive bump 7 is prevented from being oxidized. Prior to use, the surface of the resin layer 8 that fills and covers the conductive bumps 7 is wrapped, and the clean surface of the conductive bumps 7 is exposed and joined to form a highly reliable connection / connection. Implementation can be performed.

【0020】図2 (a), (b)は、半導体装置の製造方法
の実施態様を模式的に示し、また、図3は実施手順を示
すフローチャート図である。先ず、図2 (a)に平面的に
示すように、所要の半導体素子(たとえばICチップ)6
の電極6a面に導電性バンプ7を設ける。次いで、図2
(b)に断面的に示すように、半導体素子6を、その裏面
側で吸着パッド9で保持し、前記導電性バンプ7を設け
た面を流動性樹脂(たとえばエポキシ樹脂)10中に浸漬
する。なお、図2 (b)において、11は浸漬用の流動性樹
脂を収容する容器を示す。
FIGS. 2A and 2B schematically show an embodiment of a method of manufacturing a semiconductor device, and FIG. 3 is a flow chart showing an execution procedure. First, as shown in a plan view in FIG. 2A, a required semiconductor element (for example, an IC chip) 6
A conductive bump 7 is provided on the surface of the electrode 6a. Then, FIG.
As shown in cross section in FIG. 2B, the semiconductor element 6 is held by the suction pad 9 on the back surface side, and the surface provided with the conductive bumps 7 is immersed in a fluid resin (for example, epoxy resin) 10. . In FIG. 2 (b), reference numeral 11 denotes a container for housing a fluid resin for immersion.

【0021】この選択的な浸漬処理によって、導電性バ
ンプ7を設けた領域に樹脂を充填・付着させた後、流動
性樹脂10中から引上げ、充填・付着させた樹脂を乾燥・
加熱硬化させることにより、図1に図示したような構成
の半導体装置が製造され、その後、半導体装置にマーク
付けし、梱包、出荷される。そして、ユーザーが使用す
るとき、すなわち配線基板などに実装する段階で、導電
性バンプ7先端側の樹脂層8をラッピング除去し、導電
性バンプ7先端を露出させる。
After the resin is filled and adhered to the area where the conductive bumps 7 are provided by this selective immersion treatment, the resin is pulled up from the fluid resin 10 and the filled and adhered resin is dried and dried.
By heating and curing, a semiconductor device having a configuration as shown in FIG. 1 is manufactured, and thereafter, the semiconductor device is marked, packed, and shipped. Then, at the time of use by a user, that is, at the stage of mounting on a wiring board or the like, the resin layer 8 on the tip side of the conductive bump 7 is removed by lapping to expose the tip of the conductive bump 7.

【0022】つまり、一般的には、使用する段階まで導
電性バンプ7は全体的に樹脂層8で被覆され、酸化層の
形成もしくは生成が防止されている。したがって、酸化
膜の除去など煩雑な処理を要せずに、信頼性の高い半田
付け接合を確実に形成することができる。
That is, generally, the conductive bump 7 is entirely covered with the resin layer 8 until the stage of use, so that formation or formation of an oxide layer is prevented. Therefore, reliable soldering can be reliably formed without complicated processing such as removal of an oxide film.

【0023】図4 (a), (b)は、他の半導体装置の製造
方法の実施態様を模式的に示すものである。この例で
は、一主面の周辺部に電極6aが配置され、この電極6a面
に導電性バンプ7を設けたICチップ6を対象としてい
る。そして、この実施例の場合は、図4 (a)に平面的に
示すように、導電性バンプ7を設けた領域が周辺部のみ
であるため、樹脂層8を充填・被覆した構成では、図4
(b)に、図4 (a)の A-A線に沿った断面を示すごとく、
導電性バンプ7が存在しない中央部領域が凹面化してお
り、かつこの領域は薄い樹脂層8で被覆されている。な
お、この場合の製造手順は、図3に示すフローチャート
に準ずるので、説明を省略する。
FIGS. 4A and 4B schematically show another embodiment of a method for manufacturing a semiconductor device. In this example, the electrode 6a is arranged on the peripheral portion of one main surface, and the IC chip 6 in which the conductive bumps 7 are provided on the surface of the electrode 6a is targeted. In the case of this embodiment, as shown in a plan view in FIG. 4A, the region where the conductive bumps 7 are provided is only the peripheral portion. 4
FIG. 4B shows a cross section taken along the line AA in FIG.
The central area where the conductive bumps 7 are not present is concave, and this area is covered with a thin resin layer 8. Since the manufacturing procedure in this case conforms to the flowchart shown in FIG. 3, the description will be omitted.

【0024】なお、本発明は上記実施例に限定されるも
のでなく、発明の趣旨を逸脱しない範囲でいろいろの変
形を採ることができる。たとえば流動性樹脂中に、導電
性バンプを設けた領域を浸漬するときの半導体素子の保
持は、吸着パッド以外の他の手段で行うことができる。
The present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention. For example, the holding of the semiconductor element when the area provided with the conductive bumps is immersed in the fluid resin can be performed by means other than the suction pad.

【0025】[0025]

【発明の効果】請求項1の発明によれば、封止用樹脂の
充填・被覆によって、導電性バンプ先端部が外部環境か
ら保護され、かつ導電性バンプ同士の絶縁・隔離も確保
されている。すなわち、配線基板などへの実装に当たっ
て、ラッピングによって清浄な導電性バンプ面を露出さ
せ、所要の接続を容易に行うことができるので、取扱い
易いだけでなく、信頼性の高い電気的な接続が可能とな
って、実装回路装置の歩留まりなどに大きく寄与する。
According to the first aspect of the present invention, the filling and covering of the sealing resin protects the tip of the conductive bump from the external environment, and secures the insulation and isolation between the conductive bumps. . In other words, when mounting on a wiring board, etc., the required conductive connection can be easily made by exposing the clean conductive bump surface by lapping, so that not only easy handling but also highly reliable electrical connection is possible. This greatly contributes to the yield of the mounted circuit device.

【0026】請求項2ないし4の発明によれば、配線基
板などへの実装に当たって、ラッピングによって清浄な
導電性バンプ面を露出させ、所要の接続を容易に行うこ
とができる信頼性の高い電気的な接続が可能な半導体装
置を歩留まりよく提供できる。
According to the second to fourth aspects of the present invention, when mounting on a wiring board or the like, a reliable conductive bump surface is exposed by lapping, and required electrical connection can be easily performed. It is possible to provide a semiconductor device capable of performing a simple connection with a high yield.

【図面の簡単な説明】[Brief description of the drawings]

【図1】実施例の半導体装置の要部構成を示す断面図。FIG. 1 is a cross-sectional view illustrating a main configuration of a semiconductor device according to an embodiment.

【図2】実施例の半導体装置の製造工程の態様を模式的
に示すもので、 (a)は導電性バンプを設けた半導体素子
の平面図、 (b)は流動性樹脂中に導電性バンプ付け半導
体素子を浸漬した状態を示す断面図。
FIGS. 2A and 2B schematically show a manufacturing process of a semiconductor device according to an embodiment. FIG. 2A is a plan view of a semiconductor element provided with conductive bumps, and FIG. Sectional drawing which shows the state which immersed the attached semiconductor element.

【図3】実施例の半導体装置の製造工程手順を示すフロ
ーチャート図。
FIG. 3 is a flowchart showing a manufacturing process procedure of the semiconductor device of the embodiment.

【図4】他の実施例の半導体装置の製造工程の態様を模
式的に示すもので、 (a)は導電性バンプを設けた半導体
素子の平面図、 (b)は流動性樹脂を導電性バンプ領域に
充填・被覆した状態を示す断面図。
FIGS. 4A and 4B schematically show a manufacturing process of a semiconductor device according to another embodiment. FIG. 4A is a plan view of a semiconductor element provided with conductive bumps, and FIG. Sectional drawing which shows the state which filled and covered the bump area | region.

【図5】従来の半導体装置の構成例を示す断面図。FIG. 5 is a cross-sectional view illustrating a configuration example of a conventional semiconductor device.

【図6】従来の半導体装置の製造工程手順を示すフロー
チャート図。
FIG. 6 is a flowchart showing a conventional semiconductor device manufacturing process procedure.

【符号の説明】[Explanation of symbols]

6……半導体素子 6a……電極 7……導電性バンプ 8……充填・被覆樹脂層 9……吸着パッド 10……流動性樹脂 11……樹脂用容器 6 Semiconductor element 6a Electrode 7 Conductive bump 8 Filling / coating resin layer 9 Adsorption pad 10 Fluid resin 11 Container for resin

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 一主面に電極が設けられた半導体素子
と、 前記各電極面に接続配置された導電性バンプと、 前記導電性バンプが設けられた領域を充填し、かつ導電
性バンプ先端面を被覆する樹脂層と、を有することを特
徴とする半導体装置。
A semiconductor element having an electrode provided on one principal surface thereof; a conductive bump connected to each of the electrode surfaces; and a conductive bump tip for filling a region provided with the conductive bump. And a resin layer covering the surface.
【請求項2】 半導体素子の電極面に導電性バンプを設
ける工程と、 前記導電性バンプを設けた面を流動性樹脂中に浸漬し、
導電性バンプ領域に樹脂を充填・付着させる工程と、 前記充填・付着させた樹脂を硬化させる工程とを有する
ことを特徴とする半導体装置の製造方法。
2. A step of providing a conductive bump on an electrode surface of a semiconductor element, immersing the surface provided with the conductive bump in a fluid resin,
A method for manufacturing a semiconductor device, comprising: a step of filling and attaching a resin to a conductive bump region; and a step of curing the filled and attached resin.
【請求項3】 半導体素子の電極面に導電性バンプを設
ける工程と、 前記導電性バンプを設けた面を流動性樹脂中に浸漬し、
導電性バンプ領域に樹脂を充填・付着させる工程と、 前記充填・付着させた樹脂を硬化させた後、導電性バン
プの先端面側を平坦面化加工し、導電性バンプの先端部
を露出させる工程とを有することを特徴とする半導体装
置の製造方法。
A step of providing a conductive bump on an electrode surface of the semiconductor element; and immersing the surface provided with the conductive bump in a fluid resin.
A step of filling and adhering the resin to the conductive bump region, and after curing the filled and adhered resin, flattening the front end side of the conductive bump to expose the front end of the conductive bump And a method of manufacturing a semiconductor device.
【請求項4】 流動性樹脂中に半導体素子を浸漬すると
き、半導体素子の裏面側を吸着パッドで保持することを
特徴とする請求項2もしくは請求項3記載の半導体装置
の製造方法。
4. The method according to claim 2, wherein when the semiconductor element is immersed in the fluid resin, the back surface of the semiconductor element is held by a suction pad.
JP8303189A 1996-11-14 1996-11-14 Semiconductor device and manufacturing method thereof Withdrawn JPH10144825A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8303189A JPH10144825A (en) 1996-11-14 1996-11-14 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8303189A JPH10144825A (en) 1996-11-14 1996-11-14 Semiconductor device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
JPH10144825A true JPH10144825A (en) 1998-05-29

Family

ID=17917961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8303189A Withdrawn JPH10144825A (en) 1996-11-14 1996-11-14 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH10144825A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002041386A1 (en) * 2000-11-15 2002-05-23 Dow Corning Toray Silicone Co., Ltd. Method for coating electronic parts

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002041386A1 (en) * 2000-11-15 2002-05-23 Dow Corning Toray Silicone Co., Ltd. Method for coating electronic parts

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