JPH1013715A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent jitter included in a video signal from appearing as fluctuation in a digital output by detecting unsharpened waveform of an analog image signal. SOLUTION: A video signal fed to an input terminal 1 is fed to a delay circuit 12 and a subtractor circuit 14, and the video signal via the delay circuit 12 is fed to a delay circuit 13 and a synthesis circuit 16. The video signal via the delay circuit 13 is fed to a subtractor circuit 14, the subtractor circuit 14 detects a difference signal between the video signal fed to an input terminal and the video signal via the delay circuit 13 as an unsharpened signal and it is fed to a differentiation circuit 15. The unsharpened signal is differentiated by the differentiation circuit 15 and the resulting signal is synthesized with the video signal via the delay circuit 12 at a synthesis circuit 16 as a corrected unsharpening signal. Thus, the video signal waveform-shaped by a waveform shaping circuit 11 is fed to an A/D converter 2, in which the signal is converted into a digital signal based on a sampling clock fs fed to an input terminal 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter suitable for use in converting a display analog video signal of a computer into a digital video signal.

[0002]

2. Description of the Related Art At present, a raster scan type so-called CRT display device is widely used as a display device of a host computer such as a personal computer and a workstation. However, in recent years, flat panel display devices such as liquid crystal panels and plasma displays have attracted attention in terms of space saving, energy saving, ergonomics, and the like. These host computer device and the CR
In connection with the T display device, a so-called video signal,
That is, an analog image signal, a vertical and horizontal synchronizing signal, or a composite signal thereof (composite signal)
Are used, each of these signals has a very large number of specifications, and a personal computer may have a plurality of resolutions. For example, IBM P
For C compatible devices, the number of pixels in the horizontal and vertical directions is 320
* 200, 640 * 400, 720 * 400, 640 *
350, 640 * 480, 800 * 600, 1024 *
There are devices that can display at each resolution such as 768, 1280 * 1024.

For such a plurality of resolutions, there is a CRT display device called a so-called multi-sync CRT display device, which measures a synchronizing signal of an input video signal, and determines a driving cycle and a swing width of a scanning line. Is matched to the synchronization signal of the video signal. At that time, CRT
A video signal or a synchronization signal is measured in advance for each of several host computers in the display device, and the results are stored as display parameters in a memory in the CRT display device. If it can be specified, the display parameters in the memory are used to perform a more accurate display such as a display position.

On the other hand, current dot matrix displays such as liquid crystal panels and plasma displays are suitable for performing display control by digital signals.
A method is adopted in which an input video signal is A / D converted once and then displayed. At this time, the horizontal sampling is performed for one pixel of the video signal because the characteristic of the performance of the current dot matrix display is that "one pixel is larger than the shadow mask of the CRT and is difficult to control". Is generally sampled and displayed in correspondence with one pixel of the display panel.

[0005] The configuration and operation of a conventional AD converter will be described below. FIG. 6 is a configuration diagram showing a conventional AD converter, and FIG. 5A is a diagram showing a sampling operation.
6, reference numeral 1 denotes an input terminal of an analog image signal (video signal), 2 denotes an AD converter, 3 denotes an output terminal of a digital video signal, 4 denotes a synchronization signal input terminal, 5 denotes a phase comparison circuit, and 6 denotes an LPF (low-pass). 7) a VCO circuit (voltage controlled oscillator), 8 a frequency dividing circuit, 9 a PLL circuit,
Reference numeral 10 denotes a sampling pulse input terminal for AD conversion.

Next, the operation will be described. The analog video signal and the horizontal synchronizing signal output from the computer are supplied to input terminals 1 and 4 respectively. The PLL circuit 9 generates a sampling clock fs required for AD conversion from the horizontal synchronizing signal supplied to the input terminal 4, and displays a sampling clock fs having a frequency corresponding to a pixel of a video signal output from the computer on each display. Generated in accordance with the mode, and supplied to the AD converter 2 through the input terminal 10. The phase of the horizontal synchronizing signal supplied to the phase comparator 5 is compared with the output signal of the frequency divider 8, and the phase comparison error signal is supplied to the VCO circuit 7 via the LPF 6. The output signal of the VCO circuit 7 is supplied to an input terminal 10 as a sampling clock fs required for AD conversion and is also supplied to a frequency dividing circuit 8. The frequency dividing circuit 8 sets a frequency dividing ratio corresponding to each display mode so that a sampling clock fs corresponding to a pixel of a video signal output from the computer is obtained.

On the other hand, the video signal supplied to the input terminal 1 is supplied to the AD converter 2 and is converted into a digital signal by the sampling clock fs supplied to the input terminal 10. The output signal of the AD converter 2 is output from the output terminal 3 as a digital video signal corresponding to the pixel of the video signal.

FIG. 5A shows a sampling operation performed by a conventional AD converter, and is a waveform diagram showing a sampling operation for one pixel of an analog video signal input to the AD converter 2. As shown in the figure, the signal input from the computer to the AD converter 2 includes a time axis fluctuation (hereinafter, referred to as jitter), and the AD output can be obtained stably in the jitter-free portion of the AD input signal. ing.

[0009]

As shown in FIG. 5A, a video signal outputted from a computer contains jitter. For this reason, A can obtain a stable digital signal by sampling the input signal of the AD converter.
The D output stable range is a range excluding the influence of jitter, as shown in FIG. When the amount of fluctuation of the jitter is large, the amount of fluctuation of the jitter appears as a digital output of the AD converter. The fluctuation of the digital output due to the fluctuation of the jitter degrades the image quality of the dot matrix display such as liquid crystal and plasma.

[0010] In view of the above, the present invention provides a video signal output from a computer, even if the video signal contains jitter.
An object of the present invention is to provide an AD converter that does not appear as a change in digital output at the output of the AD converter.

[0011]

According to the present invention, there is provided a detecting means for detecting a dullness of a waveform of an input analog image signal and outputting a dulling signal; a differentiating means for differentiating the dulling signal; A synthesizing means for synthesizing an output and the analog image signal, and an AD converting means for converting an output of the synthesizing means into a digital signal are provided.

[0012]

According to the present invention, the detecting means detects the degree of dullness of the input analog image signal, and obtains a dulled signal as shown in FIG. The blunt signal is differentiated by differentiating means,
The differential waveform is superimposed on the analog image signal waveform to form the waveform shown in FIG. 2 (f), and this waveform is subjected to A / D conversion, so that the stable range of the AD output becomes as shown in FIG. 5 (a). ) Can be wider than before.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a display system to which the present invention is applied will be described with reference to FIG. In FIG.
1, 2, 4, 9, and 10 are substantially the same as the same reference numerals in FIG. 6, and duplicate description will be omitted. 21 is a computer for outputting an analog image signal (video signal), 11
Is a waveform shaping circuit provided according to the present invention.
From the video signal from A
Send to D converter 2.

Reference numeral 22 denotes a memory for storing the digital video signal from the AD converter 2, reference numeral 23 denotes a display device for displaying the video signal read from the memory 22, and reference numeral 24 denotes a plurality of synchronization signals (sync signals) included in the video signal. A synchronization separation circuit that extracts horizontal and vertical synchronization signals from on-green, composite, etc.) and supplies the extracted synchronization signals to the PLL circuit 9 via the input terminal 4. Reference numeral 25 denotes a memory control circuit for controlling writing and reading of the memory 22 based on the sampling clock fs output from the PLL circuit 9, and reference numeral 26 denotes a PLL circuit based on the synchronization signal extracted by the synchronization separation circuit 24 while controlling the whole. 9 is a microprocessor (MPU) for controlling the frequency divider circuit 9 and changing the frequency of the sampling clock fs.

Next, the operation of the above configuration will be described. The video signal input from the computer 21 is subjected to waveform shaping by the waveform shaping circuit 11 and then applied to the AD converter 2 and to the sync separation circuit 24 to extract horizontal and vertical sync signals. The MPU 26 sets a dividing ratio for the dividing circuit of the PLL circuit 9 based on the extracted synchronization signal. The AD converter 2 samples the waveform-shaped signal by the sampling clock fs obtained from the PLL circuit 9 and converts the sampled signal into, for example, an 8-bit digital video signal. Further, the memory control circuit 25 controls the writing of the memory 22 according to the sampling clock fs, and the digital video signal is written. Next, the MPU 26 sends a command for driving the display device 23 according to the resolution. After setting for driving, the display device 23 sends a ready signal indicating that data can be received to the MPU 26. Next, the memory control circuit 25 reads the memory 22 and sends it to the display device 23. As a result, display is performed at a resolution corresponding to the input video signal.

FIG. 1 is a block diagram showing a first embodiment of an AD converter according to the present invention, and FIG. 2 is a timing chart for explaining the operation of this embodiment.
Each signal of (a) to (f) corresponds to (a) to (f) of FIG. In FIG. 1, the AD converter includes an input terminal 1 for a video signal, an AD converter 2, an output terminal 3 for a digital video signal, an input terminal 10 for a sampling clock fs for AD conversion, and a waveform shaping circuit 11. In the waveform shaping circuit 11, reference numeral 12 denotes a first delay circuit;
Is a second delay circuit, 14 is a subtraction circuit, 15 is a differentiation circuit, and 16 is a synthesis circuit.

Next, the operation will be described. The analog video signal output from the computer 21 is supplied to the input terminal 1
Supplied to The sampling clock fs required for AD conversion is generated by the PLL circuit 9 as in the conventional example.
A sampling clock fs having a frequency corresponding to the pixel of the video signal output from the computer 21 is supplied to the input terminal 1.
0 is supplied.

The video signal supplied to the input terminal 1 is supplied to a first delay circuit 12 and a subtraction circuit 14.
The video signal passed through the first delay circuit 12 is supplied to a second delay circuit 13 and a synthesizing circuit 16. The video signal via the second delay circuit 13 is supplied to a subtraction circuit 14. The subtraction circuit 14 detects a difference signal from the video signal supplied to the input terminal 1 as a dull signal and supplies the signal to the differentiating circuit 15.

In FIG. 2, (a) is a video signal supplied to the input terminal 1, (b) is a video signal through the first delay circuit 12, and (c) is a video signal through the second delay circuit 13. The video signal, (d), shows the dull signal detected by the subtraction circuit 14. This dull signal indicates the degree of dullness of the video signal, and is differentiated by the differentiating circuit 15 and is used as a dulling correction signal by the first delay circuit 12 by the synthesizing circuit 16.
With the video signal passed through FIG. 2E shows a dullness correction signal, and FIG. 2F shows an output signal of the synthesizing circuit 16.

The video signal of FIG. 2 (f) whose waveform has been shaped by the waveform shaping circuit 11 by the above operation is supplied to the AD converter 2 and converted into a digital signal by the sampling clock fs supplied to the input terminal 10. . The output signal of the AD converter 2 is output from the output terminal 3 to the memory 22 as a digital video signal corresponding to the pixel of the video signal.

FIG. 5B shows a sampling operation by the AD converter according to the present invention, and is a waveform diagram showing a sampling operation for one pixel of an analog video signal input to the AD converter 2. As shown in the figure,
By correcting the rising / falling bluntness included in the waveform of the video signal input to the AD converter 2,
The AD output stable range of the AD converter 2 can be expanded as compared with the conventional example of FIG.

Next, a second embodiment of the AD converter according to the present invention will be described with reference to FIG. FIG. 3 differs from FIG. 1 in the configuration of the waveform shaping circuit 11. In the waveform shaping circuit 11, reference numeral 18 denotes a first variable delay circuit, and reference numeral 19 denotes a second variable delay circuit. Reference numeral 17 denotes a delay amount control circuit. Other parts are configured similarly to FIG.

As described above, this embodiment is the first embodiment of FIG.
Is replaced by a first variable delay circuit 18 and a second variable delay circuit 19 capable of adjusting a delay amount, and the delay amount is controlled by a delay amount control circuit 17 to analog video. The control can be performed according to the dullness of the signal waveform.

[0024]

As described above, according to the present invention,
The dullness of the analog image signal waveform is detected, the dulled signal is differentiated and synthesized with the analog image signal, and the synthesized output is A
By performing the D conversion, the A / D converter A
The D output stable range can be expanded, and the fluctuation of digital output due to jitter can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an AD converter according to the present invention.

FIG. 2 is a timing chart for explaining an operation.

FIG. 3 is a block diagram showing a second embodiment of the AD converter according to the present invention.

FIG. 4 is a block diagram showing a display system to which the present invention is applied.

FIG. 5 is a waveform chart for comparing the effects of the present invention and the related art.

FIG. 6 is a block diagram showing a conventional AD converter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Analog video signal input terminal 2 A / D converter 3 Digital video signal output terminal 9 PLL circuit 10 Sampling clock input terminal 11 Waveform shaping circuit 12 First delay circuit 13 Second delay circuit 14 Subtraction circuit 15 Differentiation circuit 16 Synthesis Circuit 17 Delay amount control circuit 18 First variable delay circuit 19 Second variable delay circuit

Claims (4)

[Claims] 1. A detecting means for detecting dullness of an input analog image signal waveform and outputting a dulling signal, a differentiating means for differentiating the dulling signal, and synthesizing an output of the differentiating means and the analog image signal. An A / D converter comprising: a synthesizing unit for converting the output of the synthesizing unit into a digital signal. 2. The apparatus according to claim 1, wherein said detecting means includes: first delay means for delaying said analog image signal; second delay means for delaying an output of said first delay means; And subtracting means for detecting a difference between the output of the delay means and the differential means and providing the difference to the differentiating means. The combining means combines the output of the differentiating means and the output of the first delay means. The AD converter according to claim 1, wherein: 3. The AD converter according to claim 2, further comprising control means for controlling a delay amount of said first and second delay means. 4. The AD converter according to claim 1, further comprising clock generating means for generating a sampling clock having a frequency corresponding to the synchronizing signal of the analog image signal and supplying the sampling clock to the AD converting means.