JP2002320170A - Image output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image display device which is capable of displaying images of high fidelity, even for video signals having various kinds of parameters. SOLUTION: An image display device is equipped with an A/D conversion circuit, which obtains the frequency of the reference clock signals included in the video signals composed of horizontal synchronization signals, vertical synchronization signals, and image signals and quantizes the image signals through the frequency and a sampling clock of nearly the same frequency as with the reference clock signals; an image memory circuit which retains a part out of the image data outputted from the conversion circuit, corresponding to the image period of the image signals; a display means which displays images by the use of the output of the memory circuit. The image display device displays images of high fidelity with to respect original image signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of inputting a video signal and obtaining its signal parameters, and automatically converting the video signal into digital image data and coordinate information using the signal parameters. And an image display device that outputs the image data to a display device.

[0002]

2. Description of the Related Art In recent years, a video printer device which receives image information (video signal) output from a video device such as a computer, a communication device, or a television for a display device and prints and records an image or a figure. Is being developed.

[0003] These video signals are becoming finer and have more gradations, and video printers are also being required to cope with higher definition and more gradations.

Conventionally, a video printer for printing and recording this kind of video signal is disclosed in, for example, JP-A-60-46.
As disclosed in Japanese Unexamined Patent Publication No. 733 as a still image recording device, there is known a device which once converts a video signal of a general television broadcast or the like into digital data and prints and records an image using the image data. ing.

When a video signal is converted into digital data, a video signal constituting the video signal is sampled at a timing based on a synchronization signal accompanying the video signal. Each digitized image data is managed together with coordinate position information in the entire image, and is reproduced based on the coordinate position information at the time of printing and recording.

The management of the actual image period in the video signal (the period during which the image signal constituting the actual screen of the video signal is output) in the horizontal and vertical directions is performed as follows.

FIG. 18 is a timing chart showing the structure of the video signal, showing the relationship between a vertical synchronizing signal (V synchronizing signal), a horizontal synchronizing signal (H synchronizing signal) and a video signal, and an enlarged H synchronizing signal. And the relationship between the image signal and the video signal.

In FIG. 1, an image signal 4 is displayed in the horizontal direction.
An image period 450, which is an output period of 53, and a blanking period 451 from the fall of the H synchronization signal to the start of the image period 450 are set in advance, and after the H synchronization signal falls, only the blanking period 451 is set. By sampling the video signal only for the image period 450 from the point in time after the delay, of the video signal for one line in the horizontal direction,
Only the image signal is selectively sampled.

As a result, only the image signal 453 indicating the image period 450 is digitized and output as image data.

In the vertical direction, a predetermined time (back porch period) 454 from the fall of the V synchronization signal to the input of a video signal including an image signal is set in advance, and the V synchronization signal rises. After lowering, the vertical image period is managed by sampling the video signal corresponding to the H synchronization signal starting from the time delayed by the back porch period 451.

The above-mentioned prior art example relates to a video printer device, but there is a liquid crystal display device disclosed in Japanese Patent Application Laid-Open No. 55-650 as a display device. In such a conventional example, a video signal (television signal) is input, and a video signal portion of the video signal is digitized and stored in an image memory capable of holding one screen of image data. Are read out in a predetermined order, and an image is displayed on the liquid crystal display unit.

[0012]

The video printer and the liquid crystal display device having the above-mentioned structure operate correctly for a certain kind of video signal, but can handle a predetermined kind of video signal such as a television signal. And there is a problem that it is not possible to cope with a video signal in which the values of signal parameters such as the blanking period and the back porch period are slightly different.

An apparatus capable of handling video signals having different signal parameter values is disclosed in JP-A-59-226.
581.

In this conventional apparatus, the time setting from the output of the synchronization signal to the start of the sampling process for the video signal is performed using a rewritable storage element (shift register). Can be adapted to video signals having different signal parameter values.

However, in this prior art, since the frequency of the timing signal (sampling clock) for performing the sampling process is fixed, when the type of the synchronization signal is different, that is, when the time per horizontal line is different. However, since the aspect ratio of the sampled image data changes, and the aspect ratio between the original image and the print image changes, faithful printing cannot be performed.

In addition, since the standard of an existing NTSC or PAL video signal is known, various parameter values can be prepared in advance according to each system. Is, for example, a separate transistor technology SPECIAL, No. 5 (198
7) On pages 106 to 136, techniques widely discussed under the titles of "image processing technology by personal computer" and "design and manufacture of image input board for personal computer" are widely known.

However, in recent computers and information terminal devices that handle video signals, the resolution of the display has been increased, and for example, 1280 pixels in the horizontal direction and 1 pixel in the vertical direction.
A device that displays about four times as much information as a signal format used for conventional television broadcasting, such as 024 pixels, is being developed.

However, there is no generalized standard for this kind of high-definition high-resolution video signal, and at present, different signal formats are used for different manufacturers of electronic computers as signal sources.

Therefore, in a video printer device for performing printing and recording based on these high-definition and high-resolution video signals and a liquid crystal display device for displaying images, the specifications have to correspond to the video signal standards. The conventional technology using a shift register cannot cope with a newly developed video signal in a signal format.

Further, in the prior art, if the frequency of the sampling signal on the video printer side is made sufficiently higher than the quantization frequency on the signal source side, the video signal can be obtained without considering the quantization frequency on the signal source side. However, since the frequency band of a high-definition high-definition video signal is very high, the sampling frequency cannot be made sufficiently faster than the quantization frequency at the signal source, and the sampling frequency cannot be increased. Must match the quantization frequency at the signal source.

Further, dullness of a video signal due to connection conditions such as a cable connecting a signal source and a video printer or a display cannot be ignored. That is,
If the peak value of the signal does not match the sampling position, for example, when the image signal is a line image, a problem occurs that the line image is not accurately represented in the print image or the display image is not accurately displayed. .

Therefore, in order to solve such a problem, it is necessary to match the timing at the time of quantization in the signal source with the sampling timing at the video printer or the display device side according to the situation. Such a thing cannot be performed using data set in advance.

Thus, the prior art video printer,
Alternatively, the display device can cope with a case where the format of the input video signal is known, but has a problem that it cannot handle a video signal of an unknown format.

An object of the present invention is to solve the above-mentioned problems, obtain a signal format of an input video signal, and set various parameters according to the result.
Regardless of the video signal of any signal format, the video signal is automatically and faithfully converted into digital image data and coordinate information, which is then output to a terminal device such as a general-purpose video printer. A display device is provided.

[0025]

In order to solve the above problems, the present invention takes the following measures.

(1) Corresponding to a video signal composed of a horizontal synchronization signal, a vertical synchronization signal, and a video signal having various signal parameter specifications, when the video signal is input, an image display faithful to the video signal is displayed. In a possible image display device, A / D conversion means for quantizing the video signal with a sampling clock having substantially the same frequency as a reference clock constituting the video signal, and of the outputs of the conversion means, It is characterized in that it comprises image memory means for holding image data corresponding to a video period, and a display unit for displaying an image of the output of the memory means.

(2) Further, the present invention is characterized in that a phase adjusting means for adjusting the phase of the sampling clock when a video signal having a predetermined image pattern is input is provided.

[0028]

Since the number of pixels in the horizontal and vertical directions substantially uniquely corresponds to the frequency of the horizontal synchronization signal, the number of pixels in the horizontal and vertical directions is determined if the frequency of the horizontal synchronization signal is detected. .

If the number of pixels in the horizontal direction and the frequency of the horizontal synchronizing signal are known, the approximate frequency at the time of quantization of the video signal can be obtained by multiplying the frequency by the number of pixels.

The video signal is sampled at the above-mentioned approximate frequency, and by referring to the image data, one of the horizontal synchronizing signals can be obtained.
The image period in the cycle, and one of the vertical synchronization signals
The image period within the cycle can be determined.

Then, the video signal is converted into digital image data and coordinate information according to the number of pixels, the image period, and the approximate frequency determined as described above, and this is converted into a terminal such as a video printer or a liquid crystal display device. If you output to the device,
Image output and display faithful to the original video signal can be performed.

Further, the apparatus further comprises means for correcting the image period and the approximate frequency with reference to the image data and the coordinate information, so that the reference to the image data and the like and the correction according to the reference result are repeated. By doing so, more faithful image printing and display becomes possible.

Further, by correcting the difference between the phase of the video signal and the phase of the sampling signal with reference to image data and the like, more accurate image printing and display can be performed.

[0034]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an image signal input device 1 according to an embodiment of the present invention.
FIG. 2 is a block diagram showing the entire configuration of the embodiment.

In the figure, a video signal 302, a video signal output from a video signal output device 2 such as an electronic computer connected to the outside.
A video signal 806 including a horizontal (H) synchronization signal 303 and a vertical (V) synchronization signal 304 is input to the monitor 202 and the image signal input device 1.

FIG. 3 is a timing chart showing the structure of the video signal 806. FIG. 3A shows the relationship among the V synchronization signal 304, the H synchronization signal 303, and the video signal 302. FIG. 3B shows the H synchronization signal 30.
3, the H synchronization signal 303, the video signal 302, and the video signal 302 from the video signal output device 2 per one cycle Th.
FIG. 4 is a diagram showing a relationship between a reference clock used when sending out a signal and a sampling signal having the same frequency.

If the image is color, the video signal 30
2 is red (R), green (G), and blue (B) which are three primary colors of light.
In the present embodiment, the same processing is performed for all three colors. Therefore, for simplicity, only one color will be described. The description of the colors is omitted.

The V-sync signal 304 sets the time for displaying one image, and its frequency is generally set to a period during which the after-image phenomenon of the human eye can be used, for example, 16 m.
A frequency having a period around s (60 Hz) is often used.

In FIG. 3A, a period (video period) 705 during which an H synchronization signal having an image signal constituting an actual image is output starts from one cycle of the V synchronization signal 304 and ends with a blanking period before and after that. This is only the period obtained by subtracting 704 and 706, and the blanking period 704, 706
Outputs a video signal for displaying black.

On the other hand, in FIG.
2, each image signal 4 for one row that actually forms an image
53 is output at a timing such that it falls within the period of one cycle of the H synchronization signal 303.
The image signal 453 is output only during the image period 711 obtained by subtracting the back porch period 710 and the front porch period 712 before and after the one period Th of the H synchronization signal 303 within the period. In the porch periods 710 and 712, a video signal for displaying black is output.

Returning to FIG. 1, the video signal 302 is converted into digital image data 305 by the A / D converter 301 and then output to the common bus 4, where the digital image data 305 is output.
Are temporarily stored in the image memory 5 as described later in detail.

The H synchronizing signal 303 is supplied to the reset terminal of the first frequency divider 360 in the phase comparator 351 and the horizontal synchronizing address generating means 27 of the PLL circuit 350 and in the horizontal input head position setting means 26. Generating means 28
, The clock terminal of the second frequency divider 371 in the horizontal input head position setting means 29, the clock terminal of the third frequency divider 380, and one input terminal of the interlace detecting means 30 And the output signal of the third frequency divider 380 is input to the controller 381.

The V synchronization signal 304 is supplied to the other input terminal of the interlace detecting means 30 and the second frequency divider 371.
Is input to the reset terminal. Interlace detecting means 3
0 inputs the H synchronizing signal 303 and the V synchronizing signal 304, determines whether or not interlaced scanning is performed by comparing the phases of both, and outputs the determination result to the controller 381.

The H address counter 361 in the horizontal synchronizing address generating means 27 stores the digital image data 305
Is output to the image memory 5 via the common bus 4 for setting an address in the horizontal direction when the image data is stored in the image memory 5.

Similarly, the V address counter 370 in the vertical synchronizing address generating means 28 shares a V address signal 374 for setting an address in the vertical direction when the digital image data 305 is stored in the image memory 5. Output to the image memory 5 via the bus 4.

The output signal of the freeze switch 385, the output signal of the preset switch 386, and the output signal of the automatic adjustment switch 387 are input to the controller 381. The controller 381 includes a RAM 392, a ROM
393 and a backup power supply 394 are connected.

The PLL circuit 350 includes a phase comparator 3
51, a filter 352, an amplifier 353, a VCO (voltage controlled oscillator) 354, and a fourth frequency divider 355. The frequency division ratio of the fourth frequency divider 355 is set in a frequency division ratio shift register 356. The parameters are determined by the controller 381.

The H synchronization signal 303 input to the phase comparison circuit 351 is compared with the signal output from the VCO 354 and frequency-divided by the fourth frequency divider 355, and the error signal after the comparison is passed through the filter 352. Input to the amplifier 353. The amplifier 353 converts the amplified error signal into VCO3
54, and the VCO 354 outputs a clock signal 802 in which the phase error is corrected and synchronized with the H synchronization signal 303.

That is, the clock signal 802 output from the PLL circuit 350 is synchronized with the H synchronization signal 303,
Further, the clock signal becomes a frequency division ratio multiplied by the frequency division ratio stored in the frequency division ratio shift register 356 with respect to the original H synchronization signal 303.

The clock signal 802 is supplied to the phase delay unit 2
5, the clock terminal of the H address counter 361, the delay unit 390, and the first frequency divider 360
Clock terminal.

The phase delay unit 382 delays the clock signal 802 by a time determined by a parameter set in the delay shift register 383, and outputs the delayed clock signal to the A / D converter 301 as a sampling signal 803. The delay unit 390 converts the clock signal 802 into
The output timing of the H address signal 364 output from the H address counter 361 to the common bus 4 is delayed by a time corresponding to the processing in the H address counter 361, and the sampling output to the common bus 4 via the delay unit 390. The output timing of the signal 803 is matched.

As a result, if the frequency division ratio set in the frequency division ratio shift register 356 is 1700, for example, H
The video signal per one cycle Th of the synchronization signal 303 is 170
The image data 305 is divided into 0 and 1700 pieces of image data 305 are output to the image memory 5 via the common bus 4 per one cycle Th.

As will be described later with reference to FIG. 6, the phase delay unit 25 converts the quantization frequency when the digital signal data is converted (quantized) into a video signal which is an analog signal on the video signal output device 2 side. Are used to match the phase with the sampling frequency on the image signal input device 1 side. The parameters set in the delay shift register 383 are
Is set by

The horizontal synchronizing address generating means 27 includes a horizontal input head position setting means 26, an H address counter 36
The horizontal input head position setting means 26 is constituted by a first frequency divider 360 and an H start shift register 362. The parameters of the H start shift register 362 and the H input number shift register 363 are determined by the controller 381.

In the horizontal synchronizing address generating means 27, the first frequency divider 360 is reset by the H synchronizing signal 303, and divides the clock signal 802 by the frequency dividing ratio (parameter) set in the H start shift register 362. Then, the divided output is output to the H address counter 361.

When the frequency division output is input, the H address counter 361 inputs the number of H inputs to the parameter set in the shift register 363.

On the other hand, the vertical synchronization address generating means 28
Vertical input head position setting means 29, V address counter 3
70 and a V input number shift register 373, and the vertical input head position setting means 29 further includes a second
It comprises a frequency divider 371 and a V start shift register 372. V start shift register 372
And the parameters of the V input number shift register 373 are determined by the controller 381.

In the vertical synchronizing address generating means 28, the second frequency divider 371 is reset by the V synchronizing signal 304, and divides the H synchronizing signal 303 by the dividing ratio (parameter) set in the V start shift register 372. Then, the divided output is output to the V address counter 370.

The common bus 4 is connected to an external device, for example, the image printing means 2 via an interface 22.
0, connected to the image storage means 21.

The image data 305 held in the image memory 5 is also output to the monitor 203 to display an image.

Next, the horizontal synchronization address generating means 2
7 and the operation of the vertical synchronization address generator 28 will be described in detail.

Here, the frequency division ratio parameter of the H start shift register 362 of the horizontal synchronization address generation means 27 is set to X1, and the parameter of the H input number shift register 363 is set to X2. 28 V start shift register 372 becomes Y1,
The following description is based on the assumption that the V input number shift register 373 is set to Y2 and the frequency division ratio shift register 356 is set to Z1.

In the horizontal synchronization address generating means 27,
When the H synchronization signal 303 falls, the first frequency divider 360 is reset. After that, when the clock signal 802 output from the PLL circuit 350 is frequency-divided by X1 by the first frequency divider 360, the preset signal 804 becomes It is output to the H address counter 361.

When the preset signal 804 is input, the H address counter 361 sets the H input number shift register 36
Then, every time the clock signal 802 is input, an H address signal is generated, and X2 address signals are output to the image memory 5.

As a result, in the image memory 5, of the video signals obtained by dividing one cycle of the H synchronizing signal 303 into Z1, the (X1 + 1) th from the beginning is used as the start address, that is, the (X1 + 1) th X2 to (X1 + X2) th image data are input to the image memory 5.

Therefore, the period corresponding to the back porch period 710 described with reference to FIG. 3B is set in the H start shift register 362, and the period corresponding to the image period 711 is set in the H input number shift register 363. Only the image data corresponding to the image period is output to the image memory.

On the other hand, in the vertical synchronizing address generating means 28, when the V synchronizing signal 304 falls, the second frequency divider 371
Is reset, and thereafter, when the H synchronization signal 303 is frequency-divided by Y1 by the second frequency divider 371, the preset signal 805 is output to the V address counter 370.

When the preset signal 805 is input, the V address counter 370 sets the V input number shift register 37.
3 is read, and thereafter, every time the H synchronization signal 303 is input, a V address signal is generated, and Y2 address signals are output to the image memory 5.

As a result, in the image memory 5, among the H synchronization signals after the V synchronization signal 304 is output, Y2 video signals corresponding to the (Y1 + 1) th H synchronization signal from the beginning are set as the top addresses, In other words, the (Y1 + 1) th to (Y1 + Y2) th image data Y2 are input to the image memory 5.

Therefore, a period corresponding to the blanking period 704 described with reference to FIG. 3A is set in the V start shift register 372, and an image period 705 corresponding to one screen is set in the V input number shift register 373. For example, in the vertical direction, an image period 705 for one screen
Is output to the image memory 5.

As a result, the image memory 5 stores X2 pixels in the horizontal direction and Y2 pixels in the vertical direction, for a total of X2 × Y2.
Pieces of image data are stored.

FIG. 2 is a perspective view of the image signal input device 1. The freeze switch 385, the preset switch 386, and the automatic adjustment switch 38 are provided on the front surface thereof.
7 is attached. The purpose of each switch is
This will be described in the following examples as appropriate.

FIG. 4 is a diagram showing an example of the configuration of the number of pixels of an image generally used in a display method without interlace (sequential scanning method).

The example of the image shown in FIG.
This is an image composed of four pixels. The image example of FIG. 2 (II) is an image composed of 768 pixels in the vertical direction, and the image example of FIG. 3 (III) is composed of 400 pixels in the vertical direction. It is an image.

The frequency of the H synchronizing signal in each image example is generally set generally in correspondence with the number of pixels in the vertical direction. That is, as described above, since the frequency of the V synchronization signal is set to about 60 Hz from the viewpoint of the afterimage phenomenon, if the frequency of the H synchronization signal is 64 kHz, the number of H synchronization signals in one cycle of the V synchronization signal becomes It is calculated as follows.

(64 kHz / 60 Hz) = 1067 Then, when the number of H synchronization signals in the vertical direction is obtained, it is determined that the number of pixels in the vertical direction according to the number of H synchronization signals is 1024 pixels.

Similarly, the frequency of the H synchronization signal is 49 kHz.
If it is near, the number of pixels in the vertical direction is determined to be 768 pixels. If the frequency of the H synchronization signal is near 24 kHz, the number of pixels in the vertical direction is determined to be 400 pixels.

Similarly, in general, the vertical direction is 1024
In the case of pixels, the horizontal direction is often 1280 pixels, when the vertical direction is 768 pixels, the horizontal direction is often composed of 1024 pixels, and when the vertical direction is 400 pixels, the horizontal direction is 640 pixels It is known that there are many.

The operation of each embodiment of the present invention, which will be described in detail below, determines the parameters of a video signal in an unknown signal format by partially utilizing the above estimation results, and reproduces a faithful image. I have to.

Hereinafter, the operation principle of the first embodiment shown in FIG. 1 will be described with reference to the flowchart of FIG.

In this embodiment, each parameter of the input video signal of unknown signal format is obtained by the following three-stage automatic adjustment.

First stage: determination of the number of pixels (horizontal direction and vertical direction) in an image period in a video signal.

Second stage: Judgment of image period (blanking period and video period in horizontal and vertical directions) and sampling frequency.

Third stage: phase adjustment of sampling signal.

When a video signal of an unknown signal format output from the video signal output device 2 is input to the image signal input device 1 and the automatic adjustment switch 387 is operated, the first stage of the determination operation starts.

In step S1, the H synchronization signal divided by the third divider 380 is input to the controller 381.
The controller 381 determines the approximate frequency of the H synchronization signal based on the input signal as follows.

That is, assuming that the frequency division ratio of the third frequency divider 380 that divides the H synchronization signal is 100, and the period of the H synchronization signal after frequency division is 1.5 ms, 100 / (1. 5
× 10-3) = 66.67 kHz, the controller 381 determines the RO based on the above estimation.
With reference to data registered in advance in M393, it is determined that the approximate frequency of the H synchronization signal is around 64 kHz.

When the approximate frequency of the H synchronizing signal is determined, the controller 381 refers to the data table registered in the ROM 393 based on the determination result that the approximate frequency of the H synchronizing signal is 64 kHz in step S2. Is determined to be, for example, 1280 and the number of pixels in the V direction is, for example, 1024.
The 3 and V input number shift register 373 is set.

In step S4, 1 of H synchronization signal 303
The controller 381 obtains the number of sampling clocks SC per cycle with reference to the data table registered in the ROM 393, and sets this in the frequency division ratio shift register 356.

Note that, as shown in FIG. 7, when the video signal for one cycle of the H synchronization signal 303 is divided into SC digital image data as shown in FIG. At least the periphery A of the boundary between the blanking period 710 and the image period 711 and the image period 711 and the blanking period 7 within the number of pixels (1280) in the H direction from the top of the divided digital image data.
This is a number that can include the digital image data of the periphery B around the boundary portion with 12.

In the following description, it is assumed that the sampling clock number SC is determined to be 1800. At this time, the H start register 362 and the V start register 372 store, for example, 0
Is set.

When the provisional setting of each parameter is completed, the controller 381 outputs a write enable signal to the image memory 5 via the common bus in step S5a. From the PLL circuit 350, a clock signal having a frequency of 115 MHz obtained by multiplying the value (1800) set in the frequency division ratio shift register 356 by the frequency (64 kHz) of the H synchronization signal 303 is output as a sampling clock 802. Is A / D via the phase delay unit 382 of the phase delay unit 25
Input to the converter 301. The function of the delay unit 382 will be described later in detail with reference to FIG.

The A / D converter 301 A / D converts the video signal 302 with the sampling signal 803, divides the video signal for one cycle of the H synchronization signal 303 into 1800, and converts this into digital image data 305. Output to the memory 5.

At this time, the horizontal synchronization address generation means 27
The H address counter 361 starts an operation of generating an H (horizontal) direction address signal based on the sampling clock signal 802 as follows.

That is, after the first frequency divider 360 is reset by the H synchronization signal 303, the frequency division ratio (currently 0) set in the H start shift register 362
The clock signal 802 is frequency-divided, the frequency-divided output is sent to the H address counter 361 as a preset signal 804, and the preset value (1280) set in the H input number shift register 363 is converted to the H address counter 36.
Set to 1.

The H address counter 361 counts 1280 sampling clocks from the H synchronizing signal 303 and sets 128 as an address for one line in the H direction of the image.
An H-direction address of 0 is generated and the address is output to the image memory 5.

As a result, in the image memory 5, digital image data 305 obtained by sampling the video signal at a frequency of 115 MHz by the A / D converter 301 is stored in an area specified by the address.

As described with reference to FIG. 7, the image data input to the image memory 5 at this time starts from the head of the digital image data obtained by dividing the video signal for one cycle of the H synchronization signal by 1800. Up to the 1280th digital image data, digital image data around the boundary portion A between the blanking 710 and the video period 711 and digital image data around the boundary portion B between the video period 711 and the blanking 712 are included in the 1280 digital image data. Will be included.

On the other hand, the second divider 371 also divides the H synchronization signal 303 by the division ratio (currently 0) set in the V start shift register 372, and uses the divided output as a preset signal 805. V address counter 370
The preset value (1024) set in the V input number shift register is sent to the V address counter 37.
Set to 0.

Therefore, V address counter 370
Starts counting the H synchronization signal after the V synchronization signal 304 is output, generates a V-direction address for 1024 pixels in the vertical direction of the image, and outputs this to the image memory 5.

As a result, 1280 pieces of image data corresponding to each H synchronization signal are stored in the image memory 5 in an area specified by the V address in the vertical direction.

As described above, the first step of the automatic adjustment operation is the determination of the number of pixels in the image period in the video signal, and the registration of the image data obtained by using the parameters in the image memory 5. Upon completion, the second stage of the determination operation starts.

It is desirable that the image data to be registered in the image memory 5 in the first stage be selected so that the image becomes white in consideration of each operation in the second stage described later.

In step S6a, the controller 381
Reads out the contents of the image data stored in the image memory 5 via the common bus 4.

In step S7a, first, a blanking period from the fall of the V synchronization signal to the start of the video period is obtained as an address value by referring to image data corresponding to the V address as follows.

That is, in the first stage, when the video signal for turning the image white is stored in the image memory 5,
In the back porch portion other than the image area, the video signal 3
02 indicates black (luminance 0). Therefore, it can be determined that the period in which the image data is black is the back porch and the period in which the image data is white is the video period until the start of the video period.

In this embodiment, the period of the back porch is 10
It is assumed that the address is determined.

When the entire image is black, it is difficult to distinguish between the blanking period (back porch) and the video period. Therefore, when such automatic adjustment is performed, the image data must be registered in the image memory 5 in advance. The image data to be stored must be data corresponding to a video signal other than black at least at the beginning and end of the video period.

When the determination of the video period in the vertical direction is completed in this way, the determination of the video period in the horizontal direction is started.

Incidentally, the determination of the video period in the horizontal direction is not limited to simply finding the image period and the blanking period according to the H synchronization signal 303. Need to ask at the same time.

That is, most of the video signal output device 2 generates a video signal by converting digital information from an electronic computer or the like into an analog signal. If the sampling frequency does not match the sampling frequency of the A / D conversion on the video signal input device 1 side, moire fringes may occur in the image due to quantization errors.

In determining the video period in the horizontal direction, the blanking period, the video period, and the sampling frequency are obtained as follows.

The controller 381 reads out the image data obtained in the horizontal direction from the image memory 5,
The blanking period from the fall of the synchronization signal to the start of the video period and the subsequent video period are obtained as address values in the same manner as in the vertical direction.

In this embodiment, it is determined that the blanking period is 50 addresses and the video period is 1220 addresses.

When the blanking period in the V direction, the blanking period in the H direction, and the video period are obtained in this manner, the sampling frequency at the time of D / A conversion in the video signal output device 2 is obtained as follows. .

That is, since the number of pixels in the horizontal image period is 1280 and the obtained video period is 1220 addresses, the sampling frequency is made equal, that is, the image period is divided by 1280. For this purpose, the sampling frequency is set to 1280/122.
It can be seen that it is sufficient to multiply 0 by 1.05. If the sampling frequency becomes 1.05 times, the blanking period (back porch) in the H direction is also 50 addresses × 1.05.
= 53.

Similarly, in order to increase the sampling frequency by 1.05, it is understood that the division ratio of the PLL circuit 350, that is, the set value of the division ratio shift register 356 needs to be 1890.

When each parameter is obtained in this way, in step S8, it is determined whether or not the value of each parameter is within a predetermined range.

That is, in order to effectively utilize the function of the present embodiment, it is desirable to output a video signal for displaying a white screen in the first stage, but when such a video signal is not input, In this case, the value of each parameter is out of a predetermined range. Then, when the subsequent processing is executed in this state, accurate parameters are not set.

In step S8, it is determined whether the value of each parameter is within a predetermined range. If the value is outside the predetermined range, the process proceeds to step S9.
The general setting parameters set in 393 are read out,
In step S10, the parameter is set to each parameter of interest, and in step S11, each parameter is stored in the RAM 392, and the process ends.

On the other hand, if it is determined in step S8 that the value of each parameter is within a predetermined range, each parameter is set or reset in a predetermined register in step S12.

However, if such operation is performed only once, for example, when the blanking period or the video period is determined, if the boundary portion is not clear (the image data of the boundary portion indicates an intermediate value). , The parameters include errors.

Therefore, in the present embodiment, when the rough determination of the video period is completed as described above, it is determined in step S13 whether or not the determination result, that is, the parameter is correct. This determination is made by determining whether the image data at the address corresponding to the blanking period is substantially all 0 (black) and the image data at the address corresponding to the video period is substantially all 255 (white). Done. If not accurate, the process returns to step S5 to further improve the accuracy, and stores the video signal in the image memory 5 again using the parameter.

Hereinafter, reprocessing after returning to step S5 will be briefly described.

As is clear from the above description, at this point, the frequency division ratio shift register 356 has 1890
However, 53 is set in the H start shift register 362, 10 is set in the V start shift register 372, 1280 is set in the H input number shift register 363, and 1024 is set in the V input number shift register 373. And

In step S5, the controller 381 outputs a write enable signal to the image memory 5 via the common bus with the parameters set as described above.
From the PLL circuit 350, the frequency division ratio shift register 356
Is multiplied by the frequency (64 kHz) of the H synchronizing signal 303 with the value (1890) set as the clock signal 802 having a frequency of 121 MHz is output as a sampling clock. This sampling clock passes through the phase delay unit 382 of the phase delay unit 25 Input to the A / D converter 301.

The A / D converter 301 A / D converts the video signal with the sampling clock 803,
The video signal for one cycle of 03 is divided into 1890, and this is output to the image memory 5 as digital image data.

Further, the first frequency divider 360 resets the H start shift register 36 after being reset by the H synchronizing signal.
The clock signal 802 is frequency-divided at the frequency division ratio set to 2 (53 in this case), the frequency-divided output is sent to the H address counter 361 as a set signal 804, and the preset value set in the H input number shift register is set. Value (1
280) is set in the H address counter 361.

Therefore, H address counter 361
Is the start timing of the 54th clock signal 802 after the H synchronization signal 303 is output,
It outputs zero address signals to the image memory 5.

As a result, the 54th image data of the digital image data obtained by sampling the video signal at the frequency of 121 MHz in the A / D converter 301 is used as the start address in the image memory 5, and the 1280 image data is thereafter stored. Will be stored.

On the other hand, the second frequency divider 371 also outputs the V synchronization signal 3
After resetting at 04, H at the division ratio (10 in this case) set in the V start shift register 372
The synchronization signal 303 is frequency-divided, and the frequency-divided output is sent to the V address counter 370 as a set signal 805, and the preset value (1024) set in the V input number shift register is set in the V address counter 370.

Therefore, V address counter 370
Starts address generation 10 cycles after the H synchronization signal after the V synchronization signal 304 is output, generates a V address signal for 1024 pixels in the vertical direction of the image, and outputs this to the image memory 5. .

As a result, the eleventh H synchronizing signal after the V synchronizing signal is output to the image memory 5,
Thereafter, 1024 address signals are set.

In step S6, the controller 381 reads out the contents of the image data stored in the image memory 5 via the common bus 4, and further in step S7,
Referring to the image data corresponding to the V address, a blanking period from the fall of the V synchronization signal to the start of the video period is obtained as an address value in the same manner as described above.

In this embodiment, it is assumed that the back porch period has been modified from 10 addresses to 11 addresses.

When the determination of the video period in the vertical direction is completed as described above, the determination of the video period in the horizontal direction is started.

The controller 381 refers to the image data obtained in the horizontal direction and sets the blanking period from the fall of the H synchronization signal to the start of the video period and the subsequent video period in the same manner as described above. Obtain as a value.

Here, it is assumed that the blanking period has been corrected to 56 addresses and the video period has been corrected to 1260 addresses.

When the blanking period and the video period are obtained in this way, the sampling frequency is also obtained in the same manner as described above.

Sampling frequency = 1280/1260
× 121 = 123 Blanking period = 1280/1260 × 56 = 57 Similarly, the sampling frequency is set to 1280/1260 = 57.
In order to increase the frequency by 1.02, the frequency division ratio of the PLL circuit 350 is set to 1
It can be seen that 890 × 1.02 = 1927 is sufficient.

When the rough determination of the video period is completed in this way, in this embodiment, the same processing as described above is performed in steps S8 and S12, and the value of the parameter obtained in step S13 is accurate. Is determined, the second-stage adjustment ends.

When the determination of the video period is completed as described above, the phase of the sampling clock is adjusted next.

In this phase adjustment, as described later, the video signal 302 input to the video signal input device 1 is dull due to the influence of a cable capacity or the like on the way, and as a result, the video signal 302 and the sampling signal are generated. This is performed to compensate for a phase shift with respect to phase 803.

In performing the phase matching, after setting the parameters relating to the video period obtained up to that point in each register, as shown in FIG. 8A, the video signal in which a stripe pattern is repeated in the horizontal direction is repeated. Enter

It is determined in step S14 whether or not a video signal in which a striped pattern is repeated is input. If the video signal is not such a pattern, the parameters are stored in the RAM 392 in step S11 to execute the processing. finish.

In step S15, it is determined whether or not the phase of the video signal 302 matches the phase of the sampling signal 803. If the phases match, the process proceeds to step S1.
In step 1, each parameter is stored in the RAM 392, and the process ends.

Note that the parameters stored in the RAM 392 in this manner can be appropriately read by operating the preset SW 386, and the read parameters are set in a predetermined register. Therefore, a video signal whose signal format has been clarified once can be easily processed thereafter without executing the above-described various determination processes.

If they do not match, the image data does not change from white (image data is 255) to black (image data is 0) at the edge of the stripe, and the boundary is shown in FIG. ), An area 750 in which the image data indicates an intermediate value between 0 and 255 appears.

In such a case, the phase is adjusted in step S16 as follows. That is, the controller 381 changes the value of the delay shift register 383 little by little to change the delay amount of the phase delay unit 382, and sets the value of the delay shift register 383 so that the image data at the end does not indicate an intermediate value. Is set.

FIG. 6 is a diagram showing the relationship between the phase of the sampling clock 803 and the phase of the video signal 302.

In the figure, the output section of the video signal output device 2 which outputs a video signal in which a striped pattern repeats in the horizontal direction, as shown in FIGS.
Sampling clock 730 and pulsed video signal 73
1, the video signal 731 has a dull waveform 732 when input to the image signal input device 1, as shown in FIG. When sampling is performed by the sampling clock 733 (803) of the image signal input device 1, the image data becomes image data 734 indicating an intermediate value, as shown in FIG.

Therefore, in such a case, as shown in FIG. 11F, the video signal is shifted by a sampling clock 736 shifted by, for example, 1/3 phase from the sampling clock 733 of the video signal output device 2. When 732 is sampled, the image data becomes image data 737 corresponding to the original video signal 731 as shown in FIG.

Therefore, in this embodiment, the controller 38
1 changes the value set in the delay shift register 383 little by little, thereby gradually changing the delay amount of the phase delay unit 382, and setting the delay shift register 383 so that the image data at the boundary does not show an intermediate value. Set the value, and finally set the optimal delay time.

The video signal input at this time may be any signal as long as it has no intermediate value and the value of the black and white changes several times within one horizontal period. good.

The phase matching is performed in this manner. If it is determined in step S15 that the phases match, as described above, each parameter is set to R in step S11.
The result is stored in the AM 392 and the process ends.

FIG. 9 shows the number of pixels (horizontal direction and vertical direction) in the image period in the video signal by the pixel number setting means 33.
FIG. 2 is a block diagram showing a configuration of a main part of an embodiment for determining the same, and the same reference numerals as those in FIG. 1 represent the same or equivalent parts.

In the embodiment described with reference to FIG. 1, the controller 381 determines the number of pixels in the image period by the third frequency divider 3.
Although it was determined by referring to the ROM 393 based on the output signal of 80, in the present embodiment, the controller 381 does not perform arithmetic processing or the like, and determines the number of pixels.
You can now register.

In the figure, the H synchronizing signal is inputted to one input terminal of the fh detecting means 31 and the interlace detecting means 30, and the V synchronizing signal is inputted to the other input terminal of the interlace detecting means 30. Output signals of the detection means 31 and the interlace detection means 30 are input to an address bus of the ROM 32.

The data bus of the ROM 32 has a sampling frequency setting means 24, a horizontal synchronization address setting means 2
7, and the vertical synchronization address setting means 28.

In the apparatus having such a configuration, the fh detecting means 31 measures the frequency of the H synchronization signal by an appropriate means, and outputs a digital signal (for example, 3 bits) corresponding to the frequency.
Is output to the lower three bits of the address bus of the ROM 32.

On the other hand, the interlace detecting means 30 detects the presence or absence of interlace and outputs the detection signal to the upper 1 bit of the address bus of the ROM 32.

The ROM 32 outputs digital data stored at an address corresponding to data input to the address bus to the sampling frequency setting means 24, the horizontal synchronization address setting means 27, and the vertical synchronization address setting means.

According to the present embodiment, data relating to the number of pixels can be read from the ROM 32 based on the frequency of the H synchronization signal without performing calculations or the like by the controller 381.
, The load on the controller 381 is reduced, and the processing speed is improved.

FIG. 10 is a block diagram showing the configuration of the main part of the apparatus for adjusting the phase shift of the sampling signal between the output side and the input side of the video signal as described with reference to FIG. The same reference numerals as 1 denote the same or equivalent parts.

In the figure, the video signal is supplied to the A / D converter 3
The A / D converter 301 is connected to a latch 33 for storing the maximum value and a latch 34 for storing the minimum value. The latch 33 and the latch 34
Are input to the arithmetic circuit 35, respectively. The result of the operation (subtraction) in the operation circuit 35 is sent to the controller 38.
1 is input.

In the device having such a configuration, the video signal is sampled by the sampling signal output from the phase delay means 25 in the A / D converter 301, and the maximum value and the minimum value within a predetermined period are respectively latched. 33 and latch 34. Arithmetic circuit 35
Then, the difference between the image data stored in the latch 33 and the image data stored in the latch 34 is obtained for each predetermined period, and the difference is input to the controller 381.

The controller 381 detects a phase shift of the sampling signal from the difference, and controls the phase delay means 25 so as to eliminate the shift.

FIG. 11 is a block diagram showing a configuration of a main part of an apparatus for determining the image period without performing any arithmetic processing or the like in the controller 381. The same reference numerals as those in FIG. 1 denote the same or equivalent parts. I have.

In the figure, the output signal of the A / D converter 301 is input to the edge detecting means 36. The detection signal of the edge detecting means 36 is applied to the counting means 3 of the display period detecting means 39
7, a reset terminal of the counting means 37 receives an H synchronizing signal, and a clock terminal V
A clock signal from the CO 354 is input.

The counting result of the counting means 37 is input to the latch 38, and the output signal of the latch 38 is supplied to the controller 381.
Is input to

In the device having such a configuration, when the counting means 37 is reset by the H synchronizing signal and the video signal is output after the blanking period ends, the video signal is converted by the A / D converter 301 into a digital image signal. The data is converted into data and input to the edge detecting means 36.

The edge detecting means 36 detects an edge portion with reference to the digital image data, and inputs a detection signal to a trigger input terminal of the counting means 37. When the trigger is input, the counting means 37 starts counting the clock of the VCO 354.

Thereafter, when the edge detecting means 36 detects the end of the image period, the latch 38 holds the count value of the counting means 37 and outputs the count value to the controller 381.

FIG. 12 is a block diagram showing the structure of a main part of an embodiment in which a function of changing the threshold for edge detection is added to the edge detecting means 36 described with reference to FIG. 11, and is the same as FIG. Symbols represent the same or equivalent parts.

In the figure, the output signal of the A / D converter 301 is input to one input terminal of the comparison means 41, and the output signal of the level setting means 40 is input to the other input terminal. A controller 381 is connected to the level setting means 40, and the output level of the level setting means 40 is adjusted by the controller 381.

In the device having such a configuration, if the input video signal has an offset ΔV as shown in FIG. 17, the edge detecting means 36 described with reference to FIG. The edge portion C cannot be distinguished from the edge portion D in the actual video period, resulting in an unnatural image.

In such a case, in this embodiment, the controller 381 controls the level setting means 40 appropriately to change the offset of the comparing means 41 so that only the edge portion D is detected.

According to this embodiment, a faithful image can be reproduced even when the video signal has an offset ΔV.

FIG. 13 is a block diagram of a second embodiment of the present invention. The same reference numerals as those in FIG. 1 denote the same or equivalent parts. FIG. 14 is a flowchart for explaining the operation of this embodiment.

As is clear from the comparison with FIG. 1, the present embodiment is characterized in that a line memory 55 for storing only one line in the one-dimensional direction of an image is connected instead of the image memory 5. .

In FIG. 14, steps S1 to S4 are almost the same as the operations described with reference to FIG. 5, and therefore description thereof will be omitted.

Thereafter, in step S5b, one line of the video signal 302 output from the video signal output device 2 is stored in the line memory 55, and the stored 1
The video signal for the line is read out to the controller 381.

In step S6b, it is determined each time whether or not an image signal is included in the read one-line video signal. If no image signal is included, the process returns to step S5b and returns to step S5b. The storage of the minute video signal, the reading to the controller 381, and the determination of the presence or absence of the image signal are repeated.

If it is determined in step S6b that there is an image signal, in step S7b, the order of the H synchronization signal at this time is set as a blanking period in the vertical direction.

The determination of the blanking period, the image period, and the sampling frequency in the horizontal direction is performed in the same manner as in the embodiment described with reference to FIG. 1 using the video signal having the image signal.

Since the operation after step S8 is almost the same as the operation described with reference to FIG. 5, the description is omitted.

According to this embodiment, since the capacity of the memory can be reduced, the size of the device can be reduced.

FIG. 15 is a block diagram of a third embodiment of the present invention. The same reference numerals as in FIG. 1 denote the same or equivalent parts.

As is clear from comparison with FIG. 1 or FIG. 13, in this embodiment, no external memory for storing image data is provided, and the image data is directly stored in the controller 381.
In the controller 381, and the same determination processing as in each of the above embodiments is performed.

In this embodiment, a part of the controller 381 is replaced with the image memory 5 shown in FIG. 1 or the line memory 55 shown in FIG.
Can be used as

FIG. 15 is a block diagram of a fourth embodiment of the present invention. The same reference numerals as in FIG. 1 represent the same or equivalent parts.

This embodiment utilizes the sampling theorem.
By setting the sampling frequency to twice or more that of the video signal output device 2 and generating image data twice or more as in each of the above-described embodiments, and at the time of printing, performing interpolation processing on the image data and outputting the image data, phase matching is achieved. The feature is that the process has been abolished.

Hereinafter, the operation of this embodiment will be described with reference to the flowchart of FIG. 5, assuming that the same video signal as that of the embodiment described with reference to FIG. 1 is input.

That is, from the frequency of the H synchronization signal, the approximate frequency of the H synchronization signal is 647 kHz in step S1.
When the number of pixels in the H direction in the image period is determined to be 1280 and the number of pixels in the V direction is determined to be 1024 in steps S2 and S3, the controller 381 is determined.
In step S4, the number of sampling clocks SC per cycle of the H synchronization signal 303 is set in the same manner as described above.
Referring to the data table registered in the ROM 393, 3
600 (double the case of the first embodiment), which is set in the frequency division ratio shift register 356, and the H start register 362 and the V start register 372
For example, 0 is set as an initial setting value.

From the PLL circuit 350, the frequency 230 obtained by multiplying the value (3600) set in the frequency division ratio shift register 356 by the frequency (64 kHz) of the H synchronization signal 303 is output.
A clock signal of MHz is output as a sampling clock 802, and the sampling clock 802 is input to the A / D converter 301 via the phase delay unit 382 of the phase delay unit 25.

The A / D converter 301 A / D converts the video signal with the sampling clock 803, and
03 is divided into 3600 video signals for one cycle, and this is output to the image memory 5 as digital image data 305.

In the following, as in the case described with reference to FIG. 1, the first step of the automatic adjustment operation is the determination of the number of pixels in the image period in the video signal, and the image data obtained by using the parameters. When the registration in the image memory 5 is completed, the controller 381 reads out the contents of the image data stored in the image memory 5.

In step S7a, first, the controller 381 refers to the image data to determine a blanking period of the V synchronization signal.

In this embodiment, as in the case of the embodiment shown in FIG. 1, the period of the back porch is determined to be 10 addresses.

When the determination of the video period in the vertical direction is completed, the determination of the video period in the horizontal direction is started. Here, the sampling frequency is twice as large as that in the embodiment of FIG. , The blanking period becomes 100 addresses, and the video period becomes 2440 addresses.

When the blanking period and the video period are calculated in this way, the sampling frequency is calculated in the same manner as described above, and the parameters are reset.

Each parameter is determined in this way,
When the actual print operation is started, the A / D converter 30
The digital image data output from 1 is twice the original digital image data in the video signal output device 1.

The digital image data 305 output from the A / D converter 301 is subjected to an interpolation process in an interpolation device 650, and then stored in an image printing means or an image storage means via an interface.

According to this embodiment, since the sampling frequency is at least twice the frequency of the original signal, the original video signal can be faithfully reproduced without performing the phase adjustment of the sampling signal. Become like

In the above-described embodiment, the determination of the number of pixels in the first step in the signal format determination, the determination of the image period and the sampling frequency in the second step, and the determination of the video signal and the sampling signal in the third step. Has been described as being automatically performed, but the present invention is not limited to this, and only the determination in the first and second stages is automatically performed. May not be performed, or may be performed manually.

[0206]

As apparent from the above invention, the following effects are achieved according to the present invention.

(1) By determining the frequency of the horizontal synchronizing signal, the number of pixels in an image period of a video signal whose signal format is unknown can be automatically determined.

(2) Based on the luminance information of the video signal,
The image period can be automatically determined.

(3) The frequency of the quantized clock signal of the video signal at the video signal source can be determined based on the determined number of pixels and the image period. Sampling can be performed at the same frequency as the quantization clock signal.

Therefore, faithful image data can be output to a subsequent display device or the like without dropping pixels included in the image.

(4) Using the parameters determined as in (1) to (3) above, process a video signal having a video signal whose signal format is unknown and which repeats black and white in the horizontal direction. By generating digital image data and referring to the image data, it is possible to match the phase of the video signal with the phase of the sampling signal, thereby preventing information loss during quantization and image degradation. Thus, faithful image data can be output to a subsequent display device or the like.

(5) The parameters determined as in the above (1) to (4) are stored, the stored parameters are read out as necessary, and these can be used. Once the signal format is known, the video signal can be easily processed thereafter.

(6) If the video signal source is sampled at a frequency twice or more the frequency of the quantized clock signal on the sending side, faithful image data can be transmitted to a subsequent display device or the like without impairing the original information amount. Can be output.

[Brief description of the drawings]

FIG. 1 is a block diagram of an image signal input device according to an embodiment of the present invention.

FIG. 2 is a perspective view of an image signal input device.

FIG. 3 is a timing chart of a video signal.

FIG. 4 is an explanatory diagram of an image size corresponding to a synchronization signal frequency.

FIG. 5 is a flowchart illustrating the operation of FIG. 1;

FIG. 6 is a diagram showing a relationship between a sampling signal and a video signal.

FIG. 7 is a diagram for explaining how to obtain the number of sampling clocks set in the frequency division ratio shift register.

FIG. 8 is a diagram for explaining a phase shift of a sampling signal.

FIG. 9 is a block diagram of an apparatus for calculating a frequency of a horizontal synchronization signal.

FIG. 10 is a block diagram of an apparatus for correcting a phase shift of a sampling signal.

FIG. 11 is a block diagram of an apparatus for detecting an image period.

FIG. 12 is a block diagram of an apparatus for detecting an image period of a video signal having an offset.

FIG. 13 is a block diagram of a second embodiment of the present invention.

FIG. 14 is a flowchart illustrating the operation of FIG.

FIG. 15 is a block diagram of a third embodiment of the present invention.

FIG. 16 is a block diagram of a fourth embodiment of the present invention.

FIG. 17 is a diagram for explaining the operation of FIG. 12;

FIG. 18 is a timing chart showing a configuration of a video signal.

[Explanation of symbols]

1. Image signal input device, 2. Video signal output device, 4.
Common bus, 5 ... image memory, 20 ... image printing means,
21 ... image storage means, 22, 23 ... interface,
25 ... phase delay means, 26 ... horizontal input head position setting means, 27 ... horizontal synchronization address generation means, 28 ... vertical synchronization address generation means, 29 ... horizontal input head position setting means,
30 ... interlace detecting means, 55 ... line memory, 3
01 ... A / D converter, 381 ... Controller.

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[Procedure amendment]

[Submission Date] February 28, 2002 (2002.2.2)
8)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Name of invention

[Correction method] Change

[Correction contents]

[Title of the Invention] Image output device

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

3. The phase adjustment circuit according to claim 1 , further comprising a phase delay unit for delaying the phase of the sampling clock so that the phase of the video signal of the specific pattern coincides with the phase of the sampling clock. The image output device according to claim 2.

4. The frequency adjusting circuit according to claim 1 , wherein said detecting means detects information relating to a frequency or a cycle of a horizontal synchronizing signal input together with said video signal, and detects one horizontal cycle of said horizontal synchronizing signal based on said detected information. Calculating means for obtaining parameters relating to the image period and the sampling frequency, and adjusting the frequency of the sampling clock from the sampling clock generating circuit based on the parameters relating to the image period and the sampling frequency obtained by the calculating means. The image output device according to claim 2 or 3, wherein:

5. further comprising an image memory for storing the digital signal from the A / D converter as image data, wherein the frequency adjustment circuit, in one horizontal cycle of the horizontal synchronizing signal read from the image memory 5. The image output device according to claim 4, wherein a frequency of a sampling clock from the sampling clock generating circuit is adjusted based on a difference between an image period and the image period obtained by the arithmetic unit.

6. An A / D converter capable of inputting at least a plurality of video signals having different horizontal frequencies, sampling the input video signal and converting the input video signal into a digital signal.
An image output device having a sampling clock generation circuit for supplying a sampling clock to the D converter and outputting an image based on a digital signal from the A / D converter, wherein a video signal of a specific pattern is input And a phase adjusting means for adjusting the phase of the sampling clock when the determining means determines that a video signal of a specific pattern has been input.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0001

[Correction method] Change

[Correction contents]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input video signal
The present invention relates to an image output device for outputting an image, and particularly to a video signal.
The sampling clock used when converting to digital signals
Image with means for adjusting the lock frequency and phase
The present invention relates to an image output device.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0024

[Correction method] Change

[Correction contents]

It is an object of the present invention to provide a method suitable for an input video signal.
An image output device capable of obtaining a sampling clock .

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction contents]

That is, the present invention adjusts the image output device.
Switch is provided and responds to operation of this adjustment switch
To automatically adjust the frequency of the sampling clock.
This is a feature of the present invention. Also, specific patterns
When the video signal of the
The phase of the clock is adjusted.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0027

[Correction method] Deleted

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0028

[Correction method] Change

[Correction contents]

[0028]

[Function] When the content of the video signal changes over time,
Always adjust the frequency of the pulling clock
And that the sampling clock frequency changes frequently
Becomes unstable. The present invention provides an image output device with an adjustment switch.
Switch in response to the operation of this adjustment switch.
Since the number adjustment operation is started, the adjustment switch
The video signal changes when the switch is not operated.
No adjustment operation of the sampling clock frequency is performed.
No. Therefore, it is affected by changes in the content of the video signal
And a stable sampling clock can be obtained.
You. Also, by operating the adjustment switch,
At the time of
You.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0029

[Correction method] Change

[Correction contents]

When inputting a video signal of a specific pattern,
The phase can be adjusted by adjusting the phase of the sampling clock.
Phase adjustment can be performed accurately.

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0030

[Correction method] Deleted

[Procedure amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Deleted

[Procedure amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0032

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[Procedure amendment 12]

[Document name to be amended] Statement

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[Procedure amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0206

[Correction method] Change

[Correction contents]

[0206]

As described above, according to the present invention, the video signal
Stable and appropriate frequency without being affected by the contents of
Can be obtained.

[Procedure amendment 14]

[Document name to be amended] Statement

[Correction target item name] 0207

[Correction method] Deleted

[Procedure amendment 15]

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[Document name to be amended] Statement

[Correction target item name] 0211

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 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroyuki Kimura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Home Appliance Research Laboratory, Hitachi, Ltd. (72) Yoshiaki Mochimaru 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Hitachi Image Information Systems, Ltd. (72) Inventor Yasuyuki Kobori 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Electric Appliance Research Laboratory, Hitachi, Ltd. (72) Kentaro Hanma 1410, Inada, Kata-shi, Katsuta, Ibaraki, Inc. F-term in Hitachi Tokai Plant (reference) 5C058 AA06 BA04 BA12 BA22 BB10 BB13 BB19 BB21 5C082 AA32 BA29 BB15 BB22 CA84 DA53 DA76 DA86 MM02 MM06 MM06 MM10

Claims (2)

[Claims] 1. A video signal consisting of a horizontal synchronization signal, a vertical synchronization signal, and a video signal having various signal parameter specifications and, when the video signal is input, an image faithful to the video signal can be displayed. In a simple image display device, an A / A which performs quantization of the video signal with a sampling clock having substantially the same frequency as a reference clock constituting the video signal is used.
D conversion means, image memory means for holding image data corresponding to the video period of the video signal out of the output of the conversion means, and display means for displaying the output of the memory means as an image. Image display device. 2. A video signal consisting of a horizontal synchronizing signal, a vertical synchronizing signal, and a video signal having various signal parameter specifications, and when the video signal is input, an image faithful to the video signal can be displayed. In an image display apparatus, A / D conversion means for quantizing the video signal with a sampling clock having the same frequency as a reference clock constituting the video signal, and when a video signal having a predetermined image pattern is inputted, Phase adjusting means for adjusting the phase of the sampling clock, image memory means for holding image data corresponding to the video period of the video signal among the outputs of the A / D converter means, and displaying the output of the memory means in image display An image display device comprising: