JPH10135319A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To flatten the surface of a filler filling up trenches not only at the straight sections of the trenches, but also at the crossing section of the trenches, by providing an island-like part surrounded by the trenches at the crossing section of the trenches and filling up the trenches with the filler. SOLUTION: After a silicon oxide layer 2 is formed on the upper surface of a silicon substrate 1, a polycrystalline silicon layer 3 is formed on the layer 2 by the low-pressure CVD method. Then, a silicon nitride layer 4 and a photoresist layer are successively formed on the layer 3 and an opening is formed, so that the opening can surround an island-like part 4a by removing the silicon nitride layer 4 by performing wet etching by using the photoresist layer as a mask. After the opening is formed, a silicon oxide layer 2c is formed on the side walls of the trenches 9 formed of the opening and a polysilicon layer 10 is formed by the low-pressure CVD method as the filler of the trenches 9. Therefore, the occurrence of disconnection, etc., in a wiring pattern can be prevented, because the surface of the filler at the crossing section of the trenches 9 can be flattened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device capable of flattening the surface of an isolation trench and a method of manufacturing the same.

[0002]

2. Description of the Related Art In an integrated circuit, an element isolation structure formed by forming a trench pattern is effective in reducing the size of a high breakdown voltage element, suppressing generation of a parasitic element, and the like. One of the problems in the trench pattern forming process is to planarize the surface of the filling layer. For example, in order to prevent disconnection or short circuit of the gate polysilicon or polysilicon resistor formed by polycrystalline silicon (Poly Si), the height of the trench surface should be 0.5 μm.
m or less. FIG. 5 shows a cross-sectional structure of a conventional example of the trench. In FIG. 5, a silicon oxide layer 32 and a polysilicon layer 3 are formed on a silicon substrate 31.
3 and a silicon nitride layer 34 are sequentially laminated.
The element isolation trench 35 includes the silicon nitride layer 34,
It is formed to penetrate the polysilicon layer 33 and the silicon oxide layer 32 and reach the silicon substrate 31. The silicon oxide layer 32 is formed on the wall surface of the trench 35, and the polysilicon layer 36 is formed so as to fill the trench 35.

However, in the conventional trench 35 shown in FIG. 5, since the area of the opening is larger at the intersection than at the straight portion (not intersecting), the polysilicon at the time of forming the filling layer of the trench 35 is formed. Since the deposition rate is effectively slowed down at the intersection, if the thickness of the polysilicon layer is adjusted to be flat at the straight portion (linear pattern portion), the intersection (or corner portion) of the trench 35 is formed. ), A step is formed on the surface due to the concave portion 36a (or a void (not shown)). For this reason, there has been a problem that disconnection or short-circuit of the gate polysilicon layer and the polysilicon resistor formed on the polysilicon layer 36 occurs, and furthermore, a coverage failure of the wiring formed thereon is caused. To solve this problem, refer to
-263454 discloses a trench structure for element isolation of the semiconductor device shown in FIG. In FIG. 6, a projection 40b is formed at an intersection 40a of the trench 40 so as to reduce the width of the trench 40.
Since the width of 0a is substantially equal to the width of the non-intersecting portion, it is possible to prevent the formation of the concave portions and voids on the surface of the filler at the intersecting portion 40a. In addition, 41 is an element formation region.

[0004]

However, the element isolation trench structure of the semiconductor device shown in FIG. 6 is effective only when three trenches intersect in a T-shape at the intersection 40a. There is a drawback that it cannot be applied when four or more trenches intersect. Therefore,
An object of the present invention is to eliminate the above-mentioned drawbacks of the conventional example and to flatten the surface of a filling layer of an element isolation trench of a semiconductor device not only at its linear portion but also at the intersection of four or more trenches. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same.

[0005]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a trench for element isolation, wherein the trench is formed at an intersection of the trench. The method includes a step of forming the trench while leaving an enclosed island-shaped portion, and a step of filling the trench with a filler.

According to the structure of the first aspect of the present invention, the area of the opening at the intersection of the trenches is substantially reduced and becomes closer to the area of the opening at the part where the trench does not intersect. The surface can be flattened not only at the straight portion of the trench but also at the intersection.

Further, according to a second aspect of the invention, there is provided a semiconductor device which is element-isolated by a trench, wherein the intersection of the trench has an island-shaped portion surrounded by the trench, and the trench is filled with a filler. A semiconductor device characterized in that:

According to the configuration of the second aspect, similarly to the first aspect, the surface of the filling material of the element isolation trench of the semiconductor device can be flattened.

[0009]

Next, an embodiment of the present invention will be described with reference to the drawings. 1 to 3 are cross-sectional views illustrating a manufacturing method of the embodiment. 2 is a continuation of FIG. 1, and FIG. 3 is a continuation of FIG. First, as shown in FIG. 1A, a silicon oxide (S
iO ₂ ) layer 2 is formed by a thermal oxidation method. Next, a polycrystalline silicon (Poly Si) layer 3 is formed on the silicon oxide layer 2 by a low pressure CVD method. Furthermore, the polycrystalline silicon layer 3
A silicon nitride (SiN) layer 4 is formed thereon by a low pressure CVD method. Next, as shown in FIG. 1B, a first photoresist layer 5 is formed on the silicon nitride layer 4, and an opening 5b is formed by ordinary photolithography so as to surround the island-shaped portion 5a. . Next, as shown in FIG. 1C, the silicon nitride layer 4 is removed by wet etching using the first photoresist layer 5 as a mask. After that, the first photoresist layer 5 is peeled off. As a result, an opening 4b (corresponding to the opening 5b) is formed so as to surround the island-shaped portion 4a (corresponding to the island-shaped portion 5a).

Next, as shown in FIG. 2A, a portion of the polysilicon layer 3 which is not covered by the silicon nitride layer 4 (corresponding to the opening 4b) is formed by a thermal oxidation method. To As a result, an island portion 3a of the polysilicon layer 3 is formed. Next, a non-doped silicon (NSG) is formed so as to cover the silicon oxide layer 2b and the silicon nitride layer 4.
(Cate Glass) layer 6 is formed by a normal pressure CVD method. Thereafter, a second photoresist layer 7 is formed on the NSG layer 6, and an opening 7b is formed by photolithography so as to surround the island portion 7a. In addition, this island-shaped portion 7
The position “a” corresponds to the position of the island-shaped portion 4 a of the silicon nitride layer 4. Next, as shown in FIG. 2B, the NSG layer 6 and the silicon oxide layer 2 (including the silicon oxide layer 2b) are wet-etched using the second photoresist layer 7 as a mask to form holes 8. . The hole 8 is formed so as to surround the island portion 20. In addition, the island-shaped portion 20
FIG. 2B shows an island-like portion 2 of the silicon oxide layer 2.
a, an island portion 3a of the polysilicon layer 3, an island portion 4a of the silicon nitride layer 4, and an island portion 6a of the NSG layer 6. Next, the second photoresist layer 7 is peeled off by ashing.

Next, as shown in FIG. 2C, a trench 9 is formed in the silicon substrate 1 by dry etching using the NSG layer 6 as a mask. As a result, the lowermost layer of the island portion 20 becomes the island portion 1a of the silicon substrate 1. In addition,
9a is the bottom of the trench 9. After that, the NSG layer 6 is removed by wet etching. Next, as shown in FIG. 3, a silicon oxide layer 2c is formed on the side walls of the trench 9 by a thermal oxidation method, and then a polysilicon layer 10 serving as a filler for the trench 9 is formed by a low pressure CVD method. The polysilicon layer 10 is removed by patterning by photolithography except for the portion shown in FIG. 10a is the surface of the polysilicon layer 10.
As the filling material of the trench 9, the polysilicon layer 1 is used.
Members other than zero can be used. In consideration of the accuracy of the photolithography process, productivity, breakdown voltage for element isolation of a semiconductor device, and the like, the width of the trench 9 is, for example, 10 μm.
About.

FIG. 4 shows a plan view of a trench of a semiconductor device manufactured by the manufacturing method shown in the above embodiment. In FIG. 4, a polysilicon layer 12 as a trench filling material is formed. The silicon nitride layer 11 (corresponding to the silicon nitride layer 4) is formed so as to cover portions other than the trench. An island-like portion 21 (corresponding to the above-mentioned island-like portion 20) as a compensation pattern is formed at the intersection 12a of the polysilicon layer 12. Therefore, when the thickness of the polysilicon layer serving as the filling layer is adjusted to the portion where the trench pattern is linear, the portion of the polysilicon layer 36 where the trench pattern intersects as shown in FIG. Although the concave portion 36a is formed on the surface, if the compensation pattern is formed as shown in FIG.
Even if the filling area at the intersection 12a is substantially reduced and the thickness of the polysilicon layer is adjusted to the linear portion of the trench pattern, the surface 10 of the polysilicon layer 10 as shown in FIG.
a can be made flat.

The shape of the intersection of the trenches is not limited to the shape shown in the above embodiment, but may be a shape in which three or more trenches intersect in an arbitrary state. Further, the shape of the island portion as the compensation pattern formed at the intersection is not limited to that shown in the above-described embodiment, but may be any shape.

[0014]

According to the method of manufacturing a semiconductor device according to the first aspect of the present invention, the surface of the filling material of the element isolation trench can be flattened not only at its linear portion but also at its intersection. For this reason. Since the surface of the filling material of the element isolation trench is not flat, disconnection or poor coverage of a wiring pattern formed on the filling material of the trench can be prevented. Further, according to the semiconductor device of the second invention, the surface of the filler of the trench for element isolation of the semiconductor device can be flattened not only at the linear portion but also at the intersection as in the first invention. . For this reason, disconnection of the wiring pattern provided on the filling material of the trench, poor coverage, and the like can be prevented.

[Brief description of the drawings]

FIG. 1 is a sectional view for explaining an embodiment of the present invention.

FIG. 2 is an explanatory cross-sectional view of the embodiment, and is a continuation of FIG.

FIG. 3 is an explanatory cross-sectional view of the embodiment, and is a continuation of FIG. 2;

FIG. 4 is an explanatory plan view of the embodiment.

FIG. 5 is a sectional view of a conventional example.

FIG. 6 is a plan view of another conventional example.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 9 trench 10 polysilicon layer 10a surface 20 island portion 12 polysilicon layer 12a intersection of polysilicon layer 21 island portion

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device having an element isolation trench, wherein the trench is formed by leaving an island portion surrounded by the trench at an intersection of the trench, and the trench is filled. And a step of embedding a material. 2. A semiconductor device element-isolated by a trench, wherein an intersection of the trench is provided with an island-shaped portion surrounded by the trench, and the trench is filled with a filler. Semiconductor device.