JPH1012637A - Apparatus and method for mounting chip - Google Patents

Apparatus and method for mounting chip

Info

Publication number
JPH1012637A
JPH1012637A JP8158249A JP15824996A JPH1012637A JP H1012637 A JPH1012637 A JP H1012637A JP 8158249 A JP8158249 A JP 8158249A JP 15824996 A JP15824996 A JP 15824996A JP H1012637 A JPH1012637 A JP H1012637A
Authority
JP
Japan
Prior art keywords
chips
substrate
chip
stage
corrected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8158249A
Other languages
Japanese (ja)
Other versions
JP2770817B2 (en
Inventor
Nobuhiro Mikami
伸弘 三上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8158249A priority Critical patent/JP2770817B2/en
Publication of JPH1012637A publication Critical patent/JPH1012637A/en
Application granted granted Critical
Publication of JP2770817B2 publication Critical patent/JP2770817B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

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  • Supply And Installment Of Electrical Components (AREA)
  • Die Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve position accuracy of chip mounting onto a substrate. SOLUTION: A plurality of chips 2 picked up from a wafer ring 1 are placed on a correction stage 3, and the position of the chip 2 is corrected so as to provide the same position relation where it is mounted on a substrate 5. Then, the plurality of the chips 2 positionally corrected on the correction stage 3 are attracted by a two sided channel collet 6. Then, the positions of a mount stage 4 and the two sided channel collet 6 are corrected such that their mounting positions are conicident with the substrate 5 on the mount stage 4. After the correction, the plurality of the chips 2 are scribed and are mounted on the substrate simultaneously whereby it is prevented from being affected by expansion of the mount stage 4 due to a temperature change, and is completely prevented from being affected by absolute accuracy error of a chip mounting arm between the chips.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、チップマウント装
置及び方法に関し、特にヒーター内蔵のステージ上の基
板に複数個のチップをコレットで保持してスクラブを行
いマウントする装置及び方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip mounting apparatus and method, and more particularly to an apparatus and method for scrubbing and mounting a plurality of chips on a substrate on a stage with a built-in heater by using a collet.

【0002】[0002]

【従来の技術】従来の技術としては、「松下電器産業株
式会社製DM40M−H」のようなチップマウント装置
がある。この従来のチップマウント装置では、フィルム
上にウェハを分割したチップ群が付着されたウェハリン
グからチップを1つずつチップ移載アームによりピック
アップし、この際にチップ上のマークを認識してチップ
の位置、向きを計測し、チップ移載アームなどによりチ
ップの位置を補正してチップを1個ずつスクラブして基
板上にマウントしていた。
2. Description of the Related Art As a conventional technique, there is a chip mount apparatus such as "DM40M-H manufactured by Matsushita Electric Industrial Co., Ltd." In this conventional chip mounter, chips are picked up one by one by a chip transfer arm from a wafer ring on which a chip group obtained by dividing a wafer on a film is attached, and at this time, a mark on the chip is recognized and The position and orientation are measured, the position of the chip is corrected by a chip transfer arm or the like, and the chips are scrubbed one by one and mounted on a substrate.

【0003】[0003]

【発明が解決しようとする課題】第1の問題点は、複数
のチップを1個ずつマウトしている間に基板を固定して
いるステージの温度変化により、先にマウントしたチッ
プの位置がずれ、チップ相互の位置がばらつくというこ
とである。
The first problem is that the position of the previously mounted chip shifts due to the temperature change of the stage fixing the substrate while the plurality of chips are mounted one by one. This means that the positions of the chips vary.

【0004】その理由は、温度変化により基板を固定し
ている部分が伸縮する事が理由である。
[0004] The reason is that the portion fixing the substrate expands and contracts due to a temperature change.

【0005】第2の問題点は、チップ移載アームにより
チップの搬送を個々に実施するために、チップ移載アー
ムの絶対位置決め精度誤差がチップの位置精度にそのま
ま影響する点である。
[0005] The second problem is that since the chip transfer arms individually carry the chips, the absolute positioning accuracy error of the chip transfer arm directly affects the chip position accuracy.

【0006】[0006]

【課題を解決するための手段】本発明のチップマウント
装置は、基板を載置し、加熱用ヒータを備えたマウント
ステージと、ウェハリングからピックアップされてきた
複数のチップを載置し、これらチップが前記基板上にマ
ウントする位置関係でしかも1列に並ぶようにこれらチ
ップそれぞれの位置を個々に補正する補正ステージと、
この補正ステージ上の位置補正された複数のチップを1
列に並べたまま同時に吸着して前記基板上のマウント位
置に位置決めしスクラブを行ってマウントする2面角錐
コレットとを備えている。
A chip mounting apparatus according to the present invention mounts a substrate, mounts a mount stage provided with a heater for heating, and mounts a plurality of chips picked up from a wafer ring. A correction stage for individually correcting the position of each of the chips so that they are mounted on the substrate in a positional relationship and arranged in a line.
A plurality of chips whose position on the correction stage has been corrected
And a dihedral pyramid collet that is simultaneously adsorbed while positioned in a row, positioned at the mounting position on the substrate, scrubbed and mounted.

【0007】本発明のチップマウント方法は、ウェハリ
ングからピックアップした複数のチップを補正ステージ
に載置して、基板上にマウントする位置関係でしかも1
列に並ぶように前記複数のチップの位置を補正し、前記
補正ステージ上の位置補正された複数のチップを1列に
並べたまま2面角錐コレットで吸着して、基板上のマウ
ント位置に位置決めしスクラブを行ってマウントするこ
とを特徴とする。
According to the chip mounting method of the present invention, a plurality of chips picked up from a wafer ring are placed on a correction stage and mounted on a substrate in a positional relationship.
The positions of the plurality of chips are corrected so as to be arranged in a row, and the plurality of chips whose positions have been corrected on the correction stage are arranged in a line and sucked by a dihedral pyramid collet to be positioned at a mounting position on a substrate. It is characterized by performing scrubbing and mounting.

【0008】[0008]

【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して説明する。
Next, embodiments of the present invention will be described with reference to the drawings.

【0009】図1は本発明の実施の形態のチップマウン
ト装置の平面図である。
FIG. 1 is a plan view of a chip mount device according to an embodiment of the present invention.

【0010】このチップマウント装置は、ウェハリング
1からピックアップされたチップ2の位置,向きを補正
するために縦横及び回転方向に移動可能な複数個の補正
ステージ3と基板2を載置し、基板2を加熱するための
ヒーターが内蔵され、基板2のθ(回転)方向の位置補
正ができるマウトステージ4と、チップ2の対向する2
辺を支持し、複数チップ2を同時吸着できる図2に示さ
れている2面角錐コレット6と、チップ2と基板5との
認識をするためのカメラ7と、2面角錐コレット6とカ
メラ7を移動させ、チップ2の移載、スクラブを行う移
動機構8とを備えている。
This chip mounting apparatus mounts a plurality of correction stages 3 and a substrate 2 which can be moved in the vertical and horizontal directions and in a rotational direction in order to correct the position and orientation of a chip 2 picked up from a wafer ring 1. A mute stage 4 which has a built-in heater for heating the substrate 2 and can correct the position of the substrate 2 in the θ (rotation) direction;
A dihedral pyramid collet 6 shown in FIG. 2 which supports sides and can simultaneously adsorb a plurality of chips 2, a camera 7 for recognizing the chip 2 and the substrate 5, a dihedral pyramid collet 6 and a camera 7 And a moving mechanism 8 for transferring and scrubbing the chips 2.

【0011】図2は2面角錐コレット6の斜視図であ
り、下面に断面が台形状の溝が設けられ、この断面の形
状の台形の上辺の幅と下辺の幅の中間がチップ2の幅と
なる寸法で、この溝内を真空に引くことにより1列に並
べられた複数のチップ2を吸着することができる。2面
角錐コレット6に吸着されたチップ2は溝の両側の斜面
に対向する2辺が当接し、スクラブ時に溝と直角な方向
に振動を受けても2面角錐コレット6に対する位置がず
れることはない。
FIG. 2 is a perspective view of the dihedral pyramid collet 6, in which a groove having a trapezoidal cross section is provided on the lower surface, and the width of the upper side and the lower side of the trapezoid of this cross sectional shape is the width of the chip 2. By evacuating the inside of the groove with the following dimensions, a plurality of chips 2 arranged in a line can be sucked. The chip 2 adsorbed by the dihedral pyramid collet 6 abuts on two sides facing the slopes on both sides of the groove, and the position of the chip 2 with respect to the dihedral pyramid collet 6 does not deviate even if it is vibrated in a direction perpendicular to the groove during scrubbing. Absent.

【0012】次に、本実施の形態の動作を説明する。Next, the operation of this embodiment will be described.

【0013】ウェハリング1を所定の位置に固定し、図
示しないチップ移載アームによりウェハリング1上のチ
ップ2を1個ずつ補正ステージ3に移載する。複数の補
正ステージ3それぞれに1個ずつチップ2を載せてから
カメラ7でチップ2それぞれの位置を測定し、補正ステ
ージ3を駆動して複数のチップ2を基板5上にマウント
される位置関係となるように1列に位置決めする。
The wafer ring 1 is fixed at a predetermined position, and the chips 2 on the wafer ring 1 are transferred to the correction stage 3 one by one by a chip transfer arm (not shown). The chip 2 is mounted on each of the plurality of correction stages 3, and the position of each of the chips 2 is measured by the camera 7, and the correction stage 3 is driven to mount the plurality of chips 2 on the substrate 5. So that they are aligned in one row.

【0014】次に、2面角錐コレット6を移動機構8に
より補正ステージ3に載置された複数のチップ2上に移
動させ、複数のチップ2を1列に並べたまま2面角錐コ
レット6に吸着する。ここで、2面角錐コレット6に同
時に吸着された複数個のチップ2は、2面角錐コレット
8の溝の方向の位置精度は補整ステージ3で補正された
精度に保たれ、溝と直角な方向の位置は溝の両側の斜面
に規制され、2面角錐コレット6の製作の際の精度で決
まる位置精度となる。
Next, the dihedral pyramid collet 6 is moved by the moving mechanism 8 onto the plurality of chips 2 placed on the correction stage 3, and the dihedral pyramid collet 6 is arranged in a line in the dihedral pyramid collet 6. Adsorb. Here, the plurality of chips 2 simultaneously sucked by the dihedral pyramid collet 6 maintain the positional accuracy in the direction of the groove of the dihedral pyramid collet 8 at the accuracy corrected by the compensation stage 3, and the direction perpendicular to the groove. Is restricted by the slopes on both sides of the groove, and the positional accuracy is determined by the accuracy when the dihedral pyramid collet 6 is manufactured.

【0015】次にマウントステージ4上の基板5をカメ
ラ7で認識し、マウント位置が合うようにマウントステ
ージ4の回転方向の位置を補正し、移動機構8により2
面角錐コレット6を基板5上に位置決めする。位置決
め、補正後、複数個のチップ2を2面角錐コレット6に
よりその溝と直角な方向にスクラブをかけ、基板に同時
にマウントをする。
Next, the substrate 5 on the mount stage 4 is recognized by the camera 7, and the position in the rotational direction of the mount stage 4 is corrected so that the mount position matches.
The face pyramid collet 6 is positioned on the substrate 5. After positioning and correction, a plurality of chips 2 are scrubbed by a dihedral pyramid collet 6 in a direction perpendicular to the grooves, and are simultaneously mounted on a substrate.

【0016】[0016]

【発明の効果】以上説明したように、本発明のチップマ
ウント装置及び方法は、複数個のチップを2面角錐コレ
ットに吸着して同時に基板上にマウントするため、基板
を載置するマウントステージの温度変化による伸縮の影
響を受けにくいばかりでなく、チップ間における、チッ
プ移載アームの絶対精度誤差による影響を皆無にでき、
チップマウントの位置精度を向上できるという効果があ
る。
As described above, the chip mounting apparatus and method according to the present invention employ a mount stage for mounting a substrate, since a plurality of chips are adsorbed on the dihedral pyramid collet and simultaneously mounted on the substrate. In addition to being less susceptible to the effects of expansion and contraction due to temperature changes, the effect of the absolute accuracy error of the chip transfer arm between chips can be eliminated,
There is an effect that the positional accuracy of the chip mount can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態の平面図である。FIG. 1 is a plan view of an embodiment of the present invention.

【図2】図1中の2面角錐コレット6の斜視図である。FIG. 2 is a perspective view of a dihedral pyramid collet 6 in FIG.

【符号の説明】[Explanation of symbols]

1 ウェハリング 2 チップ 3 補正ステージ 4 マウントステージ 5 基板 6 2面角錐コレット 7 カメラ 8 移動機構 DESCRIPTION OF SYMBOLS 1 Wafer ring 2 Chip 3 Correction stage 4 Mount stage 5 Substrate 6 Dihedral pyramid collet 7 Camera 8 Moving mechanism

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板を載置し、加熱用ヒータを備えたマ
ウントステージと、ウェハリングからピックアップされ
てきた複数のチップを載置し、これらチップが前記基板
上にマウントする位置関係でしかも1列に並ぶようにこ
れらチップそれぞれの位置を個々に補正する補正ステー
ジと、この補正ステージ上の位置補正された複数のチッ
プを1列に並べたまま同時に吸着して前記基板上のマウ
ント位置に位置決めしスクラブを行ってマウントする2
面角錐コレットとを含むことを特徴とするチップマウン
ト装置。
1. A substrate is mounted, a mount stage provided with a heater for heating, and a plurality of chips picked up from a wafer ring are mounted, and the chips are mounted on the substrate in a positional relationship. A correction stage for individually correcting the position of each of these chips so as to be arranged in a row; and a plurality of chips whose positions on the correction stage have been corrected are simultaneously suctioned while being arranged in a line and positioned at a mounting position on the substrate. Perform scrub and mount 2
A chip mount device comprising a face pyramid collet.
【請求項2】 ウェハリングからピックアップした複数
のチップを補正ステージに載置して、基板上にマウント
する位置関係でしかも1列に並ぶように前記複数のチッ
プの位置を補正し、前記補正ステージ上の位置補正され
た複数のチップを1列に並べたまま2面角錐コレットで
吸着して、基板上のマウント位置に位置決めしスクラブ
を行ってマウントすることを特徴とするチップマウント
方法。
2. The correction stage, wherein a plurality of chips picked up from a wafer ring are mounted on a correction stage, and the positions of the plurality of chips are corrected so as to be arranged in a line in a positional relationship for mounting on a substrate. A chip mounting method characterized in that a plurality of the chips whose positions have been corrected are arranged in a line, are sucked by a dihedral pyramid collet, positioned at a mounting position on a substrate, scrubbed, and mounted.
JP8158249A 1996-06-19 1996-06-19 Chip mounting apparatus and method Expired - Lifetime JP2770817B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8158249A JP2770817B2 (en) 1996-06-19 1996-06-19 Chip mounting apparatus and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8158249A JP2770817B2 (en) 1996-06-19 1996-06-19 Chip mounting apparatus and method

Publications (2)

Publication Number Publication Date
JPH1012637A true JPH1012637A (en) 1998-01-16
JP2770817B2 JP2770817B2 (en) 1998-07-02

Family

ID=15667514

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8158249A Expired - Lifetime JP2770817B2 (en) 1996-06-19 1996-06-19 Chip mounting apparatus and method

Country Status (1)

Country Link
JP (1) JP2770817B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015038074A1 (en) * 2013-09-13 2015-03-19 Orion Systems Integration Pte Ltd System and method for positioning a semiconductor chip with a bond head, thermal bonding system and method
KR20180106876A (en) * 2017-03-16 2018-10-01 토와 가부시기가이샤 Semiconductor package arrange apparatus, manufacturing apparatus, arrange method of semiconductor package and manufacturing method of electronic part
KR20180108434A (en) * 2017-03-23 2018-10-04 토와 가부시기가이샤 Semiconductor package arrange apparatus, manufacturing apparatus, arrange method of semiconductor package and manufacturing method of electronic part
KR20180111513A (en) * 2017-03-31 2018-10-11 토와 가부시기가이샤 Cutting apparatus, method of attaching semiconductor package and manufacturing method of electronic component

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015038074A1 (en) * 2013-09-13 2015-03-19 Orion Systems Integration Pte Ltd System and method for positioning a semiconductor chip with a bond head, thermal bonding system and method
KR20180106876A (en) * 2017-03-16 2018-10-01 토와 가부시기가이샤 Semiconductor package arrange apparatus, manufacturing apparatus, arrange method of semiconductor package and manufacturing method of electronic part
KR20180108434A (en) * 2017-03-23 2018-10-04 토와 가부시기가이샤 Semiconductor package arrange apparatus, manufacturing apparatus, arrange method of semiconductor package and manufacturing method of electronic part
KR20180111513A (en) * 2017-03-31 2018-10-11 토와 가부시기가이샤 Cutting apparatus, method of attaching semiconductor package and manufacturing method of electronic component

Also Published As

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JP2770817B2 (en) 1998-07-02

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Effective date: 19980317