JPH10124472A - 多ノードｓｃｉコンピュータシステムの経路指定方法 - Google Patents

多ノードｓｃｉコンピュータシステムの経路指定方法

Info

Publication number
JPH10124472A
JPH10124472A JP27827697A JP27827697A JPH10124472A JP H10124472 A JPH10124472 A JP H10124472A JP 27827697 A JP27827697 A JP 27827697A JP 27827697 A JP27827697 A JP 27827697A JP H10124472 A JPH10124472 A JP H10124472A
Authority
JP
Japan
Prior art keywords
node
column
row
packet
match
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27827697A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10124472A5 (enExample
Inventor
D Hoonangu Brian
ブリアン・ディー・ホーナング
D Marietta Brian
ブリアン・ディー・マリエッタ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JPH10124472A publication Critical patent/JPH10124472A/ja
Publication of JPH10124472A5 publication Critical patent/JPH10124472A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/803—Three-dimensional arrays or hypercubes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/22—Alternate routing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/28—Routing or path finding of packets in data switching networks using route fault recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/02—Networking aspects
    • G09G2370/025—LAN communication management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computing Systems (AREA)
  • Human Computer Interaction (AREA)
  • Small-Scale Networks (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Hardware Redundancy (AREA)
JP27827697A 1996-09-27 1997-09-25 多ノードｓｃｉコンピュータシステムの経路指定方法 Pending JPH10124472A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/720,331 US5898827A (en) 1996-09-27 1996-09-27 Routing methods for a multinode SCI computer system
US720,331 1996-09-27

Publications (2)

Publication Number Publication Date
JPH10124472A true JPH10124472A (ja) 1998-05-15
JPH10124472A5 JPH10124472A5 (enExample) 2005-03-17

Family

ID=24893601

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27827697A Pending JPH10124472A (ja) 1996-09-27 1997-09-25 多ノードｓｃｉコンピュータシステムの経路指定方法

Country Status (2)

Country Link
US (1) US5898827A (enExample)
JP (1) JPH10124472A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010218364A (ja) * 2009-03-18 2010-09-30 Fujitsu Ltd 情報処理システム、通信制御装置および方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6535990B1 (en) * 2000-01-10 2003-03-18 Sun Microsystems, Inc. Method and apparatus for providing fault-tolerant addresses for nodes in a clustered system
US7047196B2 (en) 2000-06-08 2006-05-16 Agiletv Corporation System and method of voice recognition near a wireline node of a network supporting cable television and/or video delivery
TW582015B (en) * 2000-06-30 2004-04-01 Nichia Corp Display unit communication system, communication method, display unit, communication circuit and terminal adapter
US20020040425A1 (en) * 2000-10-04 2002-04-04 David Chaiken Multi-dimensional integrated circuit connection network using LDT
US7050398B1 (en) 2000-12-26 2006-05-23 Cisco Technology, Inc. Scalable multidimensional ring networks
US8095370B2 (en) 2001-02-16 2012-01-10 Agiletv Corporation Dual compression voice recordation non-repudiation system
US7447872B2 (en) 2002-05-30 2008-11-04 Cisco Technology, Inc. Inter-chip processor control plane communication
US6928589B1 (en) * 2004-01-23 2005-08-09 Hewlett-Packard Development Company, L.P. Node management in high-availability cluster
EP1885086B1 (en) * 2006-08-01 2011-01-26 Alcatel Lucent Method and network node for monitoring traffic in a private VLAN
US8364922B2 (en) * 2009-12-21 2013-01-29 International Business Machines Corporation Aggregate symmetric multiprocessor system
WO2011076599A1 (en) * 2009-12-21 2011-06-30 International Business Machines Corporation Aggregate symmetric multiprocessor system
US11520640B2 (en) * 2020-01-30 2022-12-06 Alibaba Group Holding Limited Efficient and more advanced implementation of ring-AllReduce algorithm for distributed parallel deep learning

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2644718B2 (ja) * 1983-12-28 1997-08-25 株式会社日立製作所 コンピュータシステム
US4797882A (en) * 1985-10-02 1989-01-10 American Telephone And Telegraph Company, At&T Bell Laboratories Mesh-based switching network
JPH03500104A (ja) * 1988-06-20 1991-01-10 アメリカ合衆国 相互接続回路網
US5471623A (en) * 1991-02-26 1995-11-28 Napolitano, Jr.; Leonard M. Lambda network having 2m-1 nodes in each of m stages with each node coupled to four other nodes for bidirectional routing of data packets between nodes
US5515510A (en) * 1994-01-14 1996-05-07 Consilium Overseas Limited Communications internetwork system connecting a client node array to a resource array
US5613073A (en) * 1994-07-25 1997-03-18 International Business Machines Corporation Apparatus and method for a buffer reservation system
US5606551A (en) * 1994-12-21 1997-02-25 Lucent Technologies Inc. Bidirectional mesh network

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010218364A (ja) * 2009-03-18 2010-09-30 Fujitsu Ltd 情報処理システム、通信制御装置および方法

Also Published As

Publication number Publication date
US5898827A (en) 1999-04-27

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