JPH10116931A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JPH10116931A
JPH10116931A JP28612996A JP28612996A JPH10116931A JP H10116931 A JPH10116931 A JP H10116931A JP 28612996 A JP28612996 A JP 28612996A JP 28612996 A JP28612996 A JP 28612996A JP H10116931 A JPH10116931 A JP H10116931A
Authority
JP
Japan
Prior art keywords
flat plate
semiconductor chip
chip
semiconductor package
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28612996A
Other languages
Japanese (ja)
Inventor
Osamu Nakayama
修 中山
Koji Ishikawa
浩嗣 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NHK Spring Co Ltd
Original Assignee
NHK Spring Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NHK Spring Co Ltd filed Critical NHK Spring Co Ltd
Priority to JP28612996A priority Critical patent/JPH10116931A/en
Publication of JPH10116931A publication Critical patent/JPH10116931A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4918—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package which can be made high in its heat radiation, assembling reliability, strength and durability, can avoid generation of an unnecessary resistance and can facilitate easy mounting to a printed circuit board. SOLUTION: A wiring substrate is fixedly mounted to a metallic plate 2 having a semiconductor chip 3 mounted thereon, electrodes provided on a rear side of the chip 3 are exposed from the rear side of the plate 2, and connected by bonding wires 5 and 6 to pads of the wiring substrate. Thereby, the chip 3 generating heat can be mounted directly to the plate 2 so that efficient heat radiation can be realized toward its printed circuit board side with a large area. Accordingly, a heat radiating efficiency can be improved, the plate 2 can function as a reinforcing material, deformation and destruction can be avoided, and coplanarity can be improved. Thus enabling stable mounting to the printed circuit board. Further, when the rear side of the substrate is connected also by bonding wires, its assembling reliability can be improved, thus eliminating generation of any unnecessary resistance.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体チップを実
装するための半導体パッケージに関し、特にパワーデバ
イスなどの表面及び裏面に電極を有する半導体チップを
実装するのに適した半導体パッケージに関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package for mounting a semiconductor chip, and more particularly to a semiconductor package suitable for mounting a semiconductor chip having electrodes on the front and back surfaces of a power device or the like.

【０００２】[0002]

【従来の技術】従来、例えばコンピュータのマザーボー
ド等のプリント基板に搭載するための半導体チップのパ
ッケージとしてはプラスチックボールグリッドアレイな
どに代表される樹脂ベースのものやセラミックピングリ
ッドアレイなどに代表されるセラミックベースのものが
主流であった。2. Description of the Related Art Conventionally, as a package of a semiconductor chip to be mounted on a printed circuit board such as a motherboard of a computer, for example, a resin-based package represented by a plastic ball grid array or a ceramic represented by a ceramic pin grid array has been used. The base one was mainstream.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、樹脂ベ
ースのものは樹脂自体が熱伝導性に乏しいと云う問題が
あった。例えば、搭載するチップの底面に金属を埋め込
んだ通孔、所謂サーマルビアを形成し、このサーマルビ
アを介してチップの熱を下面側に逃がす構造も提案され
ているが、実際にはその接触面積が小さいことから良好
な放熱性は期待できない。また、半導体パッケージは通
常チップを搭載した側を樹脂で封止しているが、樹脂硬
化時の収縮に伴い樹脂ベースに反りが発生し、はんだバ
ンプの高さが不揃いになり、プリント基板に実装する
際、接触不良が発生することが懸念される。また、セラ
ミックベースのものは、樹脂ベースのものよりは熱伝導
性は良いものの、セラミックは高価であり、また例えば
高出力半導体チップ等のパワーデバイスを搭載する場合
にはその熱伝達性が充分ではない。例えば配線パターン
や電極なども放熱経路として利用することも考えられる
が、放熱経路が長くなり、かつパッケージとプリント基
板との接触が端子部分のみであるため接触面積が小さい
ことから良好な放熱性は期待できない。また、上記同様
チップを搭載した側の樹脂封止の際の樹脂硬化時の収縮
に伴いセラミックベースに熱応力が生じ、更にセラミッ
クと熱膨張率が著しく異なるプリント基板の場合にはプ
リント基板へのはんだリフロー時にも熱応力が生じ、場
合によってはセラミックベースが破損することも考えら
れる。However, the resin-based resin has a problem that the resin itself has poor thermal conductivity. For example, there has been proposed a structure in which a through hole in which metal is embedded, that is, a so-called thermal via, is formed on the bottom surface of a mounted chip, and heat of the chip is released to the lower surface side through the thermal via. However, good heat dissipation cannot be expected because of the small size. In addition, although the semiconductor package is usually sealed with resin on the side where the chip is mounted, the resin base warps due to shrinkage during curing of the resin, the height of the solder bumps becomes uneven, and it is mounted on the printed circuit board When doing so, there is a concern that poor contact may occur. In addition, although ceramic-based ones have better thermal conductivity than resin-based ones, ceramics are expensive.For example, when a power device such as a high-output semiconductor chip is mounted, its heat transferability is not sufficient. Absent. For example, it is conceivable to use wiring patterns and electrodes as heat dissipation paths.However, good heat dissipation is not possible because the heat dissipation path is long and the contact area between the package and the printed circuit board is only the terminal area and the contact area is small. Can't expect. In addition, similarly to the above, thermal stress is generated in the ceramic base due to shrinkage at the time of resin curing at the time of resin sealing on the chip mounting side, and furthermore, in the case of a printed circuit board having a significantly different coefficient of thermal expansion from ceramic, it is difficult to apply to the printed circuit board. Thermal stress is also generated during solder reflow, and in some cases, the ceramic base may be damaged.

【０００４】そこで、樹脂配線基板と、金属ベースとを
組み合わせ、チップ本体を金属ベースに搭載すると共に
この金属ベースに支持された樹脂配線基板にボンディン
グワイヤで配線することが考えられる。Therefore, it is conceivable to combine a resin wiring board and a metal base, mount the chip body on the metal base, and wire the resin wiring board supported by the metal base with bonding wires.

【０００５】そして一般にパワーデバイスの場合には、
チップの表裏に電極が設けられていることが多い。その
場合、例えば半導体チップの裏面側の電極を金属ベース
上に形成された配線パターンにはんだ付けまたは導電性
接着剤により接着してチップの固定と同時に裏面側の配
線を行うようになる。はんだ付けの場合、上記したよう
に、完成した半導体パッケージもマザーボード等のプリ
ント基板にリフローによりはんだ付けされることから、
加熱炉内で半導体チップと金属ベースとの間のはんだも
溶融して半導体チップが不安定になり組み付け信頼性が
低下する心配がある。このとき、高融点はんだを用いる
ことも考えられるが、樹脂配線基板が高融点はんだの溶
融温度に耐えることができないことから現実的ではな
い。また、導電性接着剤により接着する場合、導電性接
着剤はこのような高出力な回路に用いるには抵抗値が高
いことから回路構成上好ましくない。[0005] In general, in the case of a power device,
In many cases, electrodes are provided on the front and back of the chip. In this case, for example, an electrode on the back side of the semiconductor chip is soldered or adhered to the wiring pattern formed on the metal base with a conductive adhesive to fix the chip and perform wiring on the back side at the same time. In the case of soldering, as described above, the completed semiconductor package is also soldered to a printed circuit board such as a motherboard by reflow,
There is a concern that the solder between the semiconductor chip and the metal base is also melted in the heating furnace, so that the semiconductor chip becomes unstable and the assembling reliability is reduced. At this time, a high melting point solder may be used, but it is not realistic because the resin wiring board cannot withstand the melting temperature of the high melting point solder. In the case of bonding with a conductive adhesive, the conductive adhesive is not preferable in terms of circuit configuration because it has a high resistance value for use in such a high-output circuit.

【０００６】本発明は上記したような従来技術の問題点
に鑑みなされたものであり、その主な目的は、放熱性、
組み付け信頼性、強度及び耐久性が高く、不必要な抵抗
が生じることがなく、しかもプリント基板への組み付け
も容易な半導体パッケージを安価に提供することにあ
る。The present invention has been made in view of the above-mentioned problems of the prior art, and its main objects are to dissipate heat,
An object of the present invention is to provide an inexpensive semiconductor package which has high assembling reliability, strength and durability, does not generate unnecessary resistance, and is easy to assemble on a printed circuit board.

【０００７】[0007]

【課題を解決するための手段】上記した目的は本発明に
よれば、表面及び裏面に電極を有する１つまたは２つ以
上の半導体チップを実装するための半導体パッケージで
あって、表面に絶縁材を介して前記半導体チップを搭載
する金属製の平板材と、前記平板材に固着され、該平板
材により補強される配線基板とを有し、前記平板材の裏
面側から前記半導体チップの裏面側電極が露出してお
り、かつ該半導体チップの各電極が前記配線基板のパッ
ドにボンディングワイヤにより接続されていることを特
徴とする半導体パッケージを提供することにより達成さ
れる。SUMMARY OF THE INVENTION According to the present invention, there is provided a semiconductor package for mounting one or more semiconductor chips having electrodes on the front surface and the back surface. A metal flat plate on which the semiconductor chip is mounted, and a wiring board fixed to the flat plate and reinforced by the flat plate, and a back side of the semiconductor chip from a back side of the flat plate This is achieved by providing a semiconductor package in which electrodes are exposed, and each electrode of the semiconductor chip is connected to a pad of the wiring board by a bonding wire.

【０００８】[0008]

【発明の実施の形態】以下に、本発明の好適な実施形態
について添付の図面を参照して詳しく説明する。図１
は、本発明が適用されたボールグリッドアレイ（以下、
ＢＧＡと記す）の構造を示す平面図であり、図２はその
ＩＩ−ＩＩ線について拡大して見た要部断面図、図３は
図１の底面図である。このＢＧＡは、ロの字状をなし、
かつ樹脂からなる両面配線基板１と、この両面配線基板
１の矩形の開口１ａの中央部に掛け渡されるように、そ
の両端で該配線基板１に樹脂フィルムまたは接着剤によ
って接着（固着）され、かつ表面の要部に絶縁層２ａが
設けられたアルミニウム製の長方形平板材２と、この平
板材２の絶縁層２ａ上に熱伝導性の高い導電性シリコー
ン樹脂等の接着剤４をもってダイボンディングにより接
着された複数の半導体チップ３とを有している。また、
必要に応じて配線基板１上にはチップ部品が搭載される
ようになっている（図示せず）。Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG.
Is a ball grid array to which the present invention is applied.
2 is a plan view showing a structure of the BGA), FIG. 2 is a cross-sectional view of an essential part of the structure taken along line II-II, and FIG. 3 is a bottom view of FIG. This BGA has a square shape,
A double-sided wiring board 1 made of resin, and both ends of the double-sided wiring board 1 are bonded (fixed) to the wiring board 1 with a resin film or an adhesive so as to be bridged over the center of the rectangular opening 1a. In addition, an aluminum rectangular flat plate 2 having an insulating layer 2a provided on a main portion of the surface, and an adhesive 4 such as a conductive silicone resin having high thermal conductivity on the insulating layer 2a of the flat plate 2 by die bonding. And a plurality of semiconductor chips 3 bonded thereto. Also,
Chip components are mounted on the wiring board 1 as necessary (not shown).

【０００９】ここで、各半導体チップ３は例えばパワー
ＭＯＳＦＥＴなどからなり、その表面の２カ所（ゲー
ト、ソース）と裏面（ドレイン）に電極３ａ、３ｂが設
けられている。そして、各半導体チップ３はその裏面側
の電極３ｂが開口１ａにて露出するように平板材２に接
着されている。Here, each semiconductor chip 3 is composed of, for example, a power MOSFET or the like, and electrodes 3a and 3b are provided at two places (gate, source) and a back face (drain) on the surface. Each semiconductor chip 3 is bonded to the flat plate 2 so that the electrode 3b on the back surface is exposed at the opening 1a.

【００１０】各半導体チップ３の表面側電極３ａと配線
基板１の表面１ｂ側配線との間はボンディングワイヤ５
によって電気的接合がなされている。また、半導体チッ
プ３裏面側電極３ｂと配線基板１の裏面１ｃ側配線との
間もボンディングワイヤ６によって電気的接合がなされ
ている。そして、これら配線基板１及び半導体チップ
３、ボンディングワイヤ５等の上部は、その保護のため
にトランスファモールド成形若しくはポッティングによ
り封止樹脂により封止されることとなる。A bonding wire 5 is provided between the surface side electrode 3a of each semiconductor chip 3 and the surface 1b side wiring of the wiring board 1.
Electrical connection is made. Electrical connection is also made between the back surface side electrode 3b of the semiconductor chip 3 and the back side 1c side wiring of the wiring board 1 by the bonding wire 6. Then, the upper portions of the wiring substrate 1, the semiconductor chip 3, the bonding wires 5, and the like are sealed with a sealing resin by transfer molding or potting for protection.

【００１１】尚、両面配線基板１には、必要に応じて多
数のスルーホール１ｄが開設され、各スルーホール１ｄ
は両面配線基板１の裏面１ｃ側にてランド７及びはんだ
ボール８に接続されている。The double-sided wiring board 1 is provided with a large number of through holes 1d as necessary.
Are connected to the lands 7 and the solder balls 8 on the back surface 1c side of the double-sided wiring board 1.

【００１２】実際に図示されないプリント配線基板（例
えばマザーボード）に上記半導体パッケージを実装する
には、プリント配線基板のはんだボールとの接合部及び
平板材接合部にクリームはんだを印刷し、平板材とプリ
ント配線基板及びはんだボールとプリント配線基板を同
時に一括してリフロー加熱によってはんだ付けすれば良
い。これにより半導体パッケージとプリント配線基板の
電気的接続はこのはんだボールによって行われる。半導
体チップ及びチップ部品からの熱は平板材１からはんだ
を介してプリント配線基板側に逃がされることとなる。In order to actually mount the semiconductor package on a printed wiring board (eg, a motherboard) (not shown), cream solder is printed on a joint between the printed wiring board and a solder ball and on a flat material joint. What is necessary is just to solder the wiring board, the solder balls and the printed wiring board at the same time by reflow heating. Thus, the electrical connection between the semiconductor package and the printed wiring board is made by the solder balls. Heat from the semiconductor chip and the chip components is released from the flat plate material 1 to the printed wiring board side via solder.

【００１３】尚、本実施形態では平板材２をアルミニウ
ムとしたが、平板材に固着する基板の熱膨張率、実装す
るプリント配線基板の熱膨張率に応じて選択される金属
または合金を用いて良い。例えば平板材に固着する配線
基板をセラミックとした場合には熱膨張率の低いＭｏ、
ＣｕＷを用いても良い。また、本実施形態では平板材２
をもプリント基板にクリームはんだをもってはんだ付け
したが、両者が密着すれば必ずしもはんだ付けを必要と
しない。更に、本実施形態では平板材に固着する配線基
盤をロ字状としたが、Ｉ字状、Ｌ字状等としても良く、
平板材の互いに対向する２辺に２つのＩ字状基板を固着
しても良い。Although the flat plate 2 is made of aluminum in the present embodiment, a metal or an alloy selected according to the coefficient of thermal expansion of the substrate fixed to the plate and the printed circuit board to be mounted is used. good. For example, when the wiring substrate fixed to the flat plate is made of ceramic, Mo having a low coefficient of thermal expansion,
CuW may be used. In the present embodiment, the flat plate 2
Was also soldered to the printed circuit board with cream solder, but soldering is not necessarily required if both are in close contact. Further, in the present embodiment, the wiring board fixed to the flat plate material has a square shape, but may have an I shape, an L shape, or the like.
Two I-shaped substrates may be fixed to two opposing sides of a flat plate.

【００１４】図４、図５は、本発明の応用例を示す図３
と同様な図である。図４では平板材１２が図３のものよ
りもやや幅広になっており、かつ開口１２ａが開設さ
れ、その開口１２ａから半導体チップ３の裏面側電極３
ｂが露出している。この構造では上記した構造よりも半
導体チップ３の接着面積が増え、その保持が確実になっ
ている。また、図５に示す構造では平板材２２が図３の
ものよりもやや幅広になっており、かつ切り欠き２２ａ
が穿設され、その切り欠き２２ａから半導体チップ３の
裏面側電極３ｂが露出している。この構造に於いても上
記した構造より半導体チップ３の接着面積が増え、その
保持が確実になっている。FIGS. 4 and 5 show an application example of the present invention.
FIG. 4, the flat plate member 12 is slightly wider than that of FIG. 3, and an opening 12a is opened.
b is exposed. In this structure, the bonding area of the semiconductor chip 3 is increased as compared with the above-mentioned structure, and the holding thereof is ensured. Further, in the structure shown in FIG. 5, the flat plate member 22 is slightly wider than that of FIG.
The back surface side electrode 3b of the semiconductor chip 3 is exposed from the notch 22a. Also in this structure, the bonding area of the semiconductor chip 3 is increased as compared with the above structure, and the holding thereof is ensured.

【００１５】[0015]

【発明の効果】上記した説明により明らかなように、本
発明による半導体パッケージによれば、半導体チップを
搭載した金属製の平板材に配線基板を固着し、平板材の
裏面側から半導体チップの裏面側電極を露出させ、その
各電極を配線基板のパッドにボンディングワイヤにより
接続することにより、発熱する半導体チップを直接平板
材に装着し、広い面積で効率良くプリント基板側へ放熱
可能となることから放熱効率が向上すると共に平板材が
補強材として機能し、変形、破壊を防止でき、コプラナ
リティ（平面度）が向上して安定したプリント基板への
実装が可能となる。また、裏面側をもボンディングワイ
ヤにより接続させることで、組み付け信頼性が向上し、
不必要な抵抗も生じることがない。As is apparent from the above description, according to the semiconductor package of the present invention, the wiring substrate is fixed to the metal flat plate on which the semiconductor chip is mounted, and the back surface of the semiconductor chip is mounted from the back side of the flat plate member. By exposing the side electrodes and connecting each electrode to the pad of the wiring board with a bonding wire, the semiconductor chip that generates heat can be directly mounted on a flat plate material, and it is possible to efficiently radiate heat to the printed board side over a wide area. The heat dissipation efficiency is improved, and the flat plate material functions as a reinforcing material, so that deformation and destruction can be prevented, coplanarity (flatness) is improved, and stable mounting on a printed circuit board becomes possible. In addition, by connecting the back side with bonding wires, assembling reliability is improved,
No unnecessary resistance occurs.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明が適用されたボールグリッドアレイの構
造を示す平面図。FIG. 1 is a plan view showing the structure of a ball grid array to which the present invention is applied.

【図２】図１のＩＩ−ＩＩ線について拡大して見た要部
断面図。FIG. 2 is an enlarged cross-sectional view of an essential part taken along line II-II of FIG. 1;

【図３】本発明が適用されたボールグリッドアレイの構
造を示す背面図。FIG. 3 is a rear view showing the structure of a ball grid array to which the present invention is applied.

【図４】本発明の応用例を示すボールグリッドアレイの
図３と同様な背面図。FIG. 4 is a rear view similar to FIG. 3 of a ball grid array showing an application example of the present invention.

【図５】本発明の応用例を示すボールグリッドアレイの
図３と同様な背面図。FIG. 5 is a rear view similar to FIG. 3 of a ball grid array showing an application example of the present invention.

【符号の説明】[Explanation of symbols]

１ 両面配線基板 １ａ 開口 １ｂ 表面 １ｃ 裏面 １ｄ スルーホール ２ 平板材 ２ａ 絶縁層 ３ 半導体チップ ３ａ、３ｂ 電極 ４ 接着剤 ５、６ ボンディングワイヤ ７ ランド ８ ボール １２ 平板材 １２ａ 開口 ２２ 平板材 ２２ａ 切り欠き DESCRIPTION OF SYMBOLS 1 Double-sided wiring board 1a Opening 1b Front surface 1c Back surface 1d Through hole 2 Flat plate 2a Insulating layer 3 Semiconductor chip 3a, 3b Electrode 4 Adhesive 5, 6 Bonding wire 7 Land 8 Ball 12 Flat plate 12a Opening 22 Flat plate 22a Notch

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 表面及び裏面に電極を有する１つまた
は２つ以上の半導体チップを実装するための半導体パッ
ケージであって、 表面に絶縁材を介して前記半導体チップを搭載する金属
製の平板材と、 前記平板材に固着され、該平板材により補強される配線
基板とを有し、 前記平板材の裏面側から前記半導体チップの裏面側電極
が露出しており、かつ該半導体チップの各電極が前記配
線基板のパッドにボンディングワイヤにより接続されて
いることを特徴とする半導体パッケージ。1. A semiconductor package for mounting one or two or more semiconductor chips having electrodes on the front and rear surfaces, and a metal flat plate on which the semiconductor chip is mounted via an insulating material on the front surface And a wiring board fixed to the flat plate material and reinforced by the flat plate material, wherein a back surface side electrode of the semiconductor chip is exposed from a back surface side of the flat plate material, and each electrode of the semiconductor chip is provided. Is connected to a pad of the wiring board by a bonding wire. 【請求項２】 前記配線基板が樹脂基板からなること
を特徴とする請求項１に記載の半導体パッケージ。2. The semiconductor package according to claim 1, wherein said wiring substrate is formed of a resin substrate. 【請求項３】 前記平板材に前記半導体チップの裏面
側電極を露出させるための開口または切り欠きが形成さ
れていることを特徴とする請求項１若しくは請求項２に
記載の半導体パッケージ。3. The semiconductor package according to claim 1, wherein an opening or a notch for exposing a back surface side electrode of the semiconductor chip is formed in the flat plate member. 【請求項４】 前記半導体チップと前記平板材との間
の絶縁材が、両者を接着するための接着剤からなること
を特徴とする請求項１乃至請求項３のいずれかに記載の
半導体パッケージ。4. The semiconductor package according to claim 1, wherein the insulating material between the semiconductor chip and the flat plate is made of an adhesive for bonding the two. . 【請求項５】 前記半導体チップがパワーデバイスか
らなることを特徴とする請求項４に記載の半導体パッケ
ージ。5. The semiconductor package according to claim 4, wherein said semiconductor chip comprises a power device.
JP28612996A 1996-10-08 1996-10-08 Semiconductor package Pending JPH10116931A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28612996A JPH10116931A (en) 1996-10-08 1996-10-08 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28612996A JPH10116931A (en) 1996-10-08 1996-10-08 Semiconductor package

Publications (1)

Publication Number Publication Date
JPH10116931A true JPH10116931A (en) 1998-05-06

Family

ID=17700312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28612996A Pending JPH10116931A (en) 1996-10-08 1996-10-08 Semiconductor package

Country Status (1)

Country Link
JP (1) JPH10116931A (en)

Similar Documents

Publication Publication Date Title
JP3053585B2 (en) Electronic package
JPH0325023B2 (en)
JPH10200021A (en) Bottom lead semiconductor package
JPH11312769A (en) Heat sink assembly for device heat dissipation
US6710438B2 (en) Enhanced chip scale package for wire bond dies
JPH1050877A (en) Semiconductor package
JPH11176993A (en) Semiconductor device, manufacture thereof, circuit board, and electronic apparatus
US6437430B2 (en) Semiconductor apparatus and frame used for fabricating the same
JP2002151634A (en) Board radiator
US6291893B1 (en) Power semiconductor device for “flip-chip” connections
JPH0922970A (en) Electronic component
JPH11220055A (en) Bga-type semiconductor device, and stiffener used for the device
JPH10116931A (en) Semiconductor package
JPH09321188A (en) Semiconductor device and its mounting method
JPH06252299A (en) Semiconductor device and board mounted therewith
JP3714808B2 (en) Semiconductor device
JP2564645Y2 (en) Hybrid integrated circuit device having heat-generating components
KR100352119B1 (en) Structure of ball grid array semiconductor package having heatsink and fabricating method thereof
JPH1041430A (en) Semiconductor package
JPH1126634A (en) Semiconductor device
JPH1167958A (en) High-radiation type package structure for flip chip
JP2936845B2 (en) Integrated circuit mounting structure
JP2904274B2 (en) LSI package mounting method
JPH07202387A (en) Ball-grid-array
JP2000138340A (en) Hybrid module