JPH10116814A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH10116814A
JPH10116814A JP26735396A JP26735396A JPH10116814A JP H10116814 A JPH10116814 A JP H10116814A JP 26735396 A JP26735396 A JP 26735396A JP 26735396 A JP26735396 A JP 26735396A JP H10116814 A JPH10116814 A JP H10116814A
Authority
JP
Japan
Prior art keywords
film
etched
contact hole
semiconductor device
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26735396A
Other languages
Japanese (ja)
Inventor
Yuichi Inaba
裕一 稲葉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP26735396A priority Critical patent/JPH10116814A/en
Publication of JPH10116814A publication Critical patent/JPH10116814A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device by which the number of operations for forming tapered contact holes is reduced. SOLUTION: An SiO2 film 2 which is a first film to be etched is formed on a semiconductor substrate 1. An Si3 N4 film 3 having a slower etching rate than the SiO2 film 2 is formed as a second film to be etched on the SiO2 film. The Si3 N4 film 3 and the SiO2 film 2 are subjected to an anisotropic etching through a resist film 6 to form a contact hole 8 having tapered parts 7 on its upper side.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置の製造
方法に関し、更に詳しく言えば、コンタクト孔上部のテ
ーパー部形成工程における工程数の削減を図る技術に関
するものである。
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a technique for reducing the number of steps in a step of forming a tapered portion above a contact hole.

【0002】[0002]

【従来の技術】以下で、従来例に係わる半導体装置の製
造方法、特にコンタクト孔の形成工程について図4乃至
図8を参照しながら説明する。先ず、図4に示すように
半導体基板51上に形成された被エッチング膜としての
SiO2 膜52上に図5に示すように開口部53を有す
るレジスト膜54を形成し、該レジスト膜54を介して
コンタクト孔を形成する領域のSiO2 膜52を例えば
RIE(Reactive Ion Etching:反応性エッチング)等
で異方性エッチングをし、図6に示すように基板51表
面にコンタクトするコンタクト孔55を形成していた。
2. Description of the Related Art A method of manufacturing a semiconductor device according to a conventional example, in particular, a process of forming a contact hole will be described below with reference to FIGS. First, a resist film 54 having an opening 53 as shown in FIG. 5 is formed on an SiO2 film 52 as a film to be etched formed on a semiconductor substrate 51 as shown in FIG. The SiO2 film 52 in the region where the contact hole is to be formed is anisotropically etched by, for example, RIE (Reactive Ion Etching: reactive etching) to form a contact hole 55 for contacting the surface of the substrate 51 as shown in FIG. I was

【0003】しかし、被エッチング膜の膜厚が例えば1
0000Å以上と厚くなり、しかもコンタクト孔径が例
えば0.5μm以下と小さくなるとステップカバレッジ
の劣化という問題が発生した。そこで、従来はコンタク
ト孔の上部にテーパー部を形成するため、等方性エッチ
ングを行った後に、異方性エッチングを行うことでコン
タクト孔を形成するようにした技術が行われている。即
ち、図7に示すように例えばフッ酸(HF)系のエッチ
ング液を用いて前記SiO2 膜52を選択的に等方性エ
ッチングして、凹部56を形成する。
However, the thickness of the film to be etched is, for example, 1
If the contact hole diameter becomes as large as 0000 ° or more and the contact hole diameter becomes as small as, for example, 0.5 μm or less, there arises a problem that the step coverage is deteriorated. Therefore, conventionally, in order to form a tapered portion above a contact hole, a technique of forming a contact hole by performing isotropic etching and then performing anisotropic etching is performed. That is, as shown in FIG. 7, the SiO2 film 52 is selectively and isotropically etched using, for example, a hydrofluoric acid (HF) -based etchant to form the concave portion 56.

【0004】次に、図8に示すようにRIEで前記凹部
56下のSiO2 膜52を異方性エッチングをし、基板
51表面に上部にテーパー部57が形成されたコンタク
ト孔58を形成することで、ステップカバレッジの劣化
という問題を解消していた。
[0004] Next, as shown in FIG. 8, the SiO 2 film 52 under the concave portion 56 is anisotropically etched by RIE to form a contact hole 58 having a tapered portion 57 formed on the upper surface of the substrate 51. This solves the problem of step coverage degradation.

【0005】[0005]

【発明が解決しようとする課題】しかし、従来のテーパ
ー部を有するコンタクト孔の形成工程では、前述したよ
うに等方性エッチングを行った後に、異方性エッチング
を行うことで、コンタクト孔を形成していたため、工程
数が増大していた。また、等方性エッチングによるテー
パー部の形成ができないような微細ルールのデバイスに
関しては、ステップカバレッジが劣化し、ステップカバ
レッジが十分に確保できないという問題が生じることに
なる。
However, in the conventional process of forming a contact hole having a tapered portion, the contact hole is formed by performing anisotropic etching after performing isotropic etching as described above. Therefore, the number of steps was increased. Further, with respect to a device having a fine rule in which a tapered portion cannot be formed by isotropic etching, step coverage deteriorates, and a problem arises in that sufficient step coverage cannot be secured.

【0006】従って、本発明ではテーパー部を有するコ
ンタクト孔の形成工程数の削減を図った半導体装置の製
造方法を提供することを目的とする。
Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device in which the number of steps for forming a contact hole having a tapered portion is reduced.

【0007】[0007]

【課題を解決するための手段】そこで、本発明は半導体
基板上に第1の被エッチング膜としてのSiO2 膜上に
当該SiO2 膜よりエッチングレートの遅いSi3N4膜
を第2の被エッチング膜として形成した後に、レジスト
膜を介して前記Si3N4膜及びSiO2 膜を異方性エッ
チングすることで、コンタクト孔の上部にテーパー部を
有するコンタクト孔を形成するものである。
In the present invention, an Si3N4 film having a lower etching rate than the SiO2 film is formed as a second film on a SiO2 film as a first film to be etched on a semiconductor substrate. Thereafter, the Si3N4 film and the SiO2 film are anisotropically etched through a resist film to form a contact hole having a tapered portion above the contact hole.

【0008】[0008]

【発明の実施の形態】以下、本発明の半導体装置の製造
方法の一実施の形態について説明する。先ず、図1に示
すように半導体基板1上に第1の被エッチング膜として
のSiO2 膜2をおよそ12000Åの厚さで形成した
後に、前記SiO2 膜2上に第2の被エッチング膜とし
て該SiO2 膜2よりもエッチングレートの遅い、例え
ばシリコン窒化膜(以下、Si3N4膜という。)3をお
よそ1000Å乃至2000Åの厚さで形成して成る被
エッチング膜4を形成する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a method for manufacturing a semiconductor device according to the present invention will be described below. First, as shown in FIG. 1, an SiO2 film 2 as a first film to be etched is formed on a semiconductor substrate 1 to a thickness of about 12000 DEG, and then a second film to be etched is formed on the SiO2 film 2 as a second film to be etched. An etching target film 4 is formed by forming, for example, a silicon nitride film (hereinafter, referred to as a Si3N4 film) 3 having a lower etching rate than the film 2 to a thickness of about 1000 to 2000 degrees.

【0009】次に、図2に示すように開口部5を有する
レジスト膜6を形成し、該レジスト膜6をマスクにし
て、エッチング条件として例えばパワー700W、圧力
250mTorr、流量15sccmのCHF3 、流量
10sccmのCF4 及び流量300sccmのArを
用いてRIEにより前記被エッチング膜4を異方性エッ
チングすることで、SiO2 膜2との選択比の高い(エ
ッチングレートの遅い)Si3N4膜3では、エッチング
の進行に対してデポ物の供給が多く、テーパー形状を形
成することができ、従って、図3に示すように前記基板
1表層にその上部にテーパー部7を有するコンタクト孔
8が形成できる。
Next, as shown in FIG. 2, a resist film 6 having an opening 5 is formed, and using this resist film 6 as a mask, etching conditions are, for example, power 700 W, pressure 250 mTorr, CHF 3 at a flow rate of 15 sccm, flow rate of 10 sccm. By performing anisotropic etching of the film 4 to be etched by RIE using CF4 and Ar at a flow rate of 300 sccm, in the Si3N4 film 3 having a high selectivity to the SiO2 film 2 (slow etching rate), the etching progresses. On the other hand, a large amount of the deposit is supplied, and a tapered shape can be formed. Therefore, as shown in FIG. 3, a contact hole 8 having a tapered portion 7 on the upper surface thereof can be formed in the surface layer of the substrate 1.

【0010】本発明の実施の形態では、半導体基板1上
にSiO2 膜2から成る第1の被エッチング膜を形成
し、該SiO2 膜2上に当該SiO2 膜2よりエッチン
グレートの遅いSi3N4膜3から成る第2の被エッチン
グ膜をコンタクト孔8の上部に所望のテーパー部7が形
成されるに十分な膜厚で形成することで、一度の異方性
エッチング工程によりコンタクト孔8の上部にのみテー
パー部7を有するコンタクト孔8が形成できる。
In the embodiment of the present invention, a first film to be etched consisting of an SiO2 film 2 is formed on a semiconductor substrate 1, and an Si3N4 film 3 having a lower etching rate than the SiO2 film 2 is formed on the SiO2 film 2. By forming the second film to be etched to a thickness sufficient to form a desired tapered portion 7 above the contact hole 8, only the upper portion of the contact hole 8 is tapered by a single anisotropic etching step. A contact hole 8 having a portion 7 can be formed.

【0011】従って、従来のようにステップカバレッジ
の向上を図るために、コンタクト孔の上部にテーパ部を
形成するプロセスとして等方性エッチングを行った後
に、異方性エッチングを行うような2工程で行っていた
工程を1工程で行うことができ、工程の削減、リードタ
イムの短縮が図れる。また、等方性エッチングによるテ
ーパー部の形成が不可能なような微細ルールのデバイス
においても、本発明を適用することで、コンタクト孔の
上部にテーパー部を形成することができる。
Therefore, in order to improve the step coverage as in the prior art, the isotropic etching is performed as a process of forming a tapered portion above the contact hole, and then the anisotropic etching is performed in two steps. The steps that have been performed can be performed in one step, and the number of steps can be reduced and the lead time can be reduced. Further, even in a device having a fine rule in which a tapered portion cannot be formed by isotropic etching, a tapered portion can be formed above a contact hole by applying the present invention.

【0012】[0012]

【発明の効果】以上、本発明によれば一度の異方性エッ
チング工程によりコンタクト孔の上部にのみテーパー部
を有するコンタクト孔が形成できるため、工程数の削減
が図れ、リードタイムの短縮が図れる。また、等方性エ
ッチングによるテーパー部の形成が不可能なような微細
ルールのデバイスにおいても、本発明ではテーパー部の
形成が可能となり、ステップカバレッジの向上が図れ
る。
As described above, according to the present invention, a contact hole having a tapered portion only above the contact hole can be formed by a single anisotropic etching step, so that the number of steps can be reduced and the lead time can be shortened. . Further, even in a device having a fine rule in which a tapered portion cannot be formed by isotropic etching, the tapered portion can be formed in the present invention, so that step coverage can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施の形態の半導体装置の製造方法
を示す第1の断面図である。
FIG. 1 is a first sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;

【図2】本発明の一実施の形態の半導体装置の製造方法
を示す第2の断面図である。
FIG. 2 is a second cross-sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

【図3】本発明の一実施の形態の半導体装置の製造方法
を示す第3の断面図である。
FIG. 3 is a third sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

【図4】従来の半導体装置の製造方法を示す断面図であ
る。
FIG. 4 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

【図5】従来の半導体装置の製造方法を示す断面図であ
る。
FIG. 5 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

【図6】従来の半導体装置の製造方法を示す断面図であ
る。
FIG. 6 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

【図7】従来の半導体装置の製造方法を示す断面図であ
る。
FIG. 7 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

【図8】従来の半導体装置の製造方法を示す断面図であ
る。
FIG. 8 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に第1の被エッチング膜を
形成する工程と、 前記第1の被エッチング膜上に該被エッチング膜よりエ
ッチングレートの遅い第2の被エッチング膜を積層形成
する工程と、 レジスト膜を介して前記第1の被エッチング膜及び第2
の被エッチング膜を異方性エッチングする工程とを有す
ることを特徴とする半導体装置の製造方法。
A step of forming a first film to be etched on a semiconductor substrate; and a step of forming a second film to be etched having a lower etching rate than the film to be etched on the first film to be etched. And the first film to be etched and the second film via a resist film.
And anisotropically etching the film to be etched.
【請求項2】 前記第1の被エッチング膜及び第2の被
エッチング膜は、それぞれSiO2 膜及びSi3N4膜か
ら成ることを特徴とする半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein said first film to be etched and said second film to be etched are respectively composed of a SiO2 film and a Si3 N4 film.
JP26735396A 1996-10-08 1996-10-08 Manufacture of semiconductor device Pending JPH10116814A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26735396A JPH10116814A (en) 1996-10-08 1996-10-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26735396A JPH10116814A (en) 1996-10-08 1996-10-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH10116814A true JPH10116814A (en) 1998-05-06

Family

ID=17443646

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26735396A Pending JPH10116814A (en) 1996-10-08 1996-10-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH10116814A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6617201B2 (en) 2000-08-29 2003-09-09 Micron Technology, Inc. U-shape tape for BOC FBGA package to improve moldability

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6617201B2 (en) 2000-08-29 2003-09-09 Micron Technology, Inc. U-shape tape for BOC FBGA package to improve moldability

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