JPH1011489A - Automatic arrangement wiring method for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the timing verification error caused after wiring and also the back track of design without using any complicated wiring technique by placing the unit cell groups to be arranged adherent to each other based on a fixed rule or order. SOLUTION: In a logic circuit connection information analysis process P3 , the logic circuit connection information D2 including a set identifier is analyzed and the logical grouping information D3 for identifying which cell of a unit cell group including a set identifier belongs to which of groups and the logic circuit connection order information D4 for identifying the connection order of plural unit cells of every group are generated. In an automatic arrangement wiring design process P4 , plural unit cells of the same group are arranged adjacent to each other according to the connection order set in a circuit design mode based on those information D2 , D3 and D4 and also the arrangement wiring information D5 is generated for a semiconductor integrated circuit which secures connection among the unit cells.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic placement and routing method for automatically determining the arrangement of unit cells and the wiring between unit cells in an automatic placement and routing design process.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing a processing procedure and a data flow in a conventional automatic placement and routing method. A data flow is shown by a solid line, and a processing flow is shown by a broken line.

First, in a logic design process _P41 , when a function to be realized is determined, a plurality of unit cells, for example, shift registers 11 to 14 and a buffer 15 are used in FIG. after conducting the circuit design shown, the functions of interest in combination with this, such as the unit cell of will be able to achieve, determine the connection information of the unit cell of this such as a logic circuit connection information D _41, it produces.

[0004] Next, the automatic placement and routing design process P _42, based on the logic circuit connection information D _41, as placement and routing information D ₄₂ of the semiconductor integrated circuit connection information of the unit cell as shown in FIG. 5 (b) Generate.

[0005]

[SUMMARY OF THE INVENTION Incidentally, according to such conventional automatic placement and routing method for generating placement and routing information D ₄₂ in the arrangement of the plurality of unit cells of the shift registers 11 to 14 and buffer 15, Since the function and connection order of each unit cell are determined without considering at all, FIG.
As shown in FIG. 5A, a plurality of unit cells of the shift registers 11 to 14 and the buffer 15 to be arranged and wired according to a certain rule or order are automatically arranged and wired randomly as shown in FIG. Will be done. For this reason, the line length and the like between the unit cells are different, and the arrival time of the clock signal to each unit cell is different from the design value, so that an error occurs in the timing verification after the automatic placement and routing.

Therefore, there is a method of preventing the above-described error by adjusting the line length of the clock line using a complicated automatic placement and routing technique such as clock tree synthesis. However, there is a problem that the number increases.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem. Even if a complicated automatic placement and routing technique such as clock tree synthesis is not used, errors and design errors in timing verification after automatic placement and routing are achieved. To provide an automatic placement and routing method that can eliminate backtracking.

[0008]

SUMMARY OF THE INVENTION According to the present invention, a unit cell group to be arranged adjacently is not randomly arranged even if an automatic placement and routing tool is used, and adheres to a certain rule or order. Be placed.

Further, the invention according to claim 1 of the present invention includes a grouping information setting step of generating logic circuit connection information in which identifiers are set in a plurality of unit cells to be arranged adjacently at the time of placement and wiring. , Logic circuit grouping information for identifying which unit cell of the unit cell group to which the identifier is set belongs to which group, and logic circuit connection order information for identifying the connection order of a plurality of unit cells in each group Based on the logic circuit connection information, the logic circuit grouping information, and the logic circuit connection order information in which the identifiers are set, and the connection order at the time of circuit design of a plurality of unit cells of the same group. Automatic placement and routing design process for generating placement and routing information of semiconductor integrated circuits connecting adjacent unit cells and arranging adjacently according to Become ones, without using a complicated automatic placement and routing techniques, such as clock tree synthesis,
An error does not occur in the timing verification after the automatic placement and routing, and the return of the automatic placement and routing design process can be eliminated.

[0010] Further, the invention according to claim 2 of the present invention provides:
A logic circuit connection information analysis step, wherein first means for initially setting the value of the logic circuit grouping information and the value of the logic circuit connection order information, respectively, and detecting one of the unit cells in which the identifier is set. In addition, the unit cell whose input terminal is connected to the output terminal of the same type of unit cell is searched sequentially from the detected unit cell, and the output terminal of another type of unit cell is connected to the input terminal of the unit cell. A second unit that determines that the unit cell is the first unit cell in the same group when the unit cell detected is detected, and a unit cell of the same type is connected to an output terminal of the unit cell. A third means for sequentially adding the connection order information from the head unit cell every time the unit cell is detected, and another type of unit to the output terminal of the unit cell being searched. When detecting that a unit cell is connected, the same grouping information and the final connection order information in the same group are given to the other types of unit cells connected to the clock line of the first unit cell. When the addition of the connection order information to the plurality of unit cells in the same group by the fourth means and the second to fourth means ends, the value of the grouping information is rewritten, and the connection order information is initialized. When the assignment of the grouping information and the connection order information to the unit cell group to which the identifier is set is completed by repeating the fifth means and the second to fifth means, the grouping information and the connection order The sixth means for storing all the information in the memory. When the shift registers and the like are continuously arranged, explicit setting is performed. Without having it can be arranged automatically reliably adjacent.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a processing procedure and a data flow in an automatic placement and routing method according to an embodiment of the present invention. The flow of processing is shown by a broken line, and the flow of data is shown by a solid line.

[0013] First, the logical design process P _1, the function to be implemented is determined, the unit cell so that this function can be realized, for example, a shift register 1-4, as shown in FIG. 2 (a) using a buffer 5 after performing a circuit design, the function of interest is achieved by a combination of unit cells in which the like, and generates a logic circuit connection information D ₁ showing the placement and connection relationship of each unit cell.

Then, in the grouping information setting step P ₂ , predetermined identifiers are assigned to unit cells to be continuously arranged at the time of automatic arrangement and wiring, for example, shift registers 1 to 4 and a buffer 5 enclosed by broken lines in FIG. generating a logic circuit connection information D ₂ set.

[0015] Therefore, in the logic circuit connection information analyzing step P _3, analyzes the logical circuit connection information D ₂ which identifier has been set, any unit cell identifier set the unit cell group belong to any group a logic circuit grouping information D ₃ identifying whether the logical circuit connection order information D ₄ identifies the connection order of the plurality of unit cells in each group
And generate

Then, in the automatic placement and routing design process P ₄ ,
Based on the logic circuit connection information D ₂ , the logic circuit grouping information D _3, and the logic circuit connection order information D ₄ in which the identifiers are set, a plurality of unit cells of the same group, for example, the shift registers 1 to 4 and the buffer 5 are illustrated. as shown in 2 (b), while disposed adjacent according to the connection order of the circuit design, generates a placement and routing information D ₅ of the semiconductor integrated circuit for connecting the respective unit cells.

[0017] FIG. 3 is a logic circuit connection information analyzed in step P _3, the logic circuit group information D ₃ from the logic circuit connection information D ₂ which identifier has been set and a logic circuit connecting sequence information in the automatic placement and routing method of the present invention is a flowchart of when generating and D _4.

First, at the start of retrieval of a plurality of unit cells, the value “I” of the logic circuit grouping information D ₃ and the value “N” of the logic circuit connection order information D ₄ are each initialized to “0” [ Step 1 (hereinafter referred to as "S1")].

Then, the unit cell group to which the identifier is set is searched, and one unit cell (for example, flip-flop 3) is detected (S2). (S3), and it is determined whether or not the output terminal of the same type of unit cell is connected to the input terminal of the detected unit cell (for example, flip-flop 3) (S4).

Therefore, when it is detected that the same type of unit cell (eg, flip-flop 2) is connected to the input terminal of the unit cell being searched (eg, flip-flop 3), “the unit cell being searched is the first unit cell. It is determined that the unit cell is not a unit cell ”(S4), and the above-described search is performed for the next unit cell of the same type (eg, flip-flop 2) connected to the input terminal of the first detected unit cell (eg, flip-flop 3). (S2-4) is performed again.

Thereafter, each time it is determined that "the unit cell being searched is not the first unit cell" (S4), the above-described search (S2-4) is repeated, and the first unit cell in the same group is searched. Search for unit cells.

When it is detected that the output terminal of another type of unit cell (for example, buffer 5) is connected to the input terminal of the unit cell (for example, flip-flop 1) being searched, the "unit being searched for" The cell is the first unit cell in the same group "(S4).
It is determined whether or not the same type of unit cell is connected to the output terminal of the first unit cell (eg, flip-flop 1) being searched (S5).

When it is detected that the same type of unit cell (for example, flip-flop 2) is connected to the output terminal of the first unit cell (for example, flip-flop 1) (S5), the first unit cell (for example, flip-flop 2) is detected. The grouping information “0” and the connection order information “1” obtained by increasing the value of the connection order information by “1” are assigned to the flip-flop 1) (S6).

The above-described search is performed on a second unit cell (for example, flip-flop 2) of the same type connected to the output terminal of the first unit cell (for example, flip-flop 1), and the output terminal is connected to the output terminal. When it is detected that the same type of unit cell (for example, flip-flop 3) is connected (S5), the grouping information “0” is added to the second unit cell (for example, flip-flop 2).
The connection order information “2” obtained by further increasing the value of the connection order information by “1” is added (S6).

The above-described search (S5 and S6) is repeated for a plurality of unit cells connected after the third unit cell (for example, flip-flop 2).
Each time it is detected that the same type of unit cell is connected to the output terminal (S5), the grouping information “0” and the value of the connection order information are respectively set to “1” in the unit cell being searched. The connection order information “N” which has been increased by only “N” is added (S6).

When it is detected that another type of unit cell is connected to the output terminal of the unit cell being searched (for example, flip-flop 4) (S5), the head unit cell (for example, flip-flop 1) is detected. Grouping information “0” and connection order information obtained by further increasing the value of the connection order information by “1”, ie, the same group, in another type of unit cell (for example, the buffer 5) connected to the clock line of FIG. And the last connection order information “N” (“5” in the present embodiment) in the table (S7).

By performing such a search (S2 to S6) repeatedly and performing the operation of S7, a plurality of groups in the same group for realizing one related function such as a shift register and a buffer are realized. When the connection order information is given to the unit cell, the value of the grouping information is set to “1”.
And rewrite from “0” to “1”
The connection order information is returned from "N" to "0" (S8).

Thereafter, the unit cell group to which the identifier is set is searched again (S2), and one of the unit cells to which the grouping information and the connection order information have not been given yet is searched.
When one is detected, the above-described search (S2-7) is performed, and
After sequentially assigning grouping information and connection order information to a plurality of unit cells for implementing one related function,
The value of the grouping information is further increased by “1” to “1”
To “2” and change the connection order information to “N”.
To "0" (S8).

Thereafter, every time a search is made for a unit cell to which the grouping information and the connection order information have not been added in the unit cell group in which the identifier is set (S2), the above-described search (S2-8) is performed. Is repeatedly performed, the unit cell group in which the identifier is set is sorted into a plurality of groups according to functions and the like, and grouping information is given to each group, and the unit cells are connected to the plurality of grouped unit cells. Add order information.

When it is detected that the grouping information and the connection order information have been added to all the unit cells of the unit cell group in which the identifier is set (S2), it is determined that the search has been completed (S3). ), All the grouping information and the connection order information of the unit cell group to which the identifier obtained by the search is set are stored in the memory (S9).

When the automatic placement and routing is designed in the automatic placement and routing design process based on the grouping information and the connection order information obtained as described above, the unit cells having the identifiers are classified into a plurality of groups according to functions. After that, placement and routing information is generated in which a plurality of unit cells in the same group are placed adjacent to each other in the connection order.

For example, as shown in FIG. 2B, arrangement and wiring information for realizing a shift register having a circuit configuration as shown in FIG. 2A as a semiconductor integrated circuit includes, as shown in FIG. Are arranged side by side in the connection order, and a buffer connected to the clock line of the shift register is arranged adjacent to the plurality of unit cells.

That is, the arrangement and wiring of a plurality of unit cells can be realized in accordance with the flow of data from the least significant bit (LSB) to the most significant bit (MSB), and a buffer for supplying a clock is used for the data flow. Is arranged adjacent to the last unit cell, and the data flow and the clock supply direction are reversed, so that the semiconductor integrated circuit operates stably.

[0034]

As described above, according to the present invention,
Even when the automatic placement and routing tool is used, the unit cell groups to be placed adjacent to each other are not placed at random but are placed according to a certain rule or order.

As a result, no error occurs in the timing verification after the automatic placement and routing without using a complicated automatic placement and routing technique such as clock tree synthesis.
This has the effect of preventing regression of the automatic placement and routing design process.

Further, when the shift registers and the like are continuously arranged, there is an effect that they can be automatically and reliably arranged adjacent to each other without an explicit setting.

[Brief description of the drawings]

FIG. 1 is a diagram showing a processing procedure and a data flow in an automatic placement and routing method according to an embodiment of the present invention.

FIG. 2A is a diagram showing an example of a circuit to be automatically placed and routed, and FIG. 2B is a diagram showing an actual example of a circuit realized by the automatic placement and routing method of the present invention.

FIG. 3 shows a logic circuit connection information analysis step of generating logic circuit grouping information and logic circuit connection order information from logic circuit connection information in which an identifier is set in the automatic placement and routing method according to an embodiment of the present invention. It is a flowchart.

FIG. 4 is a diagram showing a processing procedure and a data flow in a conventional automatic placement and routing method.

5A is a diagram illustrating an example of a circuit to be automatically placed and routed, and FIG. 5B is a diagram illustrating an actual example of a circuit realized by a conventional automatic placement and routing method.

[Explanation of symbols]

P ₁ … Logical design process P ₂ … Grouping information setting process
P ₃ … Logic circuit connection information analysis process, P ₄ … Automatic placement and routing design process, D ₁ … Logic circuit connection information, D ₂ … Logic circuit connection information in which an identifier is set, D ₃ … Logic circuit grouping information, D ₄ ... logic connection order information, D ₅ ... placement and routing information.

Claims (2)

[Claims] 1. A method of generating placement and routing information based on logic circuit connection information of a semiconductor integrated circuit, comprising the steps of: setting identifiers for a plurality of unit cells to be placed adjacently during placement and routing; Generating grouping information setting step; logic circuit grouping information for identifying which unit cell of the unit cell group to which the identifier is set belongs to which group; and a plurality of the unit cells in each group A logic circuit connection information analyzing step of generating logic circuit connection order information for identifying the connection order of the logic circuit connection information, the logic circuit connection information in which the identifier is set, the logic circuit grouping information, and the logic circuit connection order information, A plurality of the unit cells of the same group are arranged adjacent to each other according to a connection order at the time of circuit design, and An automatic placement and routing design step for generating placement and routing information of a semiconductor integrated circuit to be connected. 2. The logic circuit connection information analysis step, wherein: first means for initially setting a value of the logic circuit grouping information and a value of the logic circuit connection order information, respectively, and a unit in which the identifier is set. After detecting one of the cell groups, the unit cells whose input terminals are connected to the output terminals of the unit cells of the same type are sequentially searched from the detected unit cells, and the input of the unit cells is performed. When detecting the unit cell in which the output terminal of another type of unit cell is connected to the terminal,
A second unit for determining that the unit cell is the first unit cell in the same group; and, whenever detecting that a unit cell of the same type is connected to an output terminal of the unit cell, A third means for sequentially providing connection order information from the unit cell of the unit cell, and detecting that another type of the unit cell is connected to the output terminal of the unit cell being searched, A fourth means for providing the same grouping information and final connection order information in the same group to other types of unit cells connected to a clock line; and the second to fourth means. When the application of the connection order information to a plurality of the unit cells in the same group is completed by rewriting the value of the grouping information, A fifth unit for initially setting the connection order information, and the second to fifth units are repeatedly performed to obtain the grouping information and the connection order information for the unit cell group in which the identifier is set. 6. The automatic placement and routing method for a semiconductor integrated circuit according to claim 1, further comprising: sixth means for storing all of the grouping information and the connection order information in a memory when the assignment is completed.