JPH10111852A - Bidirectional buffer control-system i/o port setting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bidirectional buffer control-system I/O port setting device capable of transmitting data stably and with high reliability without a trouble in a function operation. SOLUTION: The I/O port setting device is constituted by permitting a bidirectional buffer 2 and a holding circuit 3 to execute intervention at every LSI from #1-#4 and executing the connection of I/O-CONT (I/O port setting exclusive circuit) 1A. The bidirectional buffer 2 transfers data in a common data bus in accordance with I/O buffer change-over signal at every LSI from I/O-CONTA 1A and the holding circuit 3 holds anaddress in the common address bus in accordance with an address holding signal at every LSI from I/O CONT 1A. I/O CONT 1A transmits an operation indicating signal at every LSI, reads a reading setting source I/O port concerning LSI and, at the same time, executes writing in a writing setting object I/O port. But, a transfer destination address concerning LSI is previously set in the holding circuit corresponding to LSI to be a data transfer object before executing data transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is mainly applied to a digital transmission apparatus and the like, and is a bidirectional buffer control type I / O for performing interface conversion and data relay for a specific user to transfer data to another partner user. It relates to an O port setting device.

[0002]

2. Description of the Related Art Conventionally, an LSI used in a digital transmission apparatus performs most of data processing, and one apparatus is formed by a combination thereof. Such LS
Since I is designed to have versatility, it is necessary to make a fixed setting based on the specifications of each device when the power is turned on. During normal operation, data on an I / O port in an LSI may be transferred to another LSI to change the operation of each LSI.

The I / O controlling these LSI operations
An I / O port setting dedicated circuit (hereinafter referred to as I / O port
/ O-CONT) is known.

When data is transferred between LSIs, if there are many destination LSIs instead of one, the source data is temporarily stored in a table in the I / O-CONT, and then The setting data is individually written for each of the LSIs to be set as the transfer destination.

FIG. 5 shows a bidirectional buffer control type I / O constructed when data is transferred between such LSIs.
FIG. 2 is a functional block diagram illustrating a basic configuration of an O port setting device. 6A and 6B are views for explaining the operation of the I / O port setting device. FIG. 6A relates to a block diagram in one operation state, and FIG. 3) relates to a timing chart of a signal waveform in the state of FIG.

In this bidirectional buffer control type I / O port setting device, an I / O-CONT 1B is connected to four LSIs # 1 to # 4 via a bidirectional buffer 2.

Here, the I / O-CONT 1B has a normal operation table 1a and an initial start-up table 1b as tables, and the data between the LSIs # 1 to # 4 is controlled by a program that performs a periodic operation. The transfer is performed.

In this I / O port setting device, the I / O-
L from the CONT1B to the LSIs # 1 to # 4
In addition to transmitting the SI selection signals # 1 to # 4, the I / O buffer switching signal is transmitted and one bidirectional buffer 2 for one data on the common data bus relates to the data of the LSIs # 1 to # 4. Read / Write switching is performed. An external memory is used for data transfer between the LSIs # 1 to # 4.

For example, as shown in FIG. 6A, in a case where LSI # 1 is left as one operation state and Read is performed for LSI # 2, and Write1 and Write2 are performed for LSI # 3 and LSI # 4. , Common data bus, common data bus, LSI selection signals # 1 to # 4, I /
The signal waveforms relating to the O-buffer switching signal are shown in FIG.
The configuration is as shown in FIG.

Incidentally, other known techniques related to such data transfer and data control include, for example, a data transfer control device disclosed in Japanese Patent Application Laid-Open No. 62-6363 and Japanese Patent Application Laid-Open No. 2-222052. Direct memory access control device, Japanese Patent Laid-Open No. 5-120201
And a data processing device disclosed in Japanese Unexamined Patent Publication (Kokai) Publication.

[0011]

In the above-described data transfer in the bidirectional buffer control type I / O port setting device, if the source LSI data changes while data is being written to the target LSI, the source LSI In addition, there is a problem that the functional operation differs between the setting target LSIs, causing a trouble.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem. A technical problem of the present invention is to provide a bidirectional buffer capable of performing stable and highly reliable data transfer without causing trouble in functional operation. It is to provide a controllable I / O port setting device.

[0013]

According to the present invention, an I / O-C is provided for a plurality of LSIs by interposing a bidirectional buffer.
In a bidirectional buffer control type I / O port setting device connected to ONTs, a bidirectional buffer and a holding circuit are provided for each of a plurality of LSIs, and the bidirectional buffer is an I / O-CON
The data transfer on the common data bus is performed in response to the I / O buffer switching signal for each of the plurality of LSIs from T, and the holding circuit performs the common address in response to the address holding signal for each of the plurality of LSIs from the I / O-CONT. Holds the address on the bus,
As the I / O-CONT, a bidirectional buffer control type I / O port setting device that sends operation instruction signals including writing, reading, and stopping for each of a plurality of LSIs can be obtained.

According to the present invention, in the above-described I / O port setting device with bidirectional buffer control, the I / O-CON
For T, a bidirectional buffer control type I / O port setting device that reads a read setting source I / O port for a plurality of LSIs in accordance with an operation instruction signal and simultaneously writes to a write setting target I / O port is obtained.

Further, according to the present invention, in any of the above-described bidirectional buffer control type I / O port setting devices,
The O-CONT is a bidirectional buffer control type I / O that sets transfer destination addresses for a plurality of LSIs in a holding circuit corresponding to a data transfer target among the plurality of LSIs before executing data transfer. An O port setting device is obtained.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A bidirectional buffer control type I / O port setting device according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a functional block diagram showing the basic configuration of a bidirectional buffer control type I / O port setting device according to one embodiment of the present invention.

This I / O port setting device has four LSs
The I / O-CONT 1A is connected to each of the I # 1 to # 4 via the bidirectional buffer 2 and the holding circuit 3.

Of these, the bidirectional buffer 2 has an I / O-
Data transfer on the common data bus is performed according to an I / O buffer switching signal for each of LSIs # 1 to # 4 from CONT1A. The holding circuit 3 is an LSI from the I / O-CONT1A.
The address on the common address bus is held according to the address holding signal for each of # 1 to # 4. The I / O-CONT 1A sends an operation instruction signal for each LSI, and according to the operation instruction signal, a read setting source I / O for the LSIs # 1 to # 4.
At the same time as reading the port, writing is performed to the write setting target I / O port. However, I / O-CONT1A is
Before executing the data transfer, the transfer destination addresses for the LSIs # 1 to # 4 are set in advance in the holding circuits corresponding to the LSIs # 1 to # 4 corresponding to the data transfer targets.

The LSIs # 1 to # 4 store control and alarm information in an internal I / O port, and exchange the information through a common data bus. LSI # 1
To # 4 and the common data bus are connected by a bidirectional buffer 2. The bidirectional buffer 2 controls the I / O-CONT1A to transfer data transferred on the common data bus to the LSI.
Read / Write is performed for # 1 to # 4.

That is, in this I / O port setting device, holding circuits 3 for holding addresses are provided at input terminals of the LSIs # 1 to # 4 of the common address bus, respectively, and the LSIs # 1 to ## of the common data bus are provided. The I / O-CONT 1A controls switching of the bidirectional buffers 2 of the LSIs # 1 to # 4.
Is performed by a command (instruction) in the table data in the table.

FIG. 2 exemplifies a command form in the I / O-CONT 1A, and FIG. 3 exemplifies divided table data in the I / O-CONT 1A.

The command form is divided into a command part, an address part, and a data part. The command part is assigned a command and an LSI type, and the address part is assigned an I / O port address of the LSI selected by the LSI type. The data set is assigned data set to the I / O port.

Command types include Read, Write,
There are an N setting Read (N is 1 to the number of fan-outs of the bidirectional buffer 2) and an address setting, and these are respectively set to, for example, 00 ××× (b) and 01 ×× as shown in FIG.
×× (b), 10 # 1 # 2 # 3 # 4 (b), 11 ×××
× (b).

The LSI types are, for example, 00 (b) and 01, as shown in FIG.
(B), 10 (b), and 11 (b).

As shown in FIG. 3, the table data contains the table addresses 0, 1, and 2 in the I / O-CONT 1A.
The area E1 corresponding to 2, 3, 4,..., FF is for storing setting data at the time of initial startup (at the time of power-on).
100, 101, 103, ..., 109 and 10A, 10
An area E2 corresponding to B, 10C, 10D,... 1FF forms a loop for data transfer between the LSIs # 1 to # 4 during normal operation. At the time of initial startup (at the time of power-on), reading is performed on the areas E1 and E2, but reading during normal operation is performed in a loop in the area E2.

Here, for example, the address of LSI # 1 is set by the 100th table data, the address of LSI # 2 is set by the 101st table data, and
The address of LSI # 4 is set in the third table data, and LSI # 1, # 2,
LSI # to I / O port address set to # 4
3 is transferred. 106-108, 109-10
The same operation is performed for A, 10B to 10D, and the table data is divided.

Read is read from the I / O port,
write to the I / O port and set the address to Do
n't Care and N setting Read in advance I / O
Write to the LSI whose address is set,
Read for LSI specified by LSI type
Shall do. However, during execution of the N setting Read and the address holding command, the data section is Don't Ca
re.

Thus, the I / O-CONT1A
Sets the transfer destination address in the holding circuit 3 and switches the input / output of the bidirectional buffer 2 in accordance with the type of the command, so that the LSI # 1 to # 4
Perform d / Write.

If data transfer is performed in accordance with such bidirectional buffer control, the conventional bidirectional buffer is controlled on a common data bus in a one-to-one (Read 1: Write 1) manner, instead of a one-to-N (Read 1) control. : Write
N), it is possible to change to a method controlled by LSI # 1.
Since the I / O port (arbitrary address port) inside # 4 can simultaneously share a single data, it is possible to perform stable and reliable data transfer without causing any trouble in functional operation. Can be.

FIGS. 4A and 4B are views for explaining the operation of the I / O port setting device. FIG. 4A relates to a block diagram in one operation state, and FIG. It relates to a timing chart of a signal waveform in the state of a).

For example, as shown in FIG. 4A, the LSI # 1 is left as it is in one operation state, the LSI # 2 is read, and the data stored in the LSI # 2 is read into the LSIs # 3 and # 3. When Write is simultaneously performed for the specific I / O port # 4, the signal waveforms for the common data bus, the common data bus, the operation instruction signals # 1 to # 4, and the address holding signals # 1 to # 4 are respectively shown in FIG. The configuration is as shown in b).

Although the number of the LSI, the bidirectional buffer 2, and the holding circuit 3 in the I / O port setting device of one embodiment is four, it may be other numbers.

[0034]

As described above, according to the bidirectional buffer control type I / O port setting device of the present invention, the I / O-CO
NT is connected, and a transfer destination address related to the LSI is set in advance in a holding circuit corresponding to a data transfer target of the LSI before executing data transfer;
An operation instruction signal is transmitted for each LSI by the I / O-CONT to read the read setting source I / O port related to the LSI and simultaneously write to the write setting target I / O port. Instead of controlling the bidirectional buffer on a one-to-one basis (Read1: Write1), the method may be changed to a one-to-N (Read1: WriteN) control scheme (where N is 1 to the number of fanouts of the bidirectional buffer). It is possible to use multiple LSI
Since an internal I / O port (arbitrary address port) can provide a function of sharing a single data at the same time, even if the number of circuits in the configuration increases, a problem occurs in the functional operation. And stable and reliable data transfer can be performed.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing a basic configuration of a bidirectional buffer control type I / O port setting device according to an embodiment of the present invention.

FIG. 2 illustrates a command form in an I / O-CONT provided in the I / O port setting device shown in FIG.

FIG. 3 illustrates an example of divided table data in an I / O-CONT provided in the I / O port setting device shown in FIG.

4A and 4B are views for explaining the operation of the I / O port setting device shown in FIG. 1, in which FIG. 4A relates to a block diagram in one operation state, and FIG. It relates to a timing chart of a signal waveform.

FIG. 5 is a functional block diagram showing a basic configuration of a conventional bidirectional buffer control type I / O port setting device.

6A and 6B are diagrams for explaining the operation of the I / O port setting device shown in FIG. 5, in which FIG. 6A relates to a block diagram in one operation state, and FIG. It relates to a timing chart of a signal waveform.

[Explanation of symbols]

 1A, 1B I / O-CONT 1a Normal operation table 1b Initial start-up table 2 Bidirectional buffer 3 Holding circuit

Claims (3)

[Claims] 1. A bidirectional buffer control type I / O port setting device in which a dedicated circuit for setting an I / O port is connected to a plurality of LSIs with a bidirectional buffer interposed therebetween. A bidirectional buffer and a holding circuit, wherein the bidirectional buffer performs data transfer on a common data bus in response to an I / O buffer switching signal for each of the plurality of LSIs from the I / O port setting dedicated circuit; The holding circuit holds an address on a common address bus in response to an address holding signal for each of the plurality of LSIs from the I / O port setting dedicated circuit, and the I / O port setting dedicated circuit holds the address for each of the plurality of LSIs. A bidirectional buffer control type I / O port setting device for transmitting operation instruction signals including writing, reading, and stopping. 2. The bidirectional buffer control formula I according to claim 1.
In the I / O port setting device, the I / O port setting dedicated circuit includes the plurality of LSIs according to the operation instruction signal.
A bidirectional buffer control type I / O port setting device, which simultaneously reads a read setting source I / O port and writes data to a write setting target I / O port. 3. The bidirectional buffer control type I / O port setting device according to claim 1, wherein the I / O port setting dedicated circuit determines transfer destination addresses for the plurality of LSIs before executing data transfer. A bidirectional buffer control type I / O port setting device, wherein the setting is made in the holding circuit corresponding to a data transfer target among the plurality of LSIs.