JPH10107272A - Semiconductor device with high breakdown strength and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with high breakdown strength, and a fabrication method thereof, in which the channel length can be set accurately while allowing fine patterning and suppressing increase in the number of fabrication steps. SOLUTION: A source region 11 and a subdrain region 12 are formed simultaneously by a self-alignment technology using a gate electrode 4 provided on a P type silicon substrate 2 as a mask. Consequently, an accurate channe.l length can be attained. The subdrain region 12 is connected with a drift drain region 5 formed by implanting impurities at low concentration. In the case of a lightly doped PN junction, a depletion layer is widened in the vicinity of the junction. When a high voltage of 500V is applied to the drain region 13, as shown at B, the depletion layer 9 is extended and the drift drain region 5 is depleted completely to cause applied voltage drop in the range L6 of the drift drain region 5 thus realizing a transistor having high breakdown strength.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-breakdown-voltage semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device capable of accurately forming a channel length, miniaturizing the device, and suppressing an increase in the number of manufacturing steps. And a method for manufacturing the same.

[0002]

2. Description of the Related Art FIG. 7A shows a structure of a MOS transistor. The channel length L8 between the drain region (N ⁺ ) 45 and the source region (N ⁺ ) 46 has an important influence on the characteristics of the transistor. Therefore, the gate electrode 44
The drain region 45 and the source region 46 are formed by self-alignment using the mask as a mask. By forming the drain region 45 and the source region 46 using the gate electrode 44 as a mask, misalignment can be avoided and an accurate channel length L8 can be obtained.

[0003] In order to increase the breakdown voltage of a semiconductor device, a high breakdown voltage semiconductor device having a drift drain region has been conventionally provided. FIG. 7B shows a conventional high breakdown voltage transistor. In the vicinity of the junction between the P-type semiconductor and the N-type semiconductor, electrons and holes are combined to form a depletion layer in which neither electrons nor holes exist. When a reverse voltage is applied, the depletion layer functions as an insulator. The larger the width of the depletion layer, the higher the breakdown voltage and the less likely it is to cause dielectric breakdown. In the case of a PN junction having a low impurity concentration, the width of the depletion layer increases.

For this reason, as shown in FIG. 7B, an N ⁻ -type drift drain region 48 having a low impurity concentration is formed in the P-type silicon substrate 2 to obtain a wide depletion layer. Since the drift drain region 48 is of the N ⁻ type, it becomes a PN junction having a low impurity concentration, and the depletion layer 49 having a large depletion layer width L9.
Occurs, and the breakdown voltage can be increased.

It is necessary to connect the drain electrode to a region having a high impurity concentration. Therefore, an N ⁺ -type drain region 45 is formed in the drift drain region 48, and a drain electrode is connected thereto. Further, a thick dielectric region 47 is provided above the drift drain region 48 in order to ensure a withstand voltage, and a part of the gate electrode 44 covers the dielectric region 47 in order to ensure a withstand voltage in the gate electrode 44 portion. .

In manufacturing the high breakdown voltage semiconductor device shown in FIG. 7B, first, an impurity having a relatively low concentration is implanted into the P-type silicon substrate 2 to form an N ⁻ -type drift drain region 4.
8 is formed. Thereafter, a dielectric region 47 is formed, and a gate electrode 44 is formed so as to partially cover the dielectric region 47. Then, using the gate electrode 44 as a mask, a high concentration impurity is implanted to form the source region 46 and the drain region 45 is formed in the drift drain region 48.

[0007]

However, the above-mentioned conventional high breakdown voltage semiconductor device has the following problems. In the conventional high breakdown voltage semiconductor device shown in FIG. 7B, the drift drain region 48 is first formed in a step before the gate electrode 44 is formed as described above. Therefore, the drift drain region 48 cannot be formed by self-alignment using the gate electrode 44 as a mask. Therefore, it is difficult to obtain an accurate channel length L8, and the channel portion cannot be miniaturized.

If the drift drain region 48 is to be formed by self-alignment using the gate electrode 44 as a mask, N ^{− in} the step after the gate electrode 44 is provided.
In order to form the type drift drain region 48, it is necessary to implant a low concentration impurity. The drift drain region 48 is usually formed in a step before the gate electrode 44 is provided,
For example, it is formed at the same time when a low concentration impurity is implanted for forming a channel stopper.

That is, if the drift drain region 48 is to be formed by self-alignment using the gate electrode 44 as a mask, it is necessary to add a step of implanting a low-concentration impurity after the gate electrode 44 is formed. A new problem arises in that the number increases.

Accordingly, the present invention provides a high-breakdown-voltage semiconductor device and a method of manufacturing the same, which can accurately form a channel length, can be miniaturized, and can suppress an increase in the number of manufacturing steps. Aim.

[0011]

According to a first aspect of the present invention, there is provided a high withstand voltage semiconductor device comprising: a semiconductor substrate;
A second region, which is formed on the semiconductor substrate, forms a spacing region between the first region and the second region, and is a conductor provided on the semiconductor substrate and provided at a position substantially corresponding to the spacing region. A conductor for selectively forming a channel in the interval region or erasing the channel, a third region formed in the semiconductor substrate, a second region formed in the semiconductor substrate,
A voltage drop region connected to the region and the third region and not connected to the interval region, wherein the voltage drop region drops the voltage applied to the third region and transmits the voltage to the second region. Features.

A high withstand voltage semiconductor device according to a second aspect of the present invention is the high withstand voltage semiconductor device according to the first aspect, wherein the voltage drop region is formed on the opposite side of the interval region with the second region interposed therebetween. And

The high breakdown voltage semiconductor device according to claim 3 is the high breakdown voltage semiconductor device according to claim 1 or 2,
The semiconductor substrate is of a first conductivity type, and includes a first region, a second region,
The third region and the voltage drop region are of the second conductivity type, the first region, the second region and the third region are formed by implanting high concentration impurities, and the voltage drop region is formed by implantation of low concentration impurities. , Is characterized by that.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a high breakdown voltage semiconductor device, wherein a low concentration impurity is implanted into a semiconductor substrate of a first conductivity type to form a voltage drop region of a second conductivity type.
Forming a conductor on the semiconductor substrate; implanting high-concentration impurities using the conductor as a mask to form a first region of a second conductivity type and a second region of a second conductivity type connected to the voltage drop region; Forming a region.

[0015]

According to the first aspect of the present invention, the conductor is provided at a position substantially corresponding to the interval region. Therefore, the first region and the second region can be formed at the same time by self-alignment using the conductor as a mask, and the interval region can be formed with a correct length, and a correct channel length can be obtained.

The voltage drop region is connected to the second region and the third region, and is not connected to the interval region. The voltage drop region drops the voltage applied to the third region and transmits the voltage to the second region. . Therefore, the breakdown voltage of the channel portion can be increased, and miniaturization can be achieved.

In the high withstand voltage semiconductor device according to the second aspect, the voltage drop region is formed on the opposite side of the interval region with the second region interposed therebetween. Therefore, after the voltage drop region is formed in the semiconductor substrate, a conductor can be provided at a remote location on the semiconductor substrate, and the second region can be formed together with the first region using the conductor as a mask. Therefore, it is not necessary to form a voltage drop region after providing the conductor,
An increase in the number of manufacturing steps can be suppressed.

According to a third aspect of the present invention, the semiconductor substrate is of the first conductivity type, and the first, second, third, and voltage drop regions are of the second conductivity type. The first, second, and third regions are formed by implanting high-concentration impurities, and the voltage drop region is formed by implanting low-concentration impurities.

Therefore, a large depletion layer is formed at the junction between the semiconductor substrate and the voltage drop region, and the voltage applied to the third region is reduced in the voltage drop region where the depletion layer is enlarged, and the voltage is applied to the second region. Transmitted to the area. Therefore, the withstand voltage of the channel portion can be increased, and miniaturization can be achieved.

According to a fourth aspect of the present invention, in the method of manufacturing a high-breakdown-voltage semiconductor device, a low-concentration impurity is implanted into a first-conductivity-type semiconductor substrate to form a second-conductivity-type voltage drop region. Form a conductor. Then, high-concentration impurities are implanted using the conductor as a mask to form a first region of the second conductivity type and a second region of the second conductivity type connected to the voltage drop region.

As described above, the first region and the second region can be simultaneously formed by the self-alignment using the conductor as a mask, and the interval between the first region and the second region is formed to have an accurate length. Can be.

A second conductivity type voltage drop region is formed by implanting a low concentration impurity into the first conductivity type semiconductor substrate. Therefore, a wide depletion layer is formed at the junction between the semiconductor substrate and the voltage drop region, and the voltage drops in the voltage drop region, so that a semiconductor device with a high breakdown voltage can be obtained.

Furthermore, since the conductor is formed on the semiconductor substrate after the voltage drop region is formed, it is not necessary to form the voltage drop region after the conductor is provided, thereby suppressing an increase in the number of manufacturing steps. Can be.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION

[Structure of Semiconductor Device] One embodiment of a high breakdown voltage semiconductor device according to the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a part of a high breakdown voltage MOS transistor according to the present embodiment. On a P-type silicon substrate 2 which is a semiconductor substrate, a gate electrode 4 as a conductor is provided via a gate oxide film 3.

The first surface of the P-type silicon substrate 2 is
N ⁺ -type source region 11 is a region, a second region N ⁺
A type sub-drain region 12 is formed, and an interval region is formed between the two to form a channel. The source region 11 is connected to a source electrode 11K. In the manufacturing process, the source region 11, the sub-drain region 12
Are simultaneously formed by self-alignment using the gate electrode 4 as a mask, so that an accurate channel length L1 can be obtained.

An N ⁻ -type drift drain region 5 is formed on the opposite side of the channel portion across the sub-drain region 12 while being connected to the sub-drain region 12. A drain region 13 is formed in the drift drain region 5, and a drain electrode 13K is connected to the drain region 13. Although not shown in FIG. 1, a thick dielectric region is provided above the drift drain region 5 and on the surface of the P-type silicon substrate 2 for withstand voltage.

The drift drain region 5 is formed by implanting a low concentration impurity. P with low impurity concentration
In the case of the N-junction, the width of the depletion layer near the junction is large, so that a large depletion layer is formed at the junction between the P-type silicon substrate 2 and the drift drain region 5 in the present embodiment. FIG. 2 shows the relationship between the depletion layer and the drop in applied voltage. 2A and 2B show a state where the channel is erased.

As shown in FIG. 2A, a depletion layer 9 having a depletion layer width L5 is formed at the junction between the P-type silicon substrate 2 and the drift drain region 5. FIG. 2A shows the drain region 13.
Is applied with a relatively low voltage of 5V. In this case, since the voltage applied to the drain region 13 is low, the voltage applied between the source region 11 and the sub-drain region 12 is also low.

On the other hand, for example, the drain region 13
Is applied with a high voltage of 500V. FIG. 2B shows the state at this time. When a high voltage is applied to the drain region 13, the depletion layer 9 expands and the inside of the drift drain region 5 is completely depleted. Then, the voltage drops in the range L6 of the completely depleted drift drain region 5, and the voltage applied between the source region 11 and the sub-drain region 12 can be suppressed low. In the example of FIG. 2B, 495V out of 500V falls in the range L6 and the sub-drain region 12
The voltage drops to 5V near the end of the.

As described above, the drift drain region 5 formed by the low concentration impurity is replaced with the sub drain region 1.
2, the applied voltage is reduced, and a transistor with a high breakdown voltage can be obtained. Since the voltage drop rate in the drift drain region 5 changes depending on the impurity concentration of the drift drain region 5 and the length of the drift drain region 5, the voltage drop rate is adjusted by controlling the impurity concentration and the length. be able to.

In the example shown in FIG. 2B, a high voltage of 500 V is applied to the drain region 13, and the drift drain region 5 is completely depleted due to the expansion of the depletion layer 9, and the applied voltage drops. However, since a voltage drop occurs even when the depletion layer 9 is not completely depleted, the applied voltage can be reduced in a state where the drift drain region 5 is not completely depleted, and the breakdown voltage can be ensured.

[Method of Manufacturing Semiconductor Device] Next, an embodiment of a method of manufacturing a high breakdown voltage semiconductor device according to the present invention will be described in detail with reference to FIGS. First, impurities are implanted into the P-type silicon substrate 2 using the patterned photoresist as a mask, and thermally diffused into the N-well regions 15 and 16.
(FIG. 3A). The range H1 shown in FIG.
An OS transistor is formed, and a PMOS transistor is formed in the range H2 (see FIG. 6B). This range H
1. The transistor formed in H2 is a conventional CMOS.
It is similar to a transistor.

The high breakdown voltage CMOS transistor according to the present embodiment is formed in ranges H3 and H4 shown in FIG. 3A. An NMOS transistor is formed in the range H3, and a PMOS transistor is formed in the range H4 (see FIG. 6B).

First, as shown in FIG. 3A, N-well regions 15 and 16 are formed in a P-type silicon substrate 2. After this,
A pad oxide film 65 and a silicon nitride film 67 are formed on the P-type silicon substrate 2, patterning for LOCOS oxidation is performed, and a pattern is formed using a photoresist 66 (FIG. 3B). Then, the silicon nitride film 6
7. Using the photoresist 66 as a mask, a low concentration impurity for N-type formation is implanted into the channel stop portion.
At this time, low-concentration impurities are simultaneously implanted into the portions where the drift drain regions 5 and 25 are formed.

Subsequently, the photoresist 66 shown in FIG.
Then, a pattern is formed with a new photoresist 68, and a low concentration impurity for forming a P-type is implanted into the channel stop portion using the silicon nitride film 67 and the photoresist 66 as a mask (FIG. 4A). At this time, a low concentration impurity is also implanted into the portions where the drift drain regions 35 and 55 are formed at the same time.

Then, the photoresist 68 is removed, and the patterned silicon nitride film 67 is used as a mask.
An element isolation region 81 selectively on the surface of the P-type silicon substrate 2;
82, 83, 84, 85, 86, 87, 88, 89 are formed (FIG. 4B). Note that a channel stop region and a drift drain region are formed in the portion where the impurities are implanted by thermal diffusion.

Thereafter, as shown in FIGS. 5A and 5B, a gate oxide film is formed by oxidation, a gate electrode material is deposited, and then patterned by a photoresist, and the gate electrodes 64, 74, 4, 24, and 24 are formed on the gate oxide film. 34 and 54 are formed.
Then, using the gate electrodes 64, 4, and 24 as masks, high-concentration impurities for N-type formation are implanted (self-alignment), and thermally diffused to form the source regions 61, 11, 21,.
The drain region 63 and the sub drain regions 12 and 22 are formed. At this time, the drain region 13 is also formed at the same time.

Subsequently, using the gate electrodes 74, 34 and 54 as a mask, a high-concentration impurity for forming a P-type is implanted (self-alignment) and thermally diffused to form the source region 7.
1, 31, 51, a drain region 73, and sub-drain regions 32 and 52 are formed. At this time, a drain region 33 is also formed at the same time.

Then, an interlayer insulating film 10 is formed to provide a contact hole, and the source electrodes 61K, 63K, 71
K, 73K, 11K, 13K, 21K, 31K, 33
After forming K and 51K (FIG. 6B), a protective film is formed and a pad portion is formed (not shown).

Note that the gate electrodes 4, 24, 34, 54 in the above embodiment are conductors and the source region 1
1, 21, 31, and 51 are first regions. The sub-drain regions 12, 22, 32, and 52 are the second region, the drain regions 13 and 33 are the third region, and the drift drain regions 5, 25, 35, and 55 are the voltage drop regions.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a high breakdown voltage CMOS transistor showing one embodiment of a high breakdown voltage semiconductor device according to the present invention.

FIG. 2 is a diagram showing a relationship between a depletion layer and a drop state of an applied voltage in the CMOS transistor shown in FIG.

FIG. 3 is a view showing a manufacturing process of a high breakdown voltage transistor showing one embodiment of the high breakdown voltage semiconductor device according to the present invention.

FIG. 4 is a view showing a manufacturing process of a high breakdown voltage transistor showing one embodiment of the high breakdown voltage semiconductor device according to the present invention.

FIG. 5 is a diagram showing a manufacturing process of a high breakdown voltage transistor showing one embodiment of the high breakdown voltage semiconductor device according to the present invention.

FIG. 6 is a diagram showing a manufacturing process of a high breakdown voltage transistor showing one embodiment of the high breakdown voltage semiconductor device according to the present invention.

FIG. 7A is a sectional view showing a conventional MOS transistor, and FIG. 7B is a sectional view showing a conventional high breakdown voltage transistor.

[Explanation of symbols]

 ... P-type silicon substrate 4, 24, 34, 54... Gate electrode 5, 25, 35, 55... Drift drain region 11, 21, 31, 51. .. Source region 12, 22, 32, 52... Sub-drain region 13, 33... Drain region

Claims (4)

[Claims] A semiconductor substrate, a first region formed on the semiconductor substrate, a second region formed on the semiconductor substrate and forming an interval region between the semiconductor substrate and the first region, and provided on the semiconductor substrate. A conductor provided at a position substantially corresponding to the interval region, a conductor selectively forming a channel in the interval region or erasing the channel; a third region formed on the semiconductor substrate; A voltage drop region connected to the second region and the third region and not connected to the interval region, the voltage being applied to the third region and being transmitted to the second region. A high breakdown voltage semiconductor device comprising: a falling region. 2. The high breakdown voltage semiconductor device according to claim 1, wherein the voltage drop region is formed on a side opposite to the interval region with the second region interposed therebetween. 3. The high breakdown voltage semiconductor device according to claim 1, wherein the semiconductor substrate is of a first conductivity type, and the first region, the second region, the third region, and the voltage drop region are:
A second conductivity type, wherein the first region, the second region, and the third region are formed by implanting high-concentration impurities; and the voltage-drop region is formed by implantation of low-concentration impurities. High withstand voltage semiconductor device. 4. A step of implanting a low-concentration impurity into a semiconductor substrate of a first conductivity type to form a voltage drop region of a second conductivity type; a step of forming a conductor on the semiconductor substrate; Implantation of impurities at a second concentration
Forming a first region of the conductivity type and a second region of the second conductivity type connected to the voltage drop region.