JPH10107184A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a rate of effective area of a semiconductor device. SOLUTION: In a semiconductor substrate, at least first and second semiconductor chips 61 and 81 wherein an active element is formed, and first and second external connecting means 62, 63, 82 and 83 which are provided on the first and second semiconductor chips and are electrically connected with an electrode pads are provided. The first and the second semiconductor chips 61 and 81 are adjacently arranged, the first and the second external connecting means 62, 63, 82 and 83 are arranged in the vicinity of both semiconductor chips, and the first and the second external connecting means and one of the major planes of the first and the second semiconductor chips are exposed to be fixed by sealing resin 100.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having an improved effective mounting area ratio represented by a ratio of a chip area of the semiconductor device to a mounting area for mounting the semiconductor device on a mounting board such as a printed board.

[0002]

2. Description of the Related Art Generally, a semiconductor device in which a transistor element is formed on a silicon substrate mainly has a structure as shown in FIG. 1 is a silicon substrate, 2 is an island such as a heat sink on which the silicon substrate 1 is mounted, 3 is a lead terminal, and 4 is a resin mold for sealing.

As shown in FIG. 3, a transistor element formed on a silicon substrate 11 is, for example, an N-type epitaxial layer 1 serving as a collector region on an N-type silicon substrate 11.
2, a P-type impurity such as boron is diffused into the base region 13.
Is formed, and an N-type impurity such as phosphorus is diffused in base region 13 to form emitter region 14. Base region 13 and emitter region 14 are provided on the surface of silicon substrate 11.
An insulating film 15 having an opening exposing a part of the base region 13 and the exposed emitter region 14 is formed.
A metal such as aluminum is deposited on the base electrode 16,
An emitter electrode 17 is formed. In the transistor having such a configuration, the silicon substrate becomes the collector electrode 18.

As described above, the silicon substrate 1 on which the transistor elements are formed is fixedly mounted on an island 2 such as a copper-based heat sink through a brazing material 5 such as solder, as shown in FIG. The base electrode and the emitter electrode of the transistor element are electrically connected to the lead terminals 3 arranged around the substrate 1 by wires by wire bonding. The lead terminal connected to the collector electrode is formed integrally with the island, and after being electrically connected by mounting a silicon substrate on the island, transfer molding is performed using a thermosetting resin 4 such as an epoxy resin. A semiconductor device having a three-terminal structure is provided by completely covering and protecting a silicon substrate and part of a lead terminal.

[0005]

A resin-molded semiconductor device is usually mounted on a mounting substrate such as a glass epoxy substrate, and is electrically connected to other semiconductor devices and circuit elements mounted on the mounting substrate. It is handled as one component for performing a predetermined circuit operation. FIG. 9 is a cross-sectional view of a semiconductor device mounted on a mounting substrate. Reference numeral 20 denotes a semiconductor device, reference numerals 21 and 23 denote lead terminals for base or emitter electrodes, reference numeral 22 denotes a lead terminal for collector, and reference numeral 30 denotes a mounting substrate. It is.

The mounting area where the semiconductor device 20 is mounted on the mounting board 30 is represented by a region surrounded by the lead terminals 21, 22, and 23 and conductive pads connected to the lead terminals. The mounting area is larger than the area of the silicon substrate (semiconductor chip) in the semiconductor device 20, and most of the mounting area is taken by the mold resin and the lead terminals as compared with the area of the semiconductor chip having an actual function.

Here, considering the ratio between the area of the semiconductor chip having the actual function and the mounting area as the effective area ratio,
It has been confirmed that a resin-molded semiconductor device has an extremely low effective area ratio. The low effective area ratio means that
When the semiconductor device 20 is used for connection with another circuit element on the mounting board 30, most of the mounting area becomes a dead space which is not directly related to a semiconductor chip having a function. If the effective area ratio is small, the dead space on the mounting substrate 30 increases as described above, which hinders the high-density and miniaturization of the mounting substrate 30.

In particular, this problem appears remarkably in a semiconductor device having a small package size. For example, as shown in FIG. 10, the maximum size of a semiconductor chip mounted on the SC-75A outer shape of the EIAJ standard is 0.40 mm × 0.40 mm.
mm is the largest. When this semiconductor chip is connected to metal lead terminals by wires and resin-molded, the overall size of the semiconductor device becomes 1.6 mm × 1.6 mm. The chip area of this semiconductor device is 0.16 mm, and the mounting area for mounting the semiconductor device is 2.56 mm, assuming that it is almost the same as the area of the semiconductor device. Therefore, the effective area ratio of this semiconductor device is about 6.25. %, And most of the mounting area is a dead space that is not directly related to the area of the semiconductor chip having functions.

The problem relating to the effective area ratio is particularly prominent in a semiconductor device having a very small package size and a large chip size as described above. However, the semiconductor chip is wire-connected with metal lead terminals and resin-molded. A similar problem arises with a resin-sealed semiconductor device. In recent years, mounting substrates used in electronic devices, for example, portable information processing devices such as personal computers and electronic organizers, 8 mm video cameras, mobile phones, cameras, liquid crystal televisions, etc. There is also a tendency for high-density and small-sized mounting boards to be used.

However, in the above-mentioned prior art resin-encapsulated semiconductor device, as described above, the mounting area for mounting the semiconductor device has a large dead space. Has been one of the factors that hindered the miniaturization of the system. Incidentally, Japanese Patent Application Laid-Open No. 3-248551 is a prior art for improving the effective area ratio. This prior art will be briefly described with reference to FIG. In this prior art, lead terminals 41, 42, and 43 connected to a base, an emitter, and a collector electrode of a semiconductor chip 40 are formed in order to minimize a mounting area when a resin mold type semiconductor device is mounted on a mounting substrate or the like. It is described that the lead terminals 41, 42, and 43 are formed so as not to be led out from the side surface of the resin mold 44 and to be flush with the side surface of the resin mold 44.

According to this structure, the lead terminals 41, 4
The mounting area can be reduced by the extent that the leading end portions of 2, 43 are not led out, and the effective area ratio can be slightly improved. However, in the above-described semiconductor device, the tip end of the lead terminal connected to the semiconductor chip is formed by the resin mold 44.
Since it is bent at the corner of the bottom of the resin, it has a structure that can sufficiently withstand the stress during the bending process, so each lead terminal embedded in the resin mold must have a sufficient length, As a result, the resin mold size becomes larger than the semiconductor chip size to be mounted, and the effective area ratio does not decrease. Furthermore, each lead terminal connected to a semiconductor chip is required, and material cost and a manufacturing process become complicated, and there is a problem that manufacturing cost cannot be reduced.

In order to maximize the effective area ratio, as described above, the semiconductor chip is directly mounted on the mounting board, so that the semiconductor chip area and the mounting area are almost the same and the effective area ratio is maximized. . As one prior art for mounting a semiconductor chip on a substrate such as a mounting substrate, for example, as shown in JP-A-6-338504, a flip chip in which a plurality of bump electrodes 46 are formed on a semiconductor chip 45 is mounted on a mounting substrate. A technique for performing face-down bonding on a surface 47 is known (see FIG. 12). In this prior art, a gate (base) electrode, a source (emitter) electrode,
A drain (collector) electrode is formed, and a current or voltage path is formed in a lateral direction, and is mainly used for a lateral semiconductor device having a relatively small amount of heat generation.

However, in a vertical semiconductor device such as a transistor device in which a silicon substrate becomes one of the electrodes, each electrode is formed on a different surface, and a current path flows in a vertical direction, the above-mentioned flip chip technology is used. It is difficult to do. As another prior art for mounting a semiconductor chip on a substrate such as a mounting substrate, for example, as shown in JP-A-7-38334, a semiconductor chip 53 is mounted on a conductive pattern 52 formed on a mounting substrate 51 by die. Conductive pattern 5 bonded and placed around semiconductor chip 53
A technique for connecting the electrodes of the semiconductor chip 53 and the semiconductor chip 53 with wires 54 is known (see FIG. 13). In this prior art, the above-described silicon substrate can be used for a semiconductor chip such as a transistor having a vertical structure in which one electrode forms one electrode.

The wire 54 for connecting the semiconductor chip 53 and the conductive pattern 52 disposed around the semiconductor chip 53 is usually a gold wire, and therefore, the peel strength (tensile force) of the bonding joint connected to the gold wire by bonding. Is preferably performed in a heating atmosphere at about 200 ° C. to 300 ° C. However, when a semiconductor chip is die-bonded on an insulating resin-based mounting substrate, the mounting substrate may be distorted when heated to the above-mentioned temperature, and a chip capacitor and a chip resistor mounted on the mounting substrate may be distorted. Since the solder for fixing other circuit elements is melted, the wire bonding connection is performed at a heating temperature of about 100 ° C. to about 150 ° C.,
There is a problem that the peel strength of the bonding portion is reduced.

In this prior art, usually, the die-bonded semiconductor chip is covered and protected with a sealing resin such as an epoxy resin, so that the decrease in peel strength is caused by shrinkage of the epoxy resin during thermosetting or the like. There is a problem that is peeled off. The present invention has been made in view of the above-mentioned circumstances, and the present invention has an arrangement in which external connection electrodes for the base, emitter, and collector of each semiconductor chip of a semiconductor device having a plurality of semiconductor chips built therein are on the same plane. A semiconductor device in which the effective area ratio, which is the ratio of the area of each semiconductor chip to the mounting area of a single semiconductor device mounted on a mounting substrate, is maximized, and the dead space of the mounting area is minimized; The manufacturing method is provided.

[0016]

The present invention employs the following constitution and manufacturing method to solve the above-mentioned problems. That is, a semiconductor device according to the present invention includes first and second semiconductor chips each having at least an active element formed in a semiconductor substrate;
First and second external connection means provided on the surfaces of the first and second semiconductor chips and electrically connected to the electrode pads, wherein the first and second semiconductor chips are arranged adjacent to each other; The first and second external connection means are arranged in the vicinity of the two semiconductor chips, and the first and second external connection means and one main surface of the first and second semiconductor chips are exposed and sealed. It is characterized by being fixed with a stopping resin.

The semiconductor device according to claim 1, wherein the first and second external connection means and one main surface of the first and second semiconductor chips are arranged on the same plane. . In the method of manufacturing a semiconductor device according to the present invention, a plurality of first semiconductor chips and a plurality of first semiconductor chips are provided on an insulating resin layer formed on one main surface of a support substrate in a direction of n rows (or columns). A plurality of first external connection means electrically connected to the electrode pads; and die bonding such that the first semiconductor chip and the first are regularly arranged in the (n + 1) th row (or column) direction. Electrically connecting an electrode pad provided on the surface of the semiconductor chip to the external connection means with a wire, covering a main surface of the support substrate with a sealing resin, and connecting the semiconductor chip and the external connection. After fixing the means, the supporting substrate is peeled off so as to expose the surfaces of the semiconductor chip and the external connection means, and at least one semiconductor chip and the external connection means connected to the semiconductor chip are included. It is characterized by dividing individually by the sealing resin region's.

As described above, according to the semiconductor device of the present invention, the first and second semiconductor chips arranged adjacent to each other, the first and second external connection means arranged near the semiconductor chip, and the second semiconductor chip are connected to each other. First and second semiconductor chips and first and second external connection means for electrically connecting with the first and second semiconductor chips and serving as external electrodes for mounting and fixing on a mounting board such as a wiring board. Is fixed with a sealing resin so as to expose one main surface, so that a metal lead terminal for connecting an external electrode for mounting a semiconductor chip is unnecessary as in a conventional semiconductor device, and the lead Since the terminals and other lead terminals connected to the surface electrodes of the semiconductor chip are not led out of the sealing resin, the external dimensions of the semiconductor device having a plurality of semiconductor chips can be significantly reduced. Can.

Further, according to the method of manufacturing a semiconductor device of the present invention, the first and second semiconductor chips and the first
Then, after mounting the second external connection means, making an electrical connection and fixing with a sealing resin, the support substrate is peeled off, and at least one
By dividing the semiconductor chip and the external connection means connected to the semiconductor chip individually into the encapsulating resin region, metal lead terminals as in a conventional semiconductor device can be eliminated. Production cost can be reduced and mass production can be realized.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described. As shown in FIG. 1, the semiconductor device of the present invention has first and second semiconductor chips 61 and 81 on which active elements are formed, and a first electrode that is electrically connected to surface electrodes of the semiconductor chips 61 and 81. And second external connection means 62, 63, 82, 83,
And a sealing resin 100 for fixing the second semiconductor chips 61 and 81 and the first and second external connection means 62, 63, 82 and 83.

The first and second semiconductor chips 61 and 81 have active elements such as transistors formed therein.
As shown in FIG. 3, the first semiconductor chip 61 has N +
An N − -type epitaxial layer 12 is formed on a single-crystal silicon substrate 11 by an epitaxial growth technique, and an active element such as an NPN transistor is formed on the semiconductor substrate 11. On the other hand, active elements are similarly formed on the second semiconductor chip 81. Either an NPN transistor or a PNP transistor may be formed in the second semiconductor chip 81, but here, a PNP transistor is formed in order to use the collector electrode commonly connected by a pattern on the mounting substrate ( Not shown).

The present invention is particularly suitable for a device having a so-called vertical structure having external connection electrodes on the front and back surfaces of the semiconductor chip 61. FIG. 3 is a cross-sectional view of the general NPN transistor described above. For example, a transistor having an N− type epitaxial layer 12 as a collector region is formed, and a photoresist is formed on a semiconductor substrate 11. P-type impurities such as boron (B) are selectively thermally diffused into the region exposed by the photoresist to form an island-like base region 13 having a predetermined depth.

After the formation of the base region 13, a photoresist is formed again on the semiconductor substrate 11, and N-type impurities such as phosphorus (P) and antimony (Sb) are selectively heated in the base region 13 exposed by the photoresist. The diffusion forms the emitter region 14 of the transistor. When forming the emitter region 14, a ring-shaped guard ring N + type diffusion region surrounding the base region 13 may be formed in some cases.

The base region 1 is formed on the surface of the semiconductor substrate 11.
An insulating film 15 such as a silicon oxide film or a silicon nitride film having a base contact hole exposing the three surfaces and an emitter contact hole exposing the emitter region surface is formed. Base region 13 and emitter region 14 exposed by base contact hole and emitter contact hole
A base electrode 16 and an emitter electrode 17 and a pad (not shown) for external connection of these electrodes are formed on the base electrode 16 and the emitter electrode 17 selectively deposited by a metal material such as aluminum. A metal plating process is performed on the back surface of the semiconductor substrate 11 to be used as the collector electrode 18. On the other hand, a PNP transistor is formed on the second semiconductor substrate 81 in the same manner as described above using a P-type semiconductor substrate, although not particularly described.

The feature of the present invention is that the external connection electrode pads (base electrode, emitter electrode) provided on the surface side of the first and second semiconductor chips 61 and 81 are formed by the first
And disposed on the same side as the external connection electrodes (collector electrodes) on the back surfaces of the semiconductor chips 61 and 81 without being led out of the sealing resin 100 via the second external connection means 62, 63, 82 and 83; The object is to minimize the size of the sealing resin and to improve the effective area ratio by making it compact.

First and second external connection means 62, 63,
82, 83 are the first and second semiconductor chips 61, 81
The semiconductor chips 61 and 8 correspond to the number of external connection electrode pads for base and emitter provided on the surface.
1 (see FIG. 2). The first and second external connection means 62, 63, 82, 83 and the base and emitter electrode pads of the first and second semiconductor chips 61, 81 are connected by a wire made of a thin metal wire such as gold or aluminum. An electrical connection is made.

The external connection means 62, 63, 82, 83 are not particularly limited as long as they are made of a metal piece such as copper, invar, tellurium, or a conductive material such as a silicon chip made of a silicon material. In this embodiment,
Silicon chips are used in consideration of workability and cost. Semiconductor chips 61 and 81 electrically connected by wires and silicon chips 62 and 63 for external connection,
82 and 83 are fixed with a thermosetting sealing resin 100 such as an epoxy resin. At this time, the first electrode serving as a collector electrode
And the back surfaces of the second semiconductor chips 61 and 81 and the external connection silicon chips 6 serving as emitter electrodes and base electrodes.
The rear surfaces of 2, 63, 82 and 83 are arranged on the same plane.

As described above, according to the present invention, unlike a conventional semiconductor device, a metal lead terminal for connecting an external electrode for mounting a semiconductor chip is not required, and the lead terminal and the surface electrode of the semiconductor chip are not required. Since the other lead terminals connected to the semiconductor device are led out of the sealing mold resin, the external dimensions of the semiconductor device can be significantly reduced. More specifically, in the present invention, the first and second semiconductor chips 61 and 81 are incorporated in a single semiconductor device, and the back surfaces of the semiconductor chips 61 and 81 are directly connected to the mounting substrate. The external connection means connected to the surface electrodes of the semiconductor chips 61 and 81 are connected to the silicon chips 62, 63 and 8 respectively.
2, 83, the semiconductor chips 61, 8
It is possible to eliminate the need for a metal lead terminal to be connected to the first terminal.

The following is a description of a method of manufacturing a semiconductor device according to the present invention. First, as shown in FIG.
A plurality of first and second semiconductor chips 61, 81 and a plurality of first and second silicon chips 62, 63, 82, 83 on an insulating resin layer 71 made of polyimide resin or the like on one main surface.
Are arranged regularly. First and second semiconductor chips 6
When the collector electrodes 1 and 81 are commonly connected by a wiring pattern on the mounting substrate, for example, as shown in FIG. 5, the first semiconductors are arranged in the n-row and n-row + even-numbered row directions of the support substrate 70. The chip 61 is mounted, and the second semiconductor chip 8 is disposed adjacent to the first semiconductor chip 61 in the (n + odd) th row direction.
1 is implemented. Adjacently mounted semiconductor chips 61 and 8
A plurality of first and second silicon chips 62 sandwiching 1
63, 82 and 83 are mounted.

The support substrate 70 is made of a material having relatively good thermal conductivity, for example, a thin film having a thickness of about 0.3 mm to 1.2 mm formed of copper, aluminum, ceramics, glass epoxy, or the like. Substrate is used. A polyimide resin having a thickness of about 2 μ to 5 μ is adhered on the supporting substrate 70 at a heating temperature of about 300 ° C. to about 400 ° C. The plurality of first and second semiconductor chips 61 and 81 and the first and second silicon chips 62, 63, 82 and 83 heat the support substrate 70 at a heating temperature lower than the above-described heating temperature, for example, about 200 ° C. It is mounted on the support substrate 70 while being heated to about 300 ° C. If the heating temperature at this time is higher than the initial heating temperature, the adhesive force becomes too high when the semiconductor chips 61, 81, etc. are die-bonded onto the insulating resin layer 71. Adversely affect

In this embodiment, the first and second external connection means 62, 63, 82, 83 use silicon chips as described above. This silicon chip 62, 6
The size of each of the semiconductor chips 61, 81
Although it depends on the size, for example, when the semiconductor chip size is 0.40 mm × 0.40 mm, the silicon chip size may be designed to be about 0.25 mm × 0.25 mm. Therefore, similarly to the semiconductor chips 61 and 81, the silicon wafers of the silicon chips 62, 63, 82 and 83 can be individually formed by a well-known dicing technique. Silicon chips 62, 63, 82 used in the present embodiment,
In 83, high-concentration impurities are diffused from the surface to the opposite main surface for the purpose of reducing the internal resistance.

Each chip is picked up from the individually formed silicon wafer on the support substrate 70 by a die bonding apparatus, and regularly arranged in a region designated on the support substrate 70 as shown in FIG. A plurality of first and second semiconductor chips 61 and 81, and a first
Then, the second silicon chips 62, 63, 82, and 83 are die-bonded in the above-described arrangement.

In this embodiment, one semiconductor chip 6
1 (81) and silicon chips 62, 63 (82, 83) corresponding to the semiconductor chip 61 (81) are die-bonded on the support substrate 70 so as to form a triangle. The die-bonded chips are bonded by the adhesive force of the insulating resin layer 71 formed on the support substrate 70.
It is temporarily fixed on the support substrate 70.

After mounting both chips on the support substrate 70,
As shown in FIGS. 1 and 2, silicon chips 62, 63, and 82 for external connection corresponding to base and emitter electrode pads formed on the surfaces of the semiconductor chips 61 and 81, respectively.
83 is connected by wire bonding with a thin metal wire such as gold or aluminum to make electrical connection. Next, FIG.
As shown in FIG. 2, a thermosetting sealing resin 100 such as an epoxy resin is applied on the support
A heat treatment is performed at a temperature of 0 ° C., and the plurality of first and second semiconductor chips 61 and 81 mounted on the support substrate 70 and the plurality of first and second silicon chips 62, 63 and 8 are mounted.
2 and 83 are fixed with a sealing resin 100. At this time, the semiconductor chips 61, 81 and the silicon chips 62, 63, 8
The thickness of the sealing resin 100 is taken into consideration so that the surfaces of 2, 83 are not exposed.

After the two chips are fixed with the sealing resin 100, the supporting substrate 70 which is in close contact with the sealing resin 100 is peeled off from the sealing resin 100 as shown in FIG. The sealing resin 100 is subjected to scientific peeling to be dissolved using a solvent,
Alternatively, the support substrate 70 is heated to about 150 ° C. to about 200 ° C., and mechanical peeling is performed in a state where the adhesive strength of the resin layer is reduced.
After exfoliating the support substrate 70 and exposing the surfaces of the semiconductor chips 61 and 81 and the silicon chips 62, 63, 82 and 83, at least the first and second semiconductor chips 61 and 81 fixed with the sealing resin 100. And its semiconductor chip 6
First and second silicon chips 6 connected to 1, 81
The sealing resin 100 in the region including 2, 63, 82, and 83, specifically, for example, the arrow line shown in FIG. 7 and the dotted line region shown in FIG. 5 is cut using a cutting device such as a dicing device. By dividing the semiconductor device into individual devices, the semiconductor device having a plurality of semiconductor chips shown in FIG. 1 can be manufactured.

When the effective area ratio of the semiconductor device of the present invention is compared with that of the conventional semiconductor device, the chip size of the semiconductor device described in the conventional example is 0.40 mm × 0.40.
When the semiconductor chip 61 is connected to a metal lead terminal by a wire and molded with a resin, the overall size of the semiconductor device becomes 1.6 mm × 1.6 mm. Chip area is 0.1
The mounting area for mounting the semiconductor device is 2.56 mm2 with respect to 6 mm2, assuming that the mounting area is almost the same as the area of the semiconductor device. Therefore, the effective area ratio of the conventional semiconductor device is about 6.25%
Met.

On the other hand, the semiconductor device of the present invention incorporates a plurality of semiconductor chips, and even if the chip sizes are made the same, no metal lead terminal is required. It can be set to 2 mm × 1.7 mm, the area of the semiconductor device becomes 2.04 mm 2, and the effective area ratio is about 16. %, As compared with two conventional semiconductor devices, it is possible to reduce the dead space of the mounting area mounted on the mounting board, which can contribute to the miniaturization of the mounting board.

In this embodiment, the semiconductor chip 61 (81) and the silicon chips 62, 63 (82, 83) are arranged so as to form a triangle in consideration of the easiness of connection with the mounting board. If they are arranged on a straight line, the effective area ratio can be further improved. According to the method for manufacturing a semiconductor device of the present invention described above, the support substrate 7
0, semiconductor chips 61 and 81 and external connection means 62,
After mounting 63, 82, 83 and making electrical connection and fixing with sealing resin 100, support substrate 70 is peeled off and at least semiconductor chips 61, 81 and their semiconductor chips 61, 81
By separately dividing the sealing resin 100 region including the external connection means 62, 63, 82, and 83 connected to the semiconductor device, metal lead terminals as in the conventional semiconductor device can be eliminated, thereby reducing the production cost. And mass production can be realized.

In this embodiment, the semiconductor chips 61 and 81
The transistor is formed in the vertical direction, but the present invention is not limited to this as long as it is a vertical type or a horizontal type device that generates a relatively small amount of heat. For example, the semiconductor chips 61 and 81 in which devices such as a power MOSFET, IGBT, and HBT are formed. Needless to say, it can be applied to the present invention.

[0040]

As described in detail above, according to the semiconductor device of the present invention, the first and second semiconductor chips arranged adjacent to each other and the first and second semiconductor chips arranged near the semiconductor chip are arranged. The first and second semiconductor chips, and the first and second semiconductor chips, which serve as external electrodes for making electrical connection between the external connection means and the first and second semiconductor chips and mounting and fixing them on a mounting board such as a wiring board. By fixing with a sealing resin to expose one main surface of the external connection means 2, metal lead terminals for connecting external electrodes for mounting a semiconductor chip, unlike a conventional semiconductor device, are not required. Further, since the lead terminals and other lead terminals connected to the surface electrodes of the semiconductor chip are not led out of the sealing mold resin, the external dimensions of the semiconductor device including a plurality of semiconductor chips are significantly reduced. It can be. As a result, the external dimensions of a semiconductor device incorporating a plurality of semiconductor chips can be significantly reduced in size, and unnecessary dead space when mounted on a mounting substrate can be eliminated. It can greatly contribute.

According to the method of manufacturing a semiconductor device of the present invention, the first and second semiconductor chips and the first semiconductor chip are provided on the support substrate.
Then, after mounting the second external connection means, making an electrical connection and fixing with a sealing resin, the support substrate is peeled off, and at least one
By dividing the semiconductor chip and the external connection means connected to the semiconductor chip individually into the encapsulating resin region, metal lead terminals as in a conventional semiconductor device can be eliminated. Production cost can be reduced and mass production can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 2 is a diagram showing a back surface of the semiconductor device of the present invention.

FIG. 3 is a cross-sectional view of a general transistor.

FIG. 4 illustrates a method for manufacturing a semiconductor device of the present invention.

FIG. 5 illustrates a method for manufacturing a semiconductor device of the present invention.

FIG. 6 illustrates a method for manufacturing a semiconductor device of the present invention.

FIG. 7 illustrates a method for manufacturing a semiconductor device of the present invention.

FIG. 8 is a cross-sectional view of a conventional semiconductor device.

FIG. 9 is a cross-sectional view of a conventional semiconductor device mounted on a mounting substrate.

FIG. 10 is a plan view of a conventional semiconductor device.

FIG. 11 is a plan view of a conventional semiconductor device.

FIG. 12 is a cross-sectional view of a conventional semiconductor device mounted on a mounting substrate.

FIG. 13 is a cross-sectional view of a conventional semiconductor device mounted on a mounting board.

Claims (3)

[Claims] A first semiconductor chip having at least an active element formed in a semiconductor substrate; and a first semiconductor chip provided on a surface of the first and second semiconductor chips and electrically connected to an electrode pad. And second external connection means, wherein the first and second semiconductor chips are disposed adjacent to each other, and the first and second external connection means are disposed in the vicinity of the two semiconductor chips. And a second external connection means and a first main surface of the first and second semiconductor chips are exposed and fixed with a sealing resin. 2. The semiconductor device according to claim 1, wherein said first and second external connection means and one main surface of said first and second semiconductor chips are arranged on the same plane. 3. A plurality of first semiconductor chips and an electrode pad provided on the surface of the semiconductor chip and electrically connected to a plurality of first semiconductor chips in an n-row (or column) direction on an insulating resin layer formed on one main surface of the support substrate. A plurality of first external connection means, and n + 1
Die bonding such that the first semiconductor chip and the first semiconductor chip are regularly arranged in a row (or column) direction;
An electrode pad provided on a surface of the semiconductor chip and the external connection means are electrically connected to each other by a wire, and one main surface of the support substrate is covered with a sealing resin to form the semiconductor chip and the external connection means; After fixing, the support substrate is peeled off to expose the surfaces of the semiconductor chip and the external connection means, and the sealing including at least one semiconductor chip and the external connection means connected to the semiconductor chip is performed. A method for manufacturing a semiconductor device, wherein the semiconductor device is divided individually in a resin region for stopping.