JPH10105382A - Information processor and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the circuit scale. SOLUTION: A control circuit 1 stores a value 1 (value for rounding) in a register CRY. Then the control circuit 1 outputs the values A (=(A7 ... A0 of eight bits of a register A, the values B (=B(B7... B0 )) of eight bits of a register B, and the value of one bit of the register CRY to an adding element 21. The adding element 21 calculates the sum (A+B+1) of those values, and outputs the value of the least significant bit (LSB) of the arithmetic result of nine bits to the register CRY and the value (C7 ... C0 ) of the high-order eight bits as a mean value C to the register C. Thus, the mean value C (=(A+B+1)|1) of the two 8-bit data A and B is calculated (|: one-bit shift to the LSB side).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus and method, and more particularly, to a method of adding data of a plurality of first bits and data of a second number of bits stored in a predetermined storage unit. The present invention relates to an information processing apparatus and method for storing lower-order data of a second bit number of an operation result in a predetermined storage unit, outputting remaining upper-order data of the operation result, and calculating an average value of a plurality of data.

[0002]

2. Description of the Related Art With the advance of semiconductor technology, digital signal processing such as digital image processing is performed in various devices.

In digital image processing, for example, when increasing the number of pixels of image data, the value of a new pixel is
It is calculated from the values of original pixels in a predetermined area using interpolation. For example, the value of a new pixel is the value of four original pixels A,
Using B, C, and D, it is calculated as an average value of these four pixel values ((A + B + C + D) / 4).

When a pixel value is represented by an 8-bit integer, a number obtained by dividing the sum of four pixel values by 4 is rounded (rounded) to a decimal part and converted to an integer.

The rounding (rounding) is performed by adding 0.5 to a predetermined number a.
Is added (a + 0.5) and the fractional part of the number is rounded down. Therefore, when calculating the average value of N data as an integer, first, the sum Σ of the N data is expressed as
Add the value for rounding (0.5 × N) (Σ + 0.5 ×
N), then divide the value by N (Σ / N + 0.5),
Finally, the fractional part of the value can be truncated.

That is, the average value of four 8-bit (N = 4) pixel data A, B, C, and D is obtained by adding the rounding value to the sum of the 8-bit pixel data A, B, C, and D. 2 (= 0.5 ×
4) The value obtained by adding ({1, 0} in binary) is represented by LSB
(Least Significant Bit) is calculated by shifting by 2 bits.

[0007] From now on, the n-bit binary number is:
{A _n ,..., A _i ,..., A ₀ } (A _i represents the value of the ith bit).

For example, when one adder is used to calculate the average value of the above-described four 8-bit pixel data A, B, C, and D in a time series, first, an 8-bit data is calculated. Data A and 8-bit data B are added. The operation result E (= A + B) at this time is represented by 9 bits.

Next, 8-bit data C and 8-bit data D are added. The calculation result F (=
C + D) is represented by 9 bits.

Then, two 9-bit operation results E and F
Are added. Calculation result G (= E + F) at this time
Is represented by 10 bits. Further, the calculation result G
Is added to the rounding value {1, 0}.

Finally, by ignoring the lower 2 bits of the operation result G (10 bits) after adding the rounding value {1, 0}, that is, taking the upper 8 bits, 4
The average value of the 8-bit data A, B, C, and D is calculated as an integer (8 bits).

[0012]

However, as described above, when an average value is calculated from a plurality of 8-bit data, for example, although the calculated average value is 8 bits, the average value of the data is calculated. In the process of calculating the sum, 9-bit or 10-bit data is generated, so that the first data and the first data are transferred between the register for holding the data and the adder for performing the operation. A transmission path having a bit width wider than the number of bits of the calculated average value is required, and it is difficult to reduce the circuit scale.

The present invention has been made in view of such a situation, and adds a plurality of data of a first number of bits and data of a second number of bits stored in a predetermined storage unit. The lower-order data of the second number of bits of the operation result is stored in a predetermined storage unit, and the remaining upper-order data of the operation result is output, so that the same number of bits as the number of bits of the first data and the calculated average value are output. This allows processing to be performed on a transmission path having a width.

[0014]

According to a first aspect of the present invention, there is provided an information processing apparatus comprising: a storage unit for storing data of a first number of bits; a plurality of data of a second number of bits; And adding means for adding data of the first number of bits, storing lower-order data of the first number of bits of the operation result in the storage means, and outputting remaining upper-order data of the operation result. I do.

According to a fourth aspect of the present invention, in the information processing method, a plurality of data having a first number of bits and data having a second number of bits stored in a predetermined storage section are added, and a second result of the operation result is obtained.
And storing the lower-order data of the number of bits in a predetermined storage unit and outputting the remaining upper-order data of the operation result.

According to a fifth aspect of the present invention, there is provided an information processing apparatus which stores first to Nth data of a first bit number.
Storage means, first to N-th sets of data of a plurality of second bits, and first data stored by the storage means.
The first to Nth data of the number of bits of
It is characterized by comprising N number of adding means for respectively storing the lower-order data of the first number of bits of each operation result in the storage means and outputting the remaining upper-order data of each operation result.

In the information processing method according to the present invention, the first to Nth sets of data having a plurality of first bits and the second set of data stored in N predetermined storage units, respectively. The first to N-th data of the number of bits are respectively added, the lower data of the second number of bits of each operation result are stored in N predetermined storage units, and the remaining upper data of each operation result is stored. It is characterized by comprising a step of outputting each.

In the information processing apparatus according to the first aspect, the storage means stores the data of the first number of bits, and the adding means stores the data of the plurality of second bits and the storage means. The data of the first number of bits are added, the lower data of the first number of bits of the operation result is stored in the storage means, and the remaining upper data of the operation result is output.

In the information processing method according to the present invention, the data of the first number of bits and the data of the second number of bits stored in the predetermined storage unit are added, and the result of the operation is calculated. The low-order data of 2 bits is stored in a predetermined storage unit, and the remaining high-order data of the operation result is output.

In the information processing apparatus according to the fifth aspect, the N storage means stores the first to Nth bits of the first number of bits.
, Respectively, and the N number of adders include first to Nth sets of data having a plurality of second bits, and first to Nth sets of the first bits stored in the storage. The N-th data is added, the lower data of the first number of bits of each operation result is stored in the storage unit, and the remaining upper data of each operation result is output.

In the information processing method according to the present invention, the first to N-th sets of data of a plurality of first bits and the second set of data stored in N predetermined storage units, respectively. Are added to each other, and lower-order data of the second bit number of each operation result are respectively stored in N predetermined storage units, and the remaining upper-order data of each operation result is added. Are output.

[0022]

FIG. 1 shows the configuration of an information processing apparatus according to a first embodiment of the present invention. The control circuit 1
Operates according to the program stored in the memory 2,
For example, the interface 3 is transmitted from a predetermined device (not shown).
Is output to the register file 11 of the adder circuit 4 and the value calculated by the adder circuit 4 is output via the interface 3.

The register file 11 of the adder circuit 4 contains 8
In addition to the bit registers A, B, and C, and a plurality of 8-bit registers D to Q (not shown), a 1-bit register CRY (storage means) is provided.

The adding element 21 (adding means) of the adding circuit 4
Calculates the sum of two 8-bit values supplied from a predetermined two 8-bit registers of the register file 11 via an 8-bit transmission path and a 1-bit value supplied from the register CRY, The value of the lower 1 bit (LSB) of the 9-bit operation result is output to the register CRY,
The bit value is output to any of the 8-bit registers of the register file 11 via an 8-bit transmission path.

For example, as shown in FIG. 2, the adder 21 of the adder 4 stores the 8-bit values of the registers A and B and the register CR inputted at the time T.
The sum of the 1-bit values of Y is calculated, and at time T + 1, the lower 1 bit (LSL) of the 9-bit calculation result
The value of B) is output to the register CRY, and the upper 8 bits of the operation result are output to the register C.

Next, the operation of the information processing apparatus shown in FIG. 1 when calculating the average value of two 8-bit data as an integer (considering rounding) will be described. As shown in FIG. 3, the average value C of two 8-bit data A and B is calculated.
Is calculated by the following equation. C = (A + B + 1) >> 1 (1)

Here, X >> m indicates that the integer (binary number) X is shifted to the LSB side by m bits. That is, if X is a multiple of 2 ^m , X >> m becomes X
/ 2 ^m .

First, the control circuit 1 stores the value 1 (value for rounding) in the register CRY.

Next, the control circuit 1 calculates the 8-bit value A (= {A ₇ ,..., A ₀ }) of the register A,
The bit value B (= {B ₇ ,..., B ₀ }) and the 1-bit value 1 of the register CRY are output to the adder 21.

Then, as shown in FIG. 4, the adder 21 calculates the sum of the values (A + B + 1) and calculates the value of the lower 1 bit (LSB) of the 9-bit operation result (CRYC in FIG. 4). ) To the register CRY, and the value of the upper 8 bits ({C ₇ ,..., C ₀ } in the figure)
As an average value C to the register C.

As described above, the adder circuit 4 calculates the average value of the 8-bit values stored in the registers A and B as an integer and stores the calculated value in the register C. In addition, the bit width of the transmission path between the registers A to C of the register file 11 and the adder 21 is all sufficient to be 8 bits.

Next, the operation of the information processing apparatus shown in FIG. 1 when calculating the average value of four 8-bit data as an integer will be described. In addition, as shown in FIG.
The average value G of the bit data A to D is calculated by the following equation. G = (A + B + C + D + 2) >> 2 (2)

First, in the first cycle, the control circuit 1 stores the value 1 (1 of the rounding value 2) in the register CRY.

Next, the control circuit 1 calculates the 8-bit value A (= {A ₇ ,..., A ₀ }) of the register A,
The bit value B (= {B ₇ ,..., B ₀ }) and the 1-bit value 1 of the register CRY are output to the adder 21.

Then, as shown in FIG. 6, the adder 21 calculates the sum (A + B + 1) of the values, and calculates the value of the lower 1 bit (LSB) of the 9-bit calculation result (CRYE in FIG. 6). ) Is output to the register CRY, and the value of the upper 8 bits ({E ₇ ,..., E ₀ } in the figure)
Is output to the register E. Note that the value of the upper 8 bits $ E
_7, · · ·, E _0} is expressed by the following equation. 2 × {E ₇ ,..., E ₀ } + CRYE = A + B + 1 (3)

Next, in the second cycle, the control circuit 1 sets the 8-bit value C (= {C ₇ ,.
.., C ₀ }), the 8-bit value D (=
{D ₇ ,..., D ₀ }) and 1 of the register CRY
Bit value (the LSB value of the previous operation result, ie, CR
YE) is output to the adding element 21.

Then, as shown in FIG. 7, the adding element 21 calculates the sum of the values (C + D + CRYE),
The value of the lower 1 bit (LSB) of the 9-bit operation result (CRYF in the figure) is output to the register CRY, and the value of the upper 8 bits ($ F ₇ ,...,.
F ₀ }) is output to the register F. The value of the upper 8 bits {F ₇ ,..., F ₀ } is represented by the following equation. 2 × {F ₇ ,..., F ₀ } + CRYF = C + D + CRYE (4)

Next, in the third cycle, the control circuit 1 sets the 8-bit value E (= {E ₇ ,.
.., E ₀ }), the 8-bit value F (=
{F ₇ ,..., F ₀ }) and 1 of the register CRY
Bit value (the LSB value of the previous operation result, ie, CR
YF) is output to the adding element 21.

Then, as shown in FIG. 8, the adder 21 calculates the sum of the values (E + F + CRYF),
The value of the lower 1 bit (LSB) of the 9-bit operation result (CRYG in the figure) is output to the register CRY, and the value of the upper 8 bits ($ G ₇ ,...,.
G ₀ }) is output to the register G as the average value G. Note that the value of the upper 8 bits {G ₇ ,..., G ₀ } is represented by the following equation. 2 × {G ₇ ,..., G ₀ } + CRYG = E + F + CRYF (5)

The values {E ₇ ,..., E ₀ } and the values {F ₇ ,..., F ₀ } are the higher order of the sum of the values A, B, 1 or the sum of the values C, D, CRYE. An 8-bit value, C
RYF is the LSB value of the sum of the values C, D, and CRYE. Also, as shown in FIG. 9, increasing CRYF by one digit and further adding a value NOTF obtained by inverting CRYF is equivalent to adding 1 to CRYF as shown in the following equation. Further, since the value NOTF does not affect rounding, raising CRYF by one digit will
This is substantially equivalent to adding 1 to YF. 2 × CRYF + NOTF = CRYF + 1 (6)

Therefore, in the calculation of the sum of the values E, F and CRYF, by adding CRYF at the same digit as E ₀ and F ₀ , the remaining one of the rounding values is implicitly added. It will be.

Next, the value {G ₇ ,
.., G ₀ } are the average values of A to D.

First, the following equation is derived from equations (3), (4), and (6). 2 × (E + F + CRYF) + NOTF = A + B + C + D + 2 (7)

Further, when the values on both sides of the equation (7) are shifted by one bit toward the LSB, the following equation is derived. E + F + CRYF = (A + B + C + D + 2) >> 1 (8)

Further, the values on both sides of the equation (5) are set to 1 on the LSB side.
Shifting by bits leads to the relationship: {G ₇ ,..., G ₀ } = (E + F + CRYF) >> 1 (9)

Therefore, from the expressions (8) and (9), the value {G ₇ ,..., G ₀ } output to the register G is expressed by the data A, B, C , D (Expression (2)). {G ₇ ,..., G ₀ } = ((A + B + C + D + 2) >> 1) >> 1 = (A + B + C + D + 2) >> 2 (10)

As described above, the average value of the four 8-bit data A, B, C, and D is calculated as an integer in three cycles and output to the register G. In addition, the bit width of the transmission path between the registers A to G of the register file 11 and the adder 21 is all eight bits.

Next, the operation of the information processing apparatus shown in FIG. 1 when calculating the average value of eight 8-bit data as an integer will be described. As shown in FIG. 10, the average value Q of eight 8-bit data A to H is calculated by the following equation. Q = (A + B + C + D + E + F + G + H + 4) >> 3 (11)

First, in the first cycle, the control circuit 1 stores the value 1 (1 of the rounding value 4) in the register CRY.

Next, the control circuit 1 calculates the 8-bit value A (= {A ₇ ,..., A ₀ }) of the register A,
The bit value B (= {B ₇ ,..., B ₀ }) and the 1-bit value 1 of the register CRY are output to the adder 21.

Then, as shown in FIG. 11, the adder 21 calculates the sum (A + B + 1) of those values, and calculates the value of the lower 1 bit (LSB) of the 9-bit calculation result (CRYJ in FIG. 11). ) Is output to the register CRY, and the value of the upper 8 bits ({J ₇ ,...,.
J ₀ }) is output to the register J. Incidentally, the upper 8 bits of the value _{{J 7, ···, J 0} } is expressed by the following equation. 2 × {J ₇ ,..., J ₀ } + CRYJ = A + B + 1 (12)

Next, in the second cycle, the control circuit 1 sets the 8-bit value C (= {C ₇ ,.
.., C ₀ }), the 8-bit value D (=
{D ₇ ,..., D ₀ }) and 1 of the register CRY
Bit value (the LSB value of the previous operation result, ie, CR
YJ) is output to the adding element 21.

Then, as shown in FIG. 12, the adder 21 calculates the sum of the values (C + D + CRYJ), and outputs the lower 1 bit (LSL) of the 9-bit operation result.
The value of B) a (CRYK in the figure), and outputs to the register CRY, higher 8-bit value (in FIG {K _7, · ·
, K ₀ }) to the register K. The value of the upper 8 bits {K ₇ ,..., K ₀ } is represented by the following equation. 2 × {K ₇ ,..., K ₀ } + CRYK = C + D + CRYJ (13)

Next, in the third cycle, the control circuit 1 sets the 8-bit value E (= {E ₇ ,.
.., E ₀ }), the 8-bit value F (=
{F ₇ ,..., F ₀ }) and 1 of the register CRY
Bit value (the LSB value of the previous operation result, ie, CR
YK) is output to the adding element 21.

Then, as shown in FIG. 13, the adder 21 calculates the sum of the values (E + F + CRYK), and outputs the lower 1 bit (LSL) of the 9-bit operation result.
B) (CRYL in the figure) is output to the register CRY, and the value of the upper 8 bits (｛L ₇ ,.
, L ₀ }) to the register L. The value of the upper 8 bits {L ₇ ,..., L ₀ } is expressed by the following equation. 2 × {L ₇ ,..., L ₀ } + CRYL = E + F + CRYK (14)

Next, in the fourth cycle, the control circuit 1 sets the 8-bit value G (= {G ₇ ,.
···, G ₀ }), 8-bit value H (=
{H ₇ ,..., H ₀ }) and 1 of the register CRY
Bit value (the LSB value of the previous operation result, ie, CR
YL) is output to the adding element 21.

Then, as shown in FIG. 14, the adder 21 calculates the sum (G + H + CRYL) of those values, and outputs the lower 1 bit (LSL) of the 9-bit operation result.
B) (CRYM in the figure) is output to the register CRY, and the value of the upper 8 bits ({M ₇ ,...
, M ₀ }) to the register M. The value of the upper 8 bits {M ₇ ,..., M ₀ } is expressed by the following equation. 2 × {M ₇ ,..., M ₀ } + CRYM = G + H + CRYL (15)

Next, in the fifth cycle, the control circuit 1 sets the 8-bit value J (= {J ₇ ,.
.., J ₀ }, 8-bit value K of register K (=
{K ₇ ,..., K ₀ }) and 1 of the register CRY
Bit value (the LSB value of the previous operation result, ie, CR
YM) is output to the adding element 21.

Then, as shown in FIG. 15, the adding element 21 calculates the sum (J + K + CRYM) of those values, and outputs the lower 1 bit (LSL) of the 9-bit operation result.
B) (CRYN in the figure) is output to the register CRY, and the value of the upper 8 bits ({N ₇ ,...
, N ₀ }) to the register N. The value of the upper 8 bits {N ₇ ,..., N ₀ } is expressed by the following equation. 2 × {N ₇ ,..., N ₀ } + CRYN = J + K + CRYM (16)

The values {J ₇ ,..., J ₀ } and the values {K ₇ ,..., K ₀ } are the higher order of the sum of the values A, B, 1 or the sum of the values C, D, CRYJ. An 8-bit value, C
RYM is the LSB value of the sum of the values G, H, and CRYL. In addition, as shown in FIG. 16, increasing CRYM by one digit and adding a value NOTM obtained by inverting CRYM is equivalent to adding 1 to CRYM as shown in the following equation. Further, since the value NOTM does not affect rounding, raising CRYM by one digit is
This is substantially equivalent to adding 1 to RYM. 2 × CRYM + NOTM = CRYM + 1 (17)

Therefore, in calculating the sum of the values J, K, and CRYM, CRYM (the value of the 0th bit) is added at the same digit (the 1st bit) as J ₀ and K ₀ , so that This means that 1 of the rounding value 4 has been added.

Next, in the sixth cycle, the control circuit 1 sets the 8-bit value L (= {L ₇ ,.
···, L ₀ }), 8-bit value M of register K (=
{M ₇ ,..., M ₀ }) and 1 of the register CRY
Bit value (the LSB value of the previous operation result, ie, CR
YN) is output to the adding element 21.

Then, as shown in FIG. 17, the adding element 21 calculates the sum of the values (L + M + CRYN), and outputs the lower 1 bit (LSL) of the 9-bit operation result.
B) (CRYP in the figure) is output to the register CRY, and the value of the upper 8 bits ($ P ₇ ,.
, P ₀ }) to the register P. The value of the upper 8 bits {P ₇ ,..., P ₀ } is represented by the following equation. 2 × {P ₇ ,..., P ₀ } + CRYP = L + M + CRYN (18)

Next, in the seventh cycle, the control circuit 1 sets the 8-bit value N (= {N ₇ ,.
.., N ₀ }), 8-bit value P (=
{P ₇ ,..., P ₀ }) and 1 of the register CRY
Bit value (the LSB value of the previous operation result, ie, CR
YP) is output to the adding element 21.

Then, as shown in FIG. 18, the adding element 21 calculates the sum of the values (N + P + CRYP), and outputs the lower 1 bit (LSL) of the 9-bit operation result.
The value of B) a (CRYQ in the figure), and outputs to the register CRY, higher 8-bit value (in FIG. {Q _7, · ·
, Q ₀ }) to the register Q as the average value Q.
Note that the value of the upper 8 bits {Q ₇ ,..., Q ₀ } is represented by the following equation. 2 × {Q ₇ ,..., Q ₀ } + CRYQ = N + P + CRYP (19)

The values {N ₇ ,..., N ₀ } and the values {P ₇ ,..., P ₀ } are the higher order of the sum of the values J, K, CRYM or the sum of the values L, M, CRYN. This is an 8-bit value, and CRYP is the LSB value of the sum of the values L, M, and CRYN. Further, as shown in FIG. 19, adding CRYP by one digit and adding a value NOTP obtained by inverting CRYP is equivalent to adding 1 to CRYP as shown in the following equation. CRYP which is 1-bit value
By adding 1 to the sum of the data A to H is 2 (=
It is equivalent to adding {1, 0}). Furthermore, the value NOTP does not affect rounding, so CRYP is set to 1
Carrying up is substantially equivalent to adding 1 to CRYP. 2 × CRYP + NOTP = CRYP + 1 (20)

Therefore, in calculating the sum of the values N, P, and CRYP, CRYP (first bit) is added at the same digit (second bit) as N ₀ , P ₀ , thereby implicitly adding The remaining 2 of the values 4 have been added.

Next, the value {Q ₇ ,
.., Q ₀ } are average values of A to H.

First, equations (12) to (15) and (17)
Thus, the following relationship is derived. 2 × (J + K + L + M + CRYM + 1) + NOTM = A + B + C + D + E + F + G + H + 4 (21)

Further, when the values on both sides of the equation (21) are shifted by one bit toward the LSB, the following equation is derived. J + K + L + M + CRYM + 1 = (A + B + C + D + E + F + G + H + 4) >> 1 (22)

From the equations (16), (18) and (20), the following equation is derived. 2 × (N + P + CRYP) + NOTP = J + K + L + M + CRYM + 1 (23)

Further, when the values on both sides of equation (23) are shifted by one bit toward the LSB, the following equation is derived. N + P + CRYP = (J + K + L + M + CRYM + 1) >> 1 (24)

When the values on both sides of the equation (19) are shifted by one bit toward the LSB, the following equation is derived. {Q ₇ ,..., Q ₀ } = (N + P + CRYP) >> 1 (25)

Therefore, equations (22), (24) and (25)
More, the output value in the register _{Q {Q 7, ···, Q} 0}
Is the average value Q of the data A to H as expressed by the following equation.
(Expression (11)) is found. {Q ₇ ,..., Q ₀ } = (((A + B + C + D + E + F + G + H + 4) >> 1) >> 1) >> 1 = (A + B + C + D + E + F + G + H + 4) >> 3 (26)

As described above, the average value of eight 8-bit data A to H is calculated in seven cycles as an integer Q, and output to the register Q. In addition, the bit width of the transmission path between the registers A to Q of the register file 11 and the adder 21 is all sufficient to be 8 bits.

The control circuit 1 outputs the average value calculated as described above to a predetermined device via the interface 3, for example.

Further, in the above embodiment, the average value of the data is calculated when the number of data is 2, 4, or 8, but of course, 2 ^N (N is ,
It is also possible to calculate the average value of the data of (4 or more integers). Even in that case, the bit width of the transmission path between the register of the register file 11 and the adder 21 is
All 8 bits are sufficient.

FIG. 20 shows the configuration of an information processing apparatus according to a second embodiment of the present invention. The control circuit 1, the memory 2, and the interface 3 are the same as those in the first embodiment shown in FIG.

Adder circuit 41-i (i = 1,..., 4)
Of the two 32-bit values supplied from the predetermined two 32-bit registers of the register file 42, respectively.
The sum of 8 bits from (1) × 8) to the (i × 8-1) th bit and the value of 1 bit supplied from the 1-bit register 62-i (storage means) is calculated, and a 9-bit operation is performed. The value of the lower 1 bit (LSB) of the result is stored in the register 62-i.
And outputs the value of the upper 8 bits to the register file 42.
In the 32-bit register of any one of the above, the ((i−1) × 8) th to (i × th) bits of the 32-bit data are stored.
8-1) Output as bit data.

The register file 42 has 32 (= 8 ×
4) It has bit registers AA, BB, CC and a plurality of 32-bit registers (not shown). Each register holds four 8-bit data.

Next, as an example of the operation for calculating the average value, four 8-bit data stored in the register AA and four 8-bit data stored in the register BB corresponding to the data are described. The operation of the information processing apparatus shown in FIG. 20 when calculating the average values of.

In the 0th to 7th bits of the register AA, 8-bit data A ₁ (= ｛A ₁₇ ,...,
A ₁₀ }) are stored, and 8-bit data A ₂ (= {A} is stored in the eighth to fifteenth bits of the register AA.
₂₇ ,..., A ₂₀ ｝) are stored. Similarly, 8-bit data A ₃ (= {A ₃₇ ,..., A ₃₀ }) is stored in the 16th to 23rd bits of the register AA, and the 24th to 24th bits of the register AA are stored. In 31 bits, 8-bit data A ₄ (= ｛A ₄₇ ,..., A
₄₀ ｝) is stored.

On the other hand, the 0th to 7th bits of the register BB
The bits include 8-bit data B ₁ (= {B ₁₇ ,..., B
₁₀ }) is stored, and 8-bit data B ₂ (= 8 bits) is stored in the eighth to fifteenth bits of the register BB.
{B ₂₇ ,..., B ₂₀ }) are stored. Similarly,
8 to the 16th to 23rd bits of the register BB
Bit data B ₃ (= {B ₃₇ ,..., B ₃₀ }) is stored, and the 24th to 31st bits of the register BB are stored.
The bits include 8-bit data B ₄ (= ｛B ₄₇ ,...)
・, B ₄₀ ｝) are stored.

Then, the average value C _i of the data A _{i of the} register AA and the data B _i of the register BB (= (A _i + B _i +1))
>> 1) (i = 1,..., 4) is added to the adder circuit 41-i
Respectively.

First, the control circuit 1 includes an adder circuit 41-1.
1 to the registers 62-1 to 62-4 of
(Value for rounding).

Next, the control circuit 1 sets the value of the register AA to 32.
Of bit value, the data A ₁ of 8 bits of the 0th bit to the seventh bit, is output to the adding circuit 41-1, 8
Of 8-bit bit to the 15 bit data A _2, it is output to the adder circuit 41-2. Similarly, the control circuit 1
Of 32-bit value in the register AA, the data A ₃ of 8 bits of the 16 bit to the 23 bit adder circuit 4
1-3, and outputs the 24th to 31st bit 8
Bit data A _4, is output to the adder circuit 41-4.

Further, the control circuit 1 controls the register BB
Of the two-bit value, the data B ₁ of 8 bits of the 0th bit to the seventh bit, is output to the adding circuit 41-1, the 8 bits of the 8-bit to 15-bit data B _2,
The signal is output to the addition circuit 41-2. Similarly, the control circuit 1
Among the 32-bit value in the register BB, the data B ₃ of 8 bits of the 16 bit to the 23 bit, is output to the adding circuit 41-3, the 24th bit to the data B of 8 bits of the 31 bit ₄ is output to the adding circuit 41-4.

Then, the adding element 61 of the adding circuit 41-1
-1 indicates the supplied data A ₁ , B ₁ and the register 62−
1 to calculate the sum (A ₁ + B ₁ +1) of the values 1 stored therein, and calculate the lower 1 bit (LSL) of the 9-bit operation result.
B) is output to the register 62-1 and the upper 8 bits {C ₁₇ ,..., C ₁₀ } are converted to data A ₁ ,
The average value C ₁ of B ₁ is output to the 0th to 7th bits of the register CC.

In parallel with the addition circuit 41-1, the addition circuit 4
1-2 adder element 61-2 outputs the supplied data A ₂ ,
And B _2, the sum of the value 1 stored in the register 62-2 and (A ₂ + B ₂ +1) is calculated, the lower 1 bit value (LSB) of the 9-bit result, the register 62-2 And the value of the upper 8 bits {C ₂₇ ,.
C ₂₀ } as the average value C ₂ of the data A ₂ and B ₂
It outputs to the 8th to 15th bits of C.

Similarly, in parallel with the addition circuit 41-1, the addition element 61-3 of the addition circuit 41-3 stores the supplied data A ₃ and B ₃ and the value stored in the register 63-3. 1
Sum of (A ₃ + B ₃ +1) is calculated, and the lower 1 bit value (LSB) of the 9-bit result, the register 63
-3, and the value of the upper 8 bits {C _37,.
..., and outputs the C _30} as the average value C ₃ of the data A _3, B ₃ to the 16 bit to the 23 bit register CC.

Further, in parallel with the adding circuit 41-1, the adding element 61-4 of the adding circuit 41-4 stores the supplied data A ₄ and B ₄ and the value 1 stored in the register 64-4.
(A ₄ + B ₄ +1), and stores the value of the lower 1 bit (LSB) of the 9-bit operation result in the register 64
-4, and the value of the upper 8 bits {C _47,.
.., C ₄₀ } are output as the average value C ₄ of the data A ₄ and B ₄ to the 24th to 31st bits of the register CC.

As described above, the adders 41-1 to 41-4 calculate the average values of the 8-bit data stored in the registers AA and BB as integers and store the calculated values in the register CC. Thus, 4
By using the adders 41-1 through 41-4 in parallel, four average values can be calculated in one cycle.

In the second embodiment, four adder circuits 41-1 to 41-4 are used.
By using the adders 41-1 to 41-N, N average values can be calculated in one cycle.

In the first and second embodiments, the average value of 8-bit data is calculated. However, the average value of data having another number of bits may be calculated. In that case, the transmission path between the register of the register file and the addition element only needs to have a bit width corresponding to the number of bits of the data.

[0095]

As described above, according to the information processing apparatus according to the first aspect and the information processing method according to the fourth aspect,
A plurality of data of the first number of bits and data of the second number of bits stored in the predetermined storage unit are added, and lower-order data of the second number of bits of the operation result are stored in the predetermined storage unit. Since the remaining higher-order data of the operation result is output, the processing can be performed on the transmission path having the same bit width as the number of bits of the first data and the calculated average value.

According to the information processing apparatus according to the fifth aspect and the information processing method according to the eighth aspect, the first to Nth sets of data having a plurality of first bits and N predetermined bits are provided. Are added to the first to Nth data of the second number of bits respectively stored in the storage units, and the lower-order data of the second number of bits of each operation result is stored in N predetermined storage units. Since the data is stored and the remaining higher-order data of each operation result is output, processing can be performed on the transmission path having the same bit width as the initial data and the number of bits of the calculated average value, and in one cycle, An average value of N pieces can be calculated.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a first embodiment of an information processing apparatus according to the present invention.

FIG. 2 is a diagram illustrating an example of a relationship between an input and an output of an adding element 21 in FIG. 1;

FIG. 3 is a diagram illustrating an example of an operation performed when calculating an average value of two 8-bit data.

4 is a diagram illustrating an example of a relationship between an input and an output of an adder 21 in FIG. 1 when calculating an average value of two 8-bit data.

FIG. 5 is a diagram illustrating an example of an operation performed when calculating an average value of four 8-bit data.

FIG. 6 is a diagram illustrating an example of an operation performed in a first cycle when calculating an average value of four 8-bit data.

FIG. 7 is a diagram illustrating an example of an operation performed in a second cycle when calculating an average value of four 8-bit data.

FIG. 8 is a diagram illustrating an example of an operation performed in a third cycle when calculating an average value of four 8-bit data.

FIG. 9 is a diagram illustrating an example of moving up the value of a register CRY.

FIG. 10 is a diagram illustrating an example of an operation performed when calculating an average value of eight 8-bit data.

FIG. 11 is a diagram illustrating an example of an operation performed in a first cycle when calculating an average value of eight 8-bit data.

FIG. 12 is a diagram illustrating an example of an operation performed in a second cycle when calculating an average value of eight 8-bit data.

FIG. 13 is a diagram illustrating an example of an operation performed in a third cycle when calculating an average value of eight 8-bit data.

FIG. 14 is a diagram illustrating an example of an operation performed in a fourth cycle when calculating an average value of eight 8-bit data.

FIG. 15 is a diagram illustrating an example of an operation performed in a fifth cycle when calculating an average value of eight 8-bit data.

FIG. 16 is a diagram illustrating another example of moving up the value of a register CRY.

FIG. 17 is a diagram illustrating an example of an operation performed in a sixth cycle when calculating an average value of eight 8-bit data.

FIG. 18 is a diagram illustrating an example of an operation performed in a seventh cycle when calculating an average value of eight 8-bit data.

FIG. 19 is a diagram illustrating still another example of incrementing the value of register CRY.

FIG. 20 is a block diagram illustrating a configuration of an information processing apparatus according to a second embodiment of the present invention.

[Explanation of symbols]

1 control circuit, 2 memories, 3 interfaces,
4 adder circuit, 11 register file, 21
Addition element, 41-1 to 41-4 addition circuit, 42
Register file, 61-1 to 61-4 Additive element, 62-1 to 62-4 Register

Claims (8)

[Claims] A storage means for storing data of a first number of bits; a plurality of data of a second number of bits; and a data of the first number of bits stored by the storage means,
An information processing apparatus comprising: an addition unit that stores lower-order data of the first number of bits of an operation result in the storage unit and outputs remaining upper-order data of the operation result. 2. The storage device according to claim 1, wherein the storage unit stores, as the data of the first bit number, a value supplied from the addition unit or a value supplied from a predetermined circuit. An information processing apparatus according to claim 1. 3. The information processing apparatus according to claim 1, wherein the remaining higher-order data of the operation result output by the adding unit is an average value of the data of the plurality of second bits. apparatus. 4. A method of adding data of a plurality of first bits and data of a second number of bits stored in a predetermined storage unit to obtain lower-order data of the second number of bits of an operation result. An information processing method, comprising the step of storing the data in a predetermined storage unit and outputting the remaining higher-order data of the operation result. 5. An information processing apparatus for processing a plurality of N sets of data in parallel, comprising: N storage units for storing first to N-th data of a first bit number, respectively; N sets of data having a plurality of second bits and first to N-th data having the first number of bits stored by the storage means are added, and the first data of each operation result is added. An information processing apparatus, comprising: N number of adding means for respectively storing lower-order data of the number of bits in the storage means and outputting the remaining higher-order data of each operation result. 6. The N storage means, wherein the value of the first number of bits is supplied from the adding means,
6. The information processing apparatus according to claim 5, wherein values supplied from a predetermined circuit are stored. 7. The method according to claim 1, wherein the remaining higher-order data of the operation result output by the adding means is an average value of the data of the plurality of second bits corresponding to the adding means. 6. The information processing apparatus according to 5. 8. An information processing method for processing a plurality of N sets of data in parallel, wherein the first to N-th sets of data having a plurality of first bits are respectively stored in N predetermined storage units. Second memorized
The first to Nth data of the number of bits of
Storing the lower-order data of the second number of bits of each operation result in each of the N predetermined storage units and outputting the remaining upper-order data of each operation result. Processing method.