JP4313555B2 - Galois field multiplier and communication device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a Galois field multiplier and a communication device.
[0002]
[Prior art]
One communication device is a router that connects different internetworks to each other. The router extracts the connection destination address in the input data, and searches the routing table for the next connected router from the extracted address. When the next connected router is found from the extracted address using the routing table, the router outputs data to the next router.
[0003]
By the way, when searching the next connected router from the address data from the routing table, hash search is generally employed.
[0004]
In the hash search, the hash value of each search data is calculated in advance. The hash value is a hash value obtained by dividing the search data by an appropriate prime number. Since search data of different data series may have the same hash value, each search data is classified into a group for each hash value. That is, search data having the same hash value is classified into the same group.
[0005]
And a hash value is calculated | required about to-be-searched data. From the obtained hash value, it is specified to which group of the classified groups the searched data belongs. In the hash search, search data that matches the search target data is searched from the search data in the specified group.
[0006]
FIG. 4 is an explanatory diagram for explaining the hash search. In FIG. 4, a search data table TD is a set of m search data DS composed of n bytes, and is a grouped table by calculating hash values in advance. This grouping forms a list by sequentially linking the next candidates in the group by the next pointer P in each search data block DB. The pointer P of the last list of each group is set to “0”.
[0007]
The pointer P of the first search data block DB of each group is written in the search tag table TT. In the search tag table TT, the pointer P of the first search data block DB of each group of the search data table TD corresponding to the hash value HT is written with the hash value HT as an index number (address).
[0008]
When n bytes of data to be searched DX are input as input data, a hash value HT of the n bytes of data to be searched DX is calculated. Using the calculated hash value HT as an index of the search data table TD, the head pointer P of the search data DS of the group that matches the hash value HT is obtained from the search tag table TT. Based on the acquired leading pointer P, search data DS belonging to the group is searched.
[0009]
If the search data DS belonging to the group matches the searched data DX, the search is matched and the search is terminated.
[0010]
As described above, in the hash search, the remainder obtained by dividing the search target data HT by the prime number of a predetermined number of digits is used as the hash value, so that the number of search candidates can be reduced, the number of searches can be reduced, and the search time can be shortened. Excellent in terms.
[0011]
Incidentally, in this hash search, there is a method of using CRC (Cyclic Redundancy Check) calculation instead of the division. This is because the CRC calculation corresponds to the division of the bit sequence, and thus exhibits the same properties as the division. Therefore, since the communication apparatus includes a CRC encoder used for error correction, a hash search using this CRC encoder is performed.
[0012]
By the way, when the hash search is actually performed, the search target data DX is included in a part of input data (communication frame) including a plurality of data fields. Therefore, it is necessary to calculate a CRC value (hash value) of the portion of the searched data DX.
[0013]
For example, as shown in FIG. 5, for n-bit input data D, the data D1 in the area from the first bit (LSB) to the (k1-1) th bit and the last bit from the (k2 + 1) th bit counted from the first bit The data D2 in the area up to (MSB) is assumed to be searched data DX. When obtaining the CRC value (hash value) of the search target data DX, calculation is performed as follows using the linearity of the CRC.
[0014]
First, a CRC value (hash value) for n-bit input data D is calculated. Also, the CRC value (hash value) of the data D3 in the area (mask area) from the k1th bit to the k2th bit is obtained. At this time, the CRC value of the data D of n bits (all areas) is set to CRCn, the CRC value of the data D3 of the mask area from the k1th bit to the k2th bit is set to CRCm, and the CRC value (hash) of the searched data DX When the value is CRCx, it can be obtained by the following calculation.
[0015]
CRCx = (CRCn) XOR (CRCm)
However, "XOR" is exclusive OR
At this time, the CRC value (= CRCm) of the data D3 is calculated by the CRC encoder. Since the data is “0” from the first bit to the (k1-1) th bit, there is no need to perform CRC calculation. Immediately, the k1th bit data is input to perform CRC calculation. However, even when the CRC calculation is performed up to the k2th bit, it is necessary to perform the CRC calculation by subsequently inputting data “0” from the (k2 + 1) bit to the last bit. Even if the data is “0”, the same amount of computation as that of normal data is required, and there is a problem that it takes time to calculate CRCm.
[0016]
Therefore, the value when “0” from the (k2 + 1) th bit to the last bit is input to the CRC value in the middle from the k1 bit to the k2 bit is calculated in advance. Then, it is conceivable to form a table of the results calculated for various intermediate CRC values and obtain the CRC value (= CRCm) of the data D3 in the mask area using the table. However, although this method can increase the speed, for example, when the number of bits in the mask area is large, the number of patterns becomes enormous and a large data table is required.
[0017]
Furthermore, using the principle of multiplication of Galois fields, that is, in the Galois encoder, shifting one is the same as multiplying one element of the Galois field, so the number of orders of Galois of “0” number. It is known that a field element can be calculated by multiplying it. When the number of bits in the mask area is fixed and the number of “0” is also fixed, it is advantageous in that it can be dealt with by preparing only one Galois field element.
[0018]
Galois field GF (2^r) Is a set of finite numbers having a calculation rule, and when r = 4, the number of elements (prime numbers) of the Galois field is 16 (= 2)^r) It becomes a piece. And each non-zero element is
α⁰, Α¹, Α², Α^Three, …………………, α¹⁴
It is represented by Each original value has a one-to-one correspondence with an integer of 1 to 15.
[0019]
The Galois field completes all four arithmetic operations including multiplication and division. For example, α²× α^Three= Α^FiveOr α^Ten× α⁹= Α¹⁹= Α^FourIt becomes. Α^Four4 is the remainder when 19 is divided by 15. Further, addition and subtraction can be performed by exclusive OR (XOR) of vector expressions.
[0020]
An example of Galois field multiplication will be described below. For example, α which is an element (element) of Galois field⁶And α⁷The product (multiplication) can be expanded as follows.
[0021]
α⁶× α⁷= (Α^Three+ Α²) X (α^Three+ Α¹+ Α⁰)
= Α⁶+ Α^Four+ Α^Three+ Α^Five+ Α^Three+ Α²
= Α⁶+ Α^Four+ Α^Five+ Α²
= Α^Three+ Α²+ Α¹+ Α⁰+ Α²+ Α¹+ Α²
= Α¹³= Α^{(6 + 7)}
FIG. 6 shows a logic circuit showing an example of the Galois multiplier. The Galois field multiplier shown in FIG. 6 includes a first arithmetic unit 51 that performs multiplication of bit pattern combinations, that is, a product (AND) calculation, and a bit about the arithmetic result obtained by the first arithmetic unit 51. And a second arithmetic unit 52 that performs an exclusive OR (XOR) calculation of units.
[0022]
When calculating the CRC value (= CRCm) of the data D3 in the mask area shown in FIG. 5 using this multiplier, the first register 53 calculates the data D3 from the k1 bit to the k2 bit. An N-bit bit string Di composed of Galois field elements, which is a CRC value during the calculation, is input. On the other hand, an N-bit bit string Sj indicating a Galois field element of degree “0” from the (k2 + 1) -th bit to the last bit is input to the second register 54.
[0023]
The bit string Di input to the first register 53 and the bit string Sj input to the second register 54 are output to the first arithmetic unit 51. In many AND gate circuits 51 a provided in the first arithmetic unit 51, AND calculation is performed on each bit of the bit string Sj for each bit of the bit string Di. At this time, as many AND gate circuits 51a as the number of combinations are provided so that calculation of each combination can be executed simultaneously. The result obtained by each AND gate circuit 51 a of the first calculation unit 51 is output to the second calculation unit 52. The second arithmetic unit 52 includes a large number of exclusive OR gate circuits (XOR circuits) 52a, and the XOR circuit 52a performs exclusive OR for all the bit patterns, and outputs the data D3 to the output register 55. A CRC value (= CRCm) is output.
[0024]
However, although the calculation speed is high, the number of all combinations (N²And the AND gate circuit 51a is required, and the circuit scale becomes very large.
[0025]
FIG. 7 shows a Galois multiplier that can be configured with a small circuit scale. In FIG. 7, this Galois multiplier includes an input register 61, a shift register 62, an AND gate circuit 63, an exclusive OR gate circuit 64, and a Galois encoder 65.
[0026]
Now, with the Galois encoder register 53a of the Galois encoder 65 initialized to "0", the input register 61 calculates the data D3 from the k1 bit to the k2 bit in the mask area shown in FIG. An N-bit bit string Di composed of Galois field elements, which is a CRC value during the calculation, is input. In addition, an N-bit bit string Sj indicating an element of a Galois field of the order of “0” from the (k2 + 1) th bit to the last bit is input to the shift register 62.
[0027]
When the most significant bit (MSB) of the shift register 62 is “1”, the exclusive OR gate circuit 64 excludes the contents of the input register 61 (bit string Di) and the contents g of the Galois encoder register 65a. Logical OR calculation, that is,
g = gXOR (Di × (MSB of shift register 62))
However, "x" is multiplication (Di operation with each bit of Di)
And the result is input to the Galois encoder 65.
[0028]
Then, the content g of the Galois encoder register 65a is shifted one bit to the right (most significant side) once. Similarly, the contents of the shift register 62 (bit string Sj) are also shifted to the right once. Then, by shifting the contents of the shift register 62 one bit to the right once, if the new MSB of the shift register 62 is “1”, the contents of the input register 61 and the contents of the Galois encoder register 65a g and the exclusive OR, ie,
g = gXOR (Di × (MSB of shift register 62))
And the result is input to the Galois encoder 65. Then, the contents of the Galois encoder 65 are shifted one bit to the right (most significant side) once, and the shift register 62 is similarly shifted one bit to the right once.
[0029]
This calculation is repeated until the least significant bit (LSB) bit becomes the MSB when the shift register 62 is initially set and the above calculation is performed.
[0030]
Finally, the content g of the Galois encoder register 65a obtained by the Galois encoder 65, that is,
g = gXOR (Dj × (MSB of shift register 62))
Is output as the CRC value (= CRCm) of the data D3.
[0031]
Although this Galois multiplier is inferior to the Galois multiplier described in FIG. 6 by the maximum (N-1) shift operations, the circuit speed can be greatly reduced.
[0032]
[Problems to be solved by the invention]
In this way, the CRC value (= CRCm) can be obtained using a Galois encoder, but if the CRC encoder inputs “0” and shifts it to the right once, it is the same as the Galois encoder. Therefore, the Galois encoder can be replaced with a CRC encoder.
[0033]
However, each time the Galois encoder 65 shifts one bit to the right, it must initialize the encoder. Normally, the CRC encoder is generally not used as it is because it is generally shifted in N-bit units (or 8-bit units) while inputting data after initializing the register. .
[0034]
The present invention has been made to solve the above problems, and an object of the present invention is to provide a Galois field multiplier and a communication device capable of reducing the circuit scale by enabling Galois multiplication using a CRC encoder. It is in.
[0035]
[Means for Solving the Problems]
The invention according to claim 1 is an N-bit first bit string composed of Galois field elements input to the first register, and an N-bit second bit string composed of Galois field elements input to the second register; In a Galois multiplier for performing Galois field multiplication, a shift register that shifts 1 bit to the most significant bit side while inputting the result of exclusive OR calculation of N bits and outputting the most significant bit at that time, and the N bits An AND gate circuit for sequentially multiplying the N bit first bit string one bit at a time from the most significant bit of the second bit string, an operation result from the AND gate circuit, and the contents of the shift register A first exclusive OR gate circuit that performs an exclusive OR calculation between the shift registers and inputs the calculation result to the shift register; A CRC encoder that sequentially inputs the order bits and performs a CRC operation, and a second exclusive OR gate circuit that performs an exclusive OR calculation between the contents of the CRC encoder and the contents of the shift register. Is the gist.
[0036]
According to a second aspect of the present invention, there is provided an N-bit first bit string composed of Galois field elements input to the first register, and an N-bit second bit string composed of Galois field elements input to the second register. In the Galois field multiplier for performing the Galois field multiplication, the first circuit unit for multiplying the first bit string of N bits for each bit of the second bit string, and the first circuit part In each of the calculation results for the first bit string of N bits, which are performed for each bit, the exclusive OR calculation is performed with the bits of the same position to generate a 2N-bit calculation result. A circuit unit, a third register for inputting a 2N-bit calculation result performed in the second circuit unit, and an upper N bit of the 2N-bit calculation result input to the third register in order Exclusively performing an exclusive OR calculation between a CRC encoder that performs CRC calculation and a CRC calculation result of the CRC encoder and the lower N bits of the 2N-bit operation result input to the third register And a logical OR gate circuit.
[0037]
According to a third aspect of the present invention, in the Galois field multiplier according to the first or second aspect, the N-bit first bit string is an N-bit bit string indicating an element of a Galois field determined by CRC calculation, The N-bit second bit string is an N-bit bit string indicating an element of a Galois field of the order of “0”.
[0038]
According to a fourth aspect of the present invention, in the Galois field multiplier according to the third aspect, the first bit string of N bits is obtained as a result of CRC calculation of a predetermined data string in the range of k1 bits to k2 bits. N-bit bit string indicating the elements of the Galois field, and the second bit string of N bits is all the data strings from the next bit to the last bit of the k2 bits are "0", and the number of "0" This is a bit string of N bits indicating an element of a Galois field of the order of.
[0039]
The gist of a fifth aspect of the present invention is a communication device in which the Galois field multiplier according to any one of the first to fourth aspects is mounted.
[0040]
According to a sixth aspect of the present invention, in the communication device according to the fifth aspect, a CRC encoder for performing an original CRC calculation provided in a signal processing device of the communication device is a Galois field that performs the Galois field multiplication. The gist of the present invention is to also use the CRC encoder of the multiplier.
[0041]
(Function)
According to the first aspect of the present invention, when the N-bit second bit string from the second register is output one bit at a time starting from the most significant bit, the AND gate circuit outputs the one bit and the first register to the first register. Multiplying in sequence with the input N-bit first bit string, and outputting the result to the first exclusive OR gate circuit. The first exclusive OR gate circuit performs an exclusive OR calculation between the multiplication result of the AND gate circuit and the contents previously input to the shift register, and inputs the calculation result to the shift register. The most significant bit of the content input to the shift register is output to the CRC encoder in order, and the CRC encoder performs CRC calculation. Then, the second exclusive OR gate circuit performs an exclusive OR calculation between the contents of the CRC operation result of the CRC encoder and the contents of the shift register, so that an N-bit of Galois field elements is obtained. A result of Galois field multiplication of the first bit string and the second bit string is obtained. Therefore, Galois field multiplication using a CRC encoder is possible.
[0042]
According to the second aspect of the present invention, when the first circuit unit multiplies the first bit sequence of N bits for each bit of the second bit sequence, the second circuit unit For each of the calculation results for the first bit string of N bits performed for each bit, exclusive OR calculation is performed with the bits of the same position to generate a calculation result of 2N bits in the third register. input. Of the 2N-bit calculation results input to the third register, the upper N bits are sequentially output to the CRC encoder, and CRC calculation is performed in the CRC encoder. An exclusive OR gate circuit performs an exclusive OR calculation between the CRC operation result of the CRC encoder and the lower N bits of the 2N bit operation result input to the third register. The result of Galois field multiplication of the N-bit first bit string and the second bit string made up of Galois field elements is obtained. Therefore, Galois field multiplication using a CRC encoder is possible.
[0043]
According to the third aspect of the present invention, the Galois of the N-bit bit string indicating the elements of the Galois field obtained by the CRC calculation and the N-bit bit string indicating the elements of the Galois field of the order of “0”. The result of multiplication is obtained.
[0044]
According to the fourth aspect of the present invention, an N-bit bit string indicating an element of a Galois field obtained as a result of CRC calculation of a data string in a predetermined k1 bit to k2 bit range, All the data strings from the bit to the last bit are set to “0”, and the result of Galois field multiplication is obtained with an N-bit bit string indicating the elements of the Galois field of the order of “0”.
[0045]
According to the invention described in claim 5, Galois field multiplication using a CRC encoder becomes possible.
[0046]
According to the sixth aspect of the present invention, Galois field multiplication using a CRC encoder is possible without increasing the circuit scale.
[0047]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
A first embodiment embodying the present invention will be described below with reference to FIG. FIG. 1 is a block circuit diagram for explaining a Galois field multiplier 1 using a CRC encoder. For convenience of explanation, a case where the CRC value (= CRCm) in the data D3 from the k1 bit to the k2 bit in the mask area shown in FIG. 5 will be described as an example.
[0048]
In FIG. 1, a Galois field multiplier 1 is roughly composed of a shift exclusive OR circuit unit 2, a CRC encoder 3, and an exclusive OR gate circuit 4 as a second exclusive OR gate circuit. ing. The shift exclusive OR circuit unit 2 includes an input register 10 as a first register, a first shift register 11 as a second register, a second shift register 12, an AND gate circuit 13, and a first exclusive OR gate circuit. The exclusive OR gate circuit 14 is provided.
[0049]
The input register 10 receives a bit string Di composed of Galois field elements, which are CRC values being calculated for the data D3 from the k1th bit to the k2th bit of the mask area shown in FIG. In this embodiment, the bit string Di as the first bit string is an N-bit bit string. The input register 10 outputs the input bit string Di to the AND gate circuit 13.
[0050]
The first shift register 11 is input with a bit string Sj as an N-bit second bit string indicating an element of the degree Galois field of the order of “0” from the (k2 + 1) th bit to the last bit. The first shift register 11 outputs the contents of the most significant bit (MBS) at that time to the AND gate circuit 13. Also, when the first shift register 11 outputs the contents of the most significant bit to the AND gate circuit 13, the contents s (bit string Sj) of the shift register 11 is shifted one bit to the right (most significant bit side) once and newly renewed. The most significant bit (MSB) is generated.
[0051]
The AND gate circuit 13 performs multiplication between the content d (N-bit bit string Di) of the input register 10 and the content of the most significant bit (MSB) output from the first shift register 11. This calculation is repeated until the least significant bit (LSB) bit becomes the MSB when the first shift register 11 is initially set and the above calculation is performed. The AND gate circuit 13 outputs the contents of the input register 10 to the exclusive OR gate circuit 14 when the MSB output from the first shift register 11 is “1”. The AND gate circuit 13 does not output the content d of the input register 10 to the exclusive OR gate circuit 14 when the MSB output from the first shift register 11 is “0”. A multiplication operation is performed by this operation.
[0052]
When the MSB output from the first shift register 11 is “1”, the exclusive OR gate circuit 14 determines the exclusive logic between the content d of the input register 10 and the content y of the second shift register 12. Perform a sum operation. Then, the operation result of the exclusive OR is output to the second shift register 12.
[0053]
That is, the second shift register 12 has
y = yXOR (d × (MSB of the first shift register 11))
Is entered.
[0054]
The second shift register 12 is configured to output the content of the most significant bit to the CRC encoder 3 when the operation result y of the exclusive OR from the exclusive OR gate circuit 14 is input. Further, when the second shift register 12 outputs the content of the most significant bit to the CRC encoder 3, the content y of the shift register 12 is shifted one bit to the right (most significant bit side) once and a new most significant bit is obtained. (MSB) is generated.
[0055]
This operation is performed by calculating the exclusive OR operation result y by the exclusive OR gate circuit 14 because the MSB is one bit higher than the least significant bit (LSB) when the first shift register 11 is initially set. Is repeated until. The second shift register 12 outputs the shifted content y to the exclusive OR gate circuit 14.
[0056]
The CRC encoder 3 inputs the most significant bit (MSB) of the second shift register 12 to the CRC encoder register 3a, and in response to the input, shifts the N-bit content g at that time once. Do. Therefore, the CRC encoder 3 repeats the shift operation once every time the MSB is input from the second shift register 12.
[0057]
The N-bit content g of the CRC encoder register 3 a is output to the exclusive OR gate circuit 4. The exclusive OR gate circuit 4 obtains an exclusive OR between the N-bit content g of the CRC encoder register 3a and the content g of the second shift register 12, and obtains the operation result G (= gXORy). It is designed to output.
[0058]
Next, the operation of the Galois field multiplier 1 configured as described above will be described.
[0059]
Now, with the CRC encoder register 3a of the CRC encoder 3 initialized to “0”, the input register 10 calculates the data D3 from the k1 bit to the k2 bit in the mask area shown in FIG. An N-bit bit string Di composed of Galois field elements, which is the CRC value being calculated, is input. In addition, an N-bit bit string Sj indicating a Galois field element of order “0” from the (k2 + 1) -th bit to the last bit is input to the first shift register 11. Further, the content y of the second shift register 12 is initialized to “0”.
[0060]
In this state, the MBS of the first shift register 11 is output to the AND gate circuit 13, and the AND gate circuit 13 performs multiplication between the MBS of the first shift register 11 and the content d of the input register 10. The result (= d × (MSB of the first shift register 11)) is output to the exclusive OR gate circuit 14 at the next stage.
[0061]
At this time, when the content of the MSB of the first shift register 11 is “0”, no operation is performed. When the content of the MSB of the first shift register 11 is “1”, multiplication is performed and the result is supplied to the exclusive OR gate circuit 14.
[0062]
The exclusive OR gate circuit 14 obtains an exclusive OR between the operation result of the AND gate circuit 13 and the content y of the second shift register 12 at that time. The result of the exclusive OR is input to the second shift register 12 as new contents y.
[0063]
When a new content y is input to the second shift register 12, the MSB content of the content y is output to the CRC encoder 3.
[0064]
When the content of the MSB of the second shift register 12 is input, the CRC encoder 3 shifts once in response to the input to generate a new N-bit content g in the CRC encoder register 3a. become.
[0065]
When the shift operation of the CRC encoder 3 is performed, the first and second shift registers 11 and 12 each perform a 1-bit shift operation to the right, and the AND gate circuit 13, the exclusive OR gate circuit 14, and the second shift register 12 and CRC encoder 3 repeat the same operation as described above. That is, the bit higher than the least significant bit (LSB) when initially set in the first shift register 11 becomes the MSB, and the exclusive OR operation result y by the exclusive OR gate circuit 14 is input. Repeat until Accordingly, every time the exclusive OR operation result y is input to the second shift register 12, the CRC encoder 3 inputs the MSB and repeats the shift operation.
[0066]
Then, the least significant bit (LSB) bit becomes the MSB, and the exclusive OR operation result y by the exclusive OR gate circuit 14 is obtained. As a result, y is input to the second shift register 12. The content y of the second shift register 12 is output to the exclusive OR gate circuit 4. The exclusive OR gate circuit 4 obtains an exclusive OR between the content y of the second shift register 12 and the N-bit content g of the CRC encoder register 3a at that time. Then, the calculation result G (= gXORy) is output as a CRC value (= CRCm = Di × Sj).
[0067]
That is, the second shift register 12 is provided, and the second shift register 12 is initialized to “0” from time to time, that is, the operation of y = yXOR (d × MBS of the first shift register 11) is performed in the first shift register. 11, while shifting the contents s of 11, the MBS of the second shift register 12 is sequentially input to the CRC encoder 3. As a result, it is the same as the multiplication using the Galois encoder. However, since the content y (= yXOR (d × MBS of the first shift register 11)) of the second shift register 12 is not directly input to the CRC encoder 3, (N-1) shift operations are performed. After that, an exclusive OR is taken between the content y of the second shift register 12 and the content g of the CRC encoder register 3a.
[0068]
Thus, in this embodiment, by providing the shift exclusive OR circuit unit 2 in the preceding stage of the CRC encoder 3, Galois multiplication similar to the Galois encoder can be performed. Therefore, the CRC value (= CRCm = Di × Sj) can be obtained without increasing the circuit scale.
[0069]
In addition, as the data input to the first shift register 11, an N-bit bit string Sj indicating an element of the degree “0” order Galois field from the (k2 + 1) -th bit to the last bit is input. Accordingly, the CRC encoder alone is faster than the case of obtaining the CRC value (= CRCm) by inputting “0” by the number of “0” from the (k2 + 1) th bit to the last bit and performing the shift operation. A CRC value (= CRCm = Di × Sj) can be obtained.
(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a block circuit diagram for explaining a Galois field multiplier 21 using a CRC encoder. For convenience of explanation, a case where the CRC value (= CRCm) in the data D3 from the k1 bit to the k2 bit in the mask area shown in FIG. 5 will be described as an example.
[0070]
In FIG. 2, the Galois field multiplier 21 is roughly composed of a shift exclusive OR circuit unit 22, a CRC encoder 23, and an exclusive OR gate circuit 24. The shift exclusive OR circuit unit 22 includes an N-bit first register 31, an N-bit second register 32, a 2N-bit shift register 33, a first circuit unit 34, and a second circuit unit 35. Yes.
[0071]
The first register 31 receives a bit string Di composed of Galois field elements, which are CRC values being calculated for the data D3 from the k1th bit to the k2th bit of the mask area shown in FIG. In this embodiment, the bit string Di as the first bit string is an N-bit bit string. The second register 32 is input with a bit string Sj as an N-bit second bit string indicating elements of the degree of Galois field of the order of “0” from the (k2 + 1) th bit to the last bit.
[0072]
The first circuit unit 34 includes N sets corresponding to the number of bits (N bits) of the bit string Sj of the second register 32, and each set includes the number of bits of the bit string Di of the first register 31 ( N AND gate circuits 34a each corresponding to (N bits). Accordingly, the first circuit unit 34 is configured to have N²The AND gate circuit 34a is provided.
[0073]
Each set of N AND gate circuits 34a receives the bit data corresponding to the bit string Sj composed of N bits input to the second register 32 for each set. Each set of N AND gate circuits 34a receives bit data corresponding to a bit string Di consisting of N bits of the first register 31.
[0074]
That is, for example, N AND gate circuits 34a of a set (hereinafter referred to as a first set) that inputs the least significant bit (LSB) of the bit string Sj input to the second register 32 have the least significant bit (LSB). ) And the corresponding bit data of the bit string Di input to the first register 31, respectively.
[0075]
Incidentally, the N AND gate circuits 34a of the set (hereinafter referred to as the Nth set) that inputs the most significant bit (MSB) of the bit string Sj input to the second register 32 have the most significant bit (MSB) The bit data corresponding to each bit string Di input to the first register 31 is multiplied.
[0076]
The calculation results calculated by the first to Nth AND gate circuits 34 a of the first circuit unit 34 are output to the second circuit unit 35.
[0077]
The second circuit unit 35 has a number of output terminals corresponding to the number of bits (2N bits) input to the shift register 33, and each output terminal is connected to a bit of the shift register 33. . Then, the second circuit unit 35 moves the least significant bit (LSB) of the shift register 33 between the least significant bit (LSB) of the first set of bit strings Di and the least significant bit (LSB) of the bit string Sj. An operation result from the AND gate circuit 34a for performing the operation is input. The second circuit unit 35 inputs “0” data to the most significant bit (MSB) of the shift register 33. Further, the second circuit unit 35 performs the most significant bit of the Nth bit string Di with respect to the bit that is one bit lower ((2N−1) th bit) than the most significant bit (MSB) of the shift register 33. An operation result from the AND gate circuit 34a that performs an operation between (MSB) and the most significant bit (MSB) of the bit string Sj is input.
[0078]
Further, the second circuit unit 35 has each bit from 1 bit higher (second bit) than the lowest bit of the shift register 33 to 2 bits lower ((2N−2)) bit than the highest bit. Corresponding to the bit, an exclusive OR gate circuit 35a is provided. Each exclusive OR gate circuit 35a inputs the operation result to each bit of the corresponding shift register 33.
[0079]
More specifically, an exclusive OR gate circuit (hereinafter referred to as a first gate circuit) 35a corresponding to the second bit of the shift register 33 is supplied from each of the predetermined AND gate circuits 34a of the first set and the second set. Input the calculation result. An exclusive OR gate circuit (hereinafter referred to as a second gate circuit) 35a corresponding to the third bit of the shift register 33 inputs the operation results from the predetermined AND gate circuits 34a of the first to third groups. . An exclusive OR gate circuit (hereinafter referred to as a third gate circuit) 35a corresponding to the fourth bit of the shift register 33 inputs the operation results from the predetermined AND gate circuits 34a of the first to fourth groups. .
[0080]
In this way, in the exclusive OR gate circuit 35a, the number of sets for performing the exclusive OR operation is increased by one until the bit of the shift register 33 becomes N bits, and from (N + 1) bits to (2N−). 2) In the exclusive OR gate circuit 35a up to a bit, the number of sets for performing an exclusive OR operation is decreased by one. Accordingly, the exclusive OR gate circuit (Nth gate circuit) 35a corresponding to the N bits of the shift register 33 inputs the operation results from the predetermined AND gate circuit 34a from the first to Nth groups, which are the largest. .
[0081]
Each exclusive OR gate circuit 35a performs an operation by inputting the operation results from a plurality of predetermined AND gate circuits 34a.
[0082]
More specifically, the 2-bit exclusive OR gate circuit 35 a includes an AND gate circuit 34 a that performs the operation of the second bit of the first register 31 of the first set, and the lowest order of the first register 31 of the second set. An exclusive OR operation is performed on the operation result of the AND gate circuit 34a that performs a bit (first bit) operation. The 3-bit exclusive OR gate circuit 35 a includes an AND gate circuit 34 a that performs the operation of the third bit of the first register 31 and an AND operation that performs the operation of the second bit of the second register 31. An exclusive OR operation is performed on the operation results of the gate circuit 34a and the AND gate circuit 34a that performs the operation of the first bit of the third set of first registers 31.
[0083]
The 4-bit exclusive OR gate circuit 35a includes an AND gate circuit 34a that performs an operation on the fourth bit of the first register 31 and an AND gate that performs an operation on the third bit of the second register 31. The gate circuit 34a, the AND gate circuit 34a that performs the second bit operation of the third set of first registers 31, and the operation result of the AND gate circuit 34a that performs the first bit operation of the fourth set of first registers 31 Is subjected to an exclusive OR operation.
[0084]
In other words, the first and second circuit units 34 and 35 have their N-bit operation results obtained by the N AND gate circuits 34a in the first to N-th groups as they move to higher groups. The N-bit operation result of the set is shifted one bit higher than the N-bit operation result of the lower set. That is, after shifting the first to Nth sets of N-bit operation results, exclusive OR operation is performed for each bit (each digit). The first and second circuit units 34 and 35 are configured to input the obtained 2N-bit calculation result to the shift register 33.
[0085]
When the 2N-bit operation result y is input from the second circuit unit 35, the shift register 33 shifts the most significant bit to the most significant bit side and outputs the most significant bit (MSB) at that time to the CRC encoder 23. It has become. This shift operation is performed N times. Accordingly, the shift register 33 sequentially outputs the upper N bits of the 2N-bit calculation result y input from the second circuit unit 35 to the CRC encoder 23. The shift register 33 outputs the remaining lower N bits after outputting the upper N bits to the CRC encoder 23 to the exclusive OR gate circuit 24.
[0086]
The CRC encoder 23 sequentially receives the upper N bits of bit data from the shift register 33 and performs a shift operation.
[0087]
The exclusive OR gate circuit 24 inputs the content g of the operation result obtained by performing the N-time shift operation of the CRC encoder register 23 a and the content y of the lower N bits of the shift register 33. The exclusive OR gate circuit 24 obtains an exclusive OR between the contents g and y and outputs the operation result G (= gXORy).
[0088]
Next, the operation of the Galois field multiplier 21 configured as described above will be described.
[0089]
Now, in the state where the CRC encoder register 23a is initialized to “0”, the first register 31 is in the middle of calculating the data D3 from the k1 bit to the k2 bit in the mask area shown in FIG. An N-bit bit string Di composed of Galois field elements which are CRC values is input. In addition, an N-bit bit string Sj indicating a Galois field element of order “0” from the (k2 + 1) th bit to the last bit is input to the second register 32. Further, the contents y of the shift register 33 is initialized to “0”. 2N-bit data (content y) is generated from the N-bit content d and the N-bit content s and input to the shift register 33.
[0090]
The shift register 33 performs a shift operation N times, and inputs the upper N bits of bit data in the content y of 2N bits to the CRC encoder 23 in order. As a result, the CRC encoder 23 receives the upper N bits of bit data and performs a shift operation for N bits. Then, the exclusive OR gate circuit 24 obtains an exclusive OR between the lower N-bit data (content y) remaining in the shift register 33 and the content g of the CRC encoder register 23a at that time. That is, the operation result G (= gXORy) of the exclusive OR gate circuit 24 is output as a CRC value (= CRCm = Di × Sj).
[0091]
As described above, also in the second embodiment, by providing the shift exclusive OR circuit unit 22 in the previous stage of the CRC encoder 23, Galois multiplication similar to that of the Galois encoder can be performed. Therefore, the CRC value (= CRCm = Di × Sj) can be obtained without increasing the circuit scale.
[0092]
In addition, as the data input to the second register 32, an N-bit bit string Sj indicating an element of a degree Galois field of the order of “0” from the (k2 + 1) th bit to the last bit is input. Accordingly, the CRC encoder alone is faster than the case of obtaining the CRC value (= CRCm) by inputting “0” by the number of “0” from the (k2 + 1) th bit to the last bit and performing the shift operation. A CRC value (= CRCm) can be obtained.
(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 3 is a block circuit diagram for explaining an electrical configuration of a signal processing device in which the shift exclusive OR circuit unit 22 of the Galois multiplier 21 described in the second embodiment is mounted in a communication device such as a router. Indicates.
[0093]
In FIG. 3, the signal processing device 41 includes an ALU 42, a register group 43, a CRC engine 44, and a shift exclusive OR circuit unit 22, which exchange signals with each other via buses B1 and B2. The ALU 42 performs arithmetic processing for various signal processing for communication in cooperation with the register group 43. The CRC engine 44 is an engine that performs a CRC operation for error correction of an input signal input to the communication device, and is the CRC encoder 23 and the exclusive OR gate circuit 24 described in the second embodiment. And the same CRC encoder and exclusive OR gate circuit (not shown).
[0094]
The shift exclusive OR circuit unit 22 includes a first register 31, a second register 32, a shift register 33, a first circuit unit 34, and a second circuit unit 35. The first register 31 receives a CRC value calculated by the CRC engine 44 from the N-bit bit string Di. In the second register 32, the N-bit bit string Sj is read and input from data indicating Galois field elements of the order of “0” stored in the memory 45 prepared in advance. Therefore, when the number of “0” is fixed, one bit string Sj is stored in the memory 45 prepared in advance. In the memory 45, a search tag table TT and a search data table TD for searching the search target data DX shown in FIG. 4 are also stored in advance.
[0095]
The shift register 33 outputs the upper N bits of the 2N-bit calculation result y calculated based on the bit strings Di and Sj to the CRC engine 44 bit by bit in order from the upper bit. The shift register 33 outputs the upper N bits in order from the upper bits to the CRC engine 44, and then outputs the lower N bits of the 2N-bit operation result y to the CRC engine 44.
[0096]
Next, the operation of the signal processing device 41 configured as described above will be described.
[0097]
For convenience of explanation, a case will be described in which the CRC value (= CRCm = Di × Sj; where x is an exclusive OR) of the data D3 is obtained for the input data D shown in FIG.
[0098]
Now, when the input data D is input to the signal processing device 41, the CRC engine 44 starts calculating the CRC from the k1th bit data of the input data D input. The CRC engine 44 performs the CRC calculation on the entire input data D in parallel with the CRC calculation. When the calculation of the CRC up to the bit data of the k2th bit is completed, the N-bit bit string Di that is the CRC value up to that time is input to the first register 31 of the shift exclusive OR circuit unit 22. At the same time, the second register 32 receives an N-bit bit string Sj indicating an element of a Galois field of the order of “0” from the (k2 + 1) -th bit to the last bit from the memory 45. Then, a 2N-bit calculation result y calculated based on the bit strings Di and Sj is input to the shift register 33.
[0099]
Next, the CRC encoder register 44 a provided in the CRC engine 44 is initialized to “0”. Subsequently, the upper N bits of the shift register 33 are input to the CRC encoder register 44a bit by bit in order from the most significant bit. The CRC encoder register 44a of the CRC engine 44 is shifted by N bits by the input of the upper N bits of bit data. Then, by exclusive ORing the lower N bits of the shift register 33 and the value of the encoder register 44a, a Galois multiplication result of CRCm = Di × Sj is obtained.
[0100]
Then, the CRC value (= CRCx == CRCx) of the search target data DX is obtained by performing an exclusive OR operation on the CRC value (= CRCm) of the obtained data D3 and the CRC value (= CRCn) of the entire input data D. CRC × CRCm) can be obtained. When the CRC value (= CRCx) of the search target data DX is obtained, the signal processing device 41 uses the search tag table TT and the search data table TD stored in the memory 45 to search the search data DS for the search target data DX. Will search.
[0101]
Thus, according to the signal processing device 41 of the communication device such as the router of the present embodiment, only the shift exclusive OR circuit unit 22 is added and the CRC encoder provided in the CRC engine 44 is used for hash search. Thus, a CRC hash search can be performed without increasing the circuit scale.
[0102]
In addition, since the shift exclusive OR circuit unit 22 performed after the bit strings Di and Sj are input does not depend on the arithmetic processing of the ALU 42, the arithmetic operation can be performed with few instruction cycles. Further, as in the above embodiment, the CRC value can be obtained in a short time and without increasing the circuit scale.
[0103]
Further, according to the signal processing device 41 of the communication device such as the router of this embodiment, only the shift exclusive OR circuit unit 22 is added, and the CRC encoder provided in the CRC engine 44 is used for hash search. Therefore, a CRC hash search can be performed without increasing the circuit scale.
[0104]
In addition, you may change embodiment of this invention as follows.
[0105]
The signal processing device 41 according to the third embodiment has the shift exclusive OR circuit unit 22 described in the second embodiment added, but the shift exclusive OR circuit described in the first embodiment. You may apply to the signal processing apparatus formed by adding the part 2.
[0106]
In the third embodiment, the bit string Di, which is the CRC value for the data D3 from the k1th bit to the k2th bit, is a CRC calculation performed by the CRC engine 44 from time to time, and the last bit from the (k2 + 1) th bit The N-bit bit string Sj indicating the elements of the order Galois field of the number “0” up to the bit is obtained from data stored in the memory 45 in advance.
[0107]
In the input data D, the bit string Di that is the CRC value for the data D3 from the k1st bit to the k2th bit and the Galois of the order of the number “0” from the (k2 + 1) th bit to the last bit. An N-bit bit string Sj indicating a body element is included. Then, when the input data D is input, the bit string Di and the bit string Sj in the input data D may be read, and the operation may be immediately performed using the bit string Di and the bit string Sj.
[0108]
In this case, it is not necessary to perform the CRC calculation from the k1th bit to the k2th bit, and the bit string Sj indicating the elements of the Galois field of the order of “0” from the (k2 + 1) th bit to the last bit is stored. No storage means is required.
[0109]
【The invention's effect】
As described above in detail, according to the present invention, the Galois field multiplication using the CRC encoder can be performed.
[Brief description of the drawings]
FIG. 1 is a block circuit diagram for explaining a Galois field multiplier using a CRC encoder according to a first embodiment.
FIG. 2 is a block circuit diagram for explaining a Galois field multiplier using the CRC encoder of the second embodiment.
FIG. 3 is a block circuit diagram for explaining a signal processing device of a communication device according to a third embodiment.
FIG. 4 is an explanatory diagram for explaining a hash search.
FIG. 5 is an explanatory diagram for explaining a data structure of data to be searched for hash search and how to obtain the data structure;
FIG. 6 is a block circuit diagram for explaining a Galois field multiplier using a conventional Galois encoder.
FIG. 7 is a block circuit diagram for explaining a Galois field multiplier similarly using a conventional Galois encoder.
[Explanation of symbols]
1,21 ... Galois field multiplier
2,22 ... Shift exclusive OR circuit section
3, 23 ... CRC encoder
4, 24 ... Exclusive OR gate circuit
10 ... Input register
11: First shift register
12 ... Second shift register
13 ... AND gate circuit
14 ... Exclusive OR gate circuit
31 ... 1st register
32. Second register
33 ... Shift register
34. First circuit portion
34a ... AND gate circuit
35 ... Second circuit section
35a ... Exclusive OR gate circuit
41 ... Signal processing device
42 ... ALU
43: Register group
44 ... CRC engine
45 ... Memory
Di: Bit string
Sj: Bit string
TD ... Search data table
D3 ... Data
d, g, s, y

Claims (6)

Galois field multiplication for performing Galois field multiplication of an N-bit first bit string composed of Galois field elements input to the first register and an N-bit second bit string composed of Galois field elements input to the second register In the vessel
A shift register that shifts 1 bit to the most significant bit side while inputting the result of the exclusive OR calculation of N bits and outputting the most significant bit at that time;
An AND gate circuit that sequentially multiplies the first bit string of N bits one by one in order from the most significant bit of the second bit string of N bits;
A first exclusive OR gate circuit that performs an exclusive OR calculation between the operation result from the AND gate circuit and the contents of the shift register and inputs the calculation result to the shift register;
A CRC encoder that sequentially inputs the most significant bit from the shift register and performs a CRC operation;
A Galois field multiplier comprising a second exclusive OR gate circuit for performing an exclusive OR calculation between the contents of the CRC encoder and the contents of the shift register. Galois field multiplication for performing Galois field multiplication of an N-bit first bit string composed of Galois field elements input to the first register and an N-bit second bit string composed of Galois field elements input to the second register In the vessel
The first bit sequence of the N bits, the first set corresponding to the respective multiplication for each bit of the Dear second bit string row stomach, the most significant bits from the least significant bit of the second bit sequence of the N-bit A first circuit unit for generating Nth set of calculation results ;
Of the N sets of calculation results from the first set for the first bit sequence of said N bits made for each bit of each position the second bit string in said first circuit portion, each of the second set of the N sets computed by shifting the respective front set of calculations than 1 bit higher, for the first set of calculation result and the shifted second set the N sets of the calculation results from each set of same-position a second circuit portion for generating a calculation result of 2N bit performs exclusive OR computation between bits,
A third register for inputting a 2N-bit calculation result performed in the second circuit section;
A CRC encoder that sequentially inputs the upper N bits of the 2N-bit operation result input to the third register and performs CRC calculation;
An exclusive OR gate circuit that performs an exclusive OR calculation between the CRC calculation result of the CRC encoder and the lower N bits of the 2N-bit operation result input to the third register. Characteristic Galois field multiplier. The Galois field multiplier according to claim 1 or 2,
The N-bit first bit string is an N-bit bit string indicating an element of a Galois field obtained by CRC calculation.
The N-bit second bit string is an N-bit bit string indicating an element of an order Galois field of the number “0”. The Galois field multiplier according to claim 3,
The N-bit first bit string is an N-bit bit string indicating an element of a Galois field obtained as a result of CRC calculation of a predetermined data string in the range of k1 bits to k2 bits.
The N-bit second bit string is an N-bit bit string indicating all elements of the Galois field of the order of the number “0”, where all data strings from the next bit to the last bit of the k2 bit are “0”. A Galois field multiplier characterized by being.   The communication apparatus which mounted the Galois field multiplier as described in any one of Claims 1 thru | or 4. The communication device according to claim 5, wherein
A communication apparatus characterized in that a CRC encoder for performing an original CRC calculation provided in a signal processing apparatus of the communication apparatus also serves as a CRC encoder of a Galois multiplier for performing the Galois multiplication.

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