JP4243277B2 - Data processing device - Google Patents

Description

  The present invention relates to a data processing apparatus, and more particularly to a technique for realizing a rounding operation with an efficient hardware configuration in a fixed-point arithmetic unit in a processor element.

Image processing including moving image compression is a relatively simple iteration of a calculation algorithm, and data parallelism for the same instruction is large. Therefore, a SIMD (Single Instruction Multiple Data stream) type parallel calculation method is suitable for speeding up image processing.
MPEG (ISO / IEC14496-2 (MPEG4), ISO / IEC13818-2 (MPEG2), ISO / IEC11172-2 (MPEG1)) is known as a moving picture compression standard. According to this video compression standard, a digitized image is divided into blocks, a motion vector is detected for each block, DTC (Discrete Cosine Transform) and quantization are performed, and Huffman coding is performed to compress the image data. .
When the SIMD parallel computing architecture is applied to MPEG video compression, a plurality of processors can be used as the calculation unit of the image block. In other words, in motion vector detection, the shift block of the detection range is arranged in the local memory of multiple processors, the block to be compressed is broadcast to all the processors from the control system, and the frame difference is calculated in parallel, thereby speeding up the number of processors Can be expected. Also, the block difference frame data of the block image to be compressed or the detected motion vector position is placed in the local memory of multiple processors, and DCT (or IDCT) or quantization (or inverse quantization) calculations are performed in parallel. By doing so, it can be expected to increase the speed by several times the number of processors.

According to the study by the present inventors, in the above-described technique, for the data in the fixed-point format, adjustment of the number of bits changed by multiplication or change of the decimal point position for adjusting the number of significant digits of the integer part by addition / subtraction is not performed. This is done with a shifter in the processor. At this time, when the bit on the LSB side is deleted or the right bit is shifted by the shifter in order to reduce the multiplication result to a predetermined data width, a rounding process is required for the LSB of the data in order to avoid deterioration of the calculation accuracy. It is.
For rounding, there is a method defined in IEEE 754, which is a floating-point format standard, for rounding the result of an operation to a predetermined bit of the mantissa and outputting it. According to this standard, there are four types of methods: nearest rounding, -∞ direction rounding, + ∞ direction rounding, and 0 direction rounding. Can be selected).
In the above-described technique, the data is rounded off in the −∞ direction simply because of the truncation. In order to use other nearest rounding, + ∞ direction rounding, or 0 direction rounding, it is necessary to carry out in software by program description. That is, according to the description of the program, the bits to be discarded are examined according to the desired rounding method, the state is judged, and the operation is performed to add 1 to the least significant bit to be rounded.
However, in order to realize the rounding process by a program, it is necessary to perform a shift operation for evaluating the bits to be discarded and a condition code acquisition process by an ALU (arithmetic logic unit) for determining the state.
Therefore, in the case of the −∞ direction, which is hardware inconvenient, for example, even if the operation allows one apparent data to be processed in one step by pipeline processing, other nearest value rounding and + ∞ direction rounding In the case of using 0-direction rounding, a processing step for rounding is required, and the speed performance is deteriorated. In particular, in the SIMD type parallel arithmetic unit configuration, since a plurality of pieces of arithmetic data exist simultaneously for one program, it is difficult to increase the speed by branching the processing step according to the data state, and the processing step time of all cases is difficult. Necessary.
An object of the present invention is to provide a data processing device that can reduce the overhead of rounding processing with an efficient circuit configuration and can efficiently improve the numerical operation accuracy of an information processing device using a fixed-point arithmetic unit. is there.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
That is, the data processing apparatus of the present invention has the following characteristics.
(1) A processor configured to include a shifter having a right bit shift operation function, an ALU having a carry-in function for adding 1-bit data to the least significant bit in addition of two input data, and the processor A data processing apparatus configured with a control unit controlled by a single instruction, wherein the shifter outputs data of a shift operation result and simultaneously performs a rounding evaluation on a bit that is truncated in the case of right bit shift and shifts Rounding evaluation means for outputting 1-bit data indicating whether or not addition of “1” is necessary to the least significant bit of the operation result, and the ALU uses one of the two input data as output data of the shifter, The data used in the carry-in function is 1-bit data output by the rounding evaluation means of the shifter.
Thereby, when adding data of different decimal point positions, in order to guarantee an integer digit, the data with a small number of integer digits is right-shifted and digitized before adding. With the above configuration, first, the shifter can output the necessity of 1 addition for rounding processing as 1-bit data at the same time as the right shift for digit alignment, and then the two data aligned in the ALU Since the detected 1-bit data can be added simultaneously with the addition of, the time required for the rounding process for the right-shifted data can be eliminated.
In addition, since 1 addition for rounding can be an addition function with carry-in in the ALU of the prior art, it is only necessary to add a round evaluation to the shifter and a 1-bit data output circuit as a result.
(2) The right shift operation in the shifter and the addition of the carry-in function in the ALU are operations corresponding to 2's complement data.
Thereby, the calculation of the shifter and the ALU is performed in the two's complement format, which is a conventional technique, so that the rounding process can be realized with the same configuration as the above for the signed calculation. For example, if the shifter and ALU operations can be selected as either unsigned operation or signed operation in response to a control signal from the control system, the purpose of use is such that unsigned data and signed data are mixed. Even so, it is possible to perform rounding processing with the same effect as described above.
(3) It has a rounding mode selection means, and the rounding evaluation means performs rounding evaluation corresponding to each of a plurality of rounding modes selectable by the rounding mode selection means.
Thus, by making the rounding evaluation circuit compatible with a plurality of rounding modes, it is possible to realize a rounding process in a desired rounding mode with the same configuration as described above. For example, if the rounding mode in the operation of the rounding evaluation circuit can be selected in response to a control signal from the control system, the same rounding mode as described above can be used for the purpose of use by dynamically changing different rounding modes. The effect can be rounded.
(4) The processor includes a plurality of processors, and the rounding mode selection means selects a rounding mode by data storage means provided for each of the plurality of processors.
As a result, the means for selecting the rounding mode is a storage means such as a register provided for each processor, so that the number of control signals from the control system to a plurality of processors can be reduced.
(5) The rounding evaluation is a logical sum of bits rounded down by the right bit shift.
As a result, the rounding evaluation operation is the logical sum of the bits rounded down by the right bit shift in the shifter, thereby rounding (rounding up) the unsigned data or the signed data in the two's complement format. Can be realized. Further, the ∞ rounding of the sign can be realized for signed absolute value format data.
(6) The rounding evaluation is a logical product of the logical sum of the bits rounded down by the right bit shift and the sign of the shift operation data.
As a result, the rounding evaluation operation is performed on the signed two-complement signed data by performing a logical product of the logical sum of the bits rounded down by the right bit shift in the shifter and the sign of the shift operation data. Zero-direction rounding can be realized. Further, rounding in the −∞ direction can be realized for signed absolute value format data.
(7) The rounding evaluation is performed by calculating the logical sum of the bit except the most significant bit of the bits truncated by the right bit shift and the least significant bit of the shift operation result and the bits of the bits truncated by the right bit shift. It is the logical product with the most significant bit.
As a result, the rounding evaluation operation is performed using the logical sum of the bits other than the most significant bit of the bits truncated by the shift in the shifter and the least significant bit of the shift operation result, and the bits truncated by the right shift. By performing a logical product with the most significant bit of, nearest rounding can be realized for unsigned data, signed data in 2's complement format, or signed absolute value format data.
(8) It is configured on one semiconductor substrate.
According to the data processing apparatus, in order to realize truncation as in the prior art, a state is provided in which the rounding mode selection means always negates 1-bit data output from the rounding evaluation circuit to the ALU. Just do it. At this time, it operates as -∞ direction rounding for signed data in 2's complement format. Also, it operates as rounding in the zero direction (truncating) on unsigned data or signed absolute value format data.
The addition of the shifter terminal by providing the rounding evaluation circuit as described above requires only a mode designation signal and a 1-bit data output signal to the ALU. Even if the rounding evaluation circuit added to the shifter supports a plurality of rounding modes, the logical sum of bits to be rounded down can be made common, so that the circuit scale can be reduced.
As described above, the overhead reduction of the rounding process is achieved with an efficient circuit configuration.

FIG. 1 is a block diagram showing a circuit configuration for realizing a rounding process according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a detailed circuit configuration of the shifter of FIG.
FIG. 3 is a diagram showing a truth table of operations in the rounding evaluation circuit of FIG.
FIG. 4 is a diagram showing a configuration of a SIMD type parallel DSP including the circuit configuration of FIG.
FIG. 5 is a diagram showing a configuration in which storage means for designating the number of shift bits is added to the shifters of FIGS.
FIG. 6 is a diagram showing another configuration of the data calculation execution unit of FIG.
FIG. 7 is a block diagram showing a detailed circuit configuration of the shifter of FIG.
FIG. 8 is a diagram showing a truth table of operations in the rounding evaluation circuit of FIG.
FIG. 9 is a diagram showing a configuration in which the rounding processing of the present invention is applied to a conventional data processing apparatus.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that in all the drawings for explaining the embodiments, the same members are denoted by the same reference numerals, and the repeated explanation thereof is omitted.
FIG. 1 is a block diagram showing a circuit configuration for realizing a rounding process according to an embodiment of the present invention.
In FIG. 1, n represents the number of bits of the data signal, and can be, for example, 32 bits.
The shifter 10 performs a shift operation on the n-bit data selectively transmitted from the general-purpose register file 20 or the outside via the shifter input line, and outputs the result to the n-bit shifter output latch 30. At the same time, the rounding evaluation result is output to the 1-bit latch r40.
Here, the selection of data on the shifter input line is performed by, for example, a control signal supplied from the outside although not shown.
The shift operation in the shifter 10 has an arithmetic / logical value shift function of left / right m (<n) bit shift, and although not shown, for example, an operation designated by an external control signal or the like is performed.
The difference between the arithmetic shift and the logical shift is that the arithmetic shift is a shift in which the input data is a two's complement binary number, and the code (MSB bit) by the shift operation is not changed. That is, in the case of the right shift, the sign bit (input MSB bit) is packed in the number of upper shift bits of the output data in the arithmetic shift, and 0 is packed in the logical shift.
In the case of left shift, the lower shift bits of the output data are padded with 0 for both arithmetic and logical shifts. However, in the arithmetic shift, overflow processing is performed for input data whose upper shift bits + 1 bit of the input data are not the same. The maximum value equal to the sign of the input data (in the case of 32 bits, the positive maximum value is H'7fffffff, the negative maximum value is H'80000000, where H 'is a prefix for representing a hexadecimal number) is output. The
Further, the shifter 10 has a rounding evaluation function, and outputs 1 to the latch r40 when 1 addition is necessary to round the bits overflowing to the right by the right shift to the output data of the right shift calculation result, and otherwise. In this case, 0 is output to the latch r40.
The ALU 50 receives the first n-bit data or constant “0” alternatively transmitted from the shifter output latch 30, the general-purpose register file 20 or the outside via the ALU input (1) line, and the ALU input (2). The second n-bit data or constant “0” alternatively transmitted from the cumulative addition register ΣR60 or the general-purpose register file 20 via the line, and the selector 90 selects the 1-bit latch r40 or the latch CO70. An arithmetic logic operation is performed on the 1-bit data, and the result is output to the n-bit ALU output latch 80 and the cumulative addition register ΣR60.
At the same time, the carry (carry out) from the most significant bit is output to the 1-bit latch CO70. Here, the selection of data on the ALU input (1) line and the ALU input (2) line, the selection of constant 0, and the selection of 1-bit data are not illustrated, but are performed by, for example, control signals given from the outside. Is done.
Arithmetic / logical operations in the ALU 50 have addition / subtraction as arithmetic operations and a logical operation function. Although not shown, for example, an operation designated by an external control signal or the like is performed. Arithmetic operations are signed addition / subtraction in which the first data and the second data are binary numbers in two's complement format, or unsigned addition / subtraction in which the first data and the second data are unsigned binary numbers. In addition, in these two additions and subtractions, a carry-in function for simultaneously adding 1-bit data to the least significant bit (LSB) can be selected.
Although the logical operation is not particularly limited, the logical sum, logical product, exclusive logical sum, logical sum inversion, logical product inversion, or exclusive logic for each corresponding bit of the first data and the second data is not limited. It is sum reversal.
Although not shown, the cumulative addition register ΣR60 is written with n-bit data output from the ALU 50 in response to, for example, a control signal supplied from the outside.
The general-purpose register file 20 is not particularly limited, and is composed of one input and two outputs for a register group of n bits × multiple words. Although not shown, for example, writing to a register designated by an externally supplied control signal or the like Reading is done.
That is, in response to the control signal, the n-bit data alternatively transmitted from the shifter output latch 30 or the ALU output latch 80 via the RF write line is the general register address 1 ( It is written to the register specified by RFA1).
One of the two outputs of the general-purpose register file 20 outputs the data of the register specified by the general-purpose register address 0 (RFA0) included in the control signal, and the shifter input line and the ALU input (1) line Is transmitted to. On the other hand, the data of the register designated by the general-purpose register address 1 (RFA1) is output and transmitted to the ALU input (2) line and to the outside. When the above-described writing is performed on the register designated by general-purpose register address 1 (RFA1), the output data is data before writing.
Next, an operation using the rounding process according to the circuit configuration example of FIG.
First, as an example, an operation in the case where three binary numbers A, B, and C having different fixed-point positions stored in the general-purpose register file 20 are added and stored in the general-purpose register file 20 will be described.
Here, for simplicity of explanation, when the data width is n = 32 bits and the fixed-point position of the data is represented by a data name (integer number of bits.number of fractional bits), the fixed-point position of the three data is A (10.22), B (1.31), and C (15.17), and the fixed point position of the addition result X is X (16.16).
[Processing step 1]
For the general register file 20, the address where A (10.22) is stored is designated by RFA0 and A (10.22) is output.
At the same time, the general-purpose register file 20 is selected for the shifter input line, and A (10.22) is transmitted to the shifter.
At the same time, a right 6-bit arithmetic shift operation is designated for the shifter 10.
With the above control, in processing step 1, data obtained by arithmetically shifting A (10.22) to the right by 6 bits is output to the shifter output latch 30, and the rounding evaluation result for 6 bits to be simultaneously discarded is output to the latch r40. .
[Processing step 2]
An address where B (1.31) is stored is designated by RFA0 for the general-purpose register file 20, and B (1.31) is output.
At the same time, the general-purpose register file 20 is selected for the shifter input line, and B (1.31) is transmitted to the shifter.
At the same time, a right 15-bit arithmetic shift operation is designated for the shifter 10.
At the same time, the shifter output latch 30 is selected for the ALU input (1) line, and the A shift result in the processing step 1 is transmitted as the first data of the ALU 50.
At the same time, the constant 0 is selected for the ALU input (2) line, and the second data of the ALU 50 is set to 0.
At the same time, a signed addition operation with a carry-in function with the carry-in as a latch r40 is designated for the ALU 50.
At the same time, write is designated to the cumulative addition register ΣR60.
With the above control, in processing step 2, data obtained by arithmetically shifting B (1.31) to the right by 15 bits is output to the shifter output latch 30, and the rounding evaluation result for 15 bits to be simultaneously discarded is output to the latch r40. . The ALU 50 rounds the 6 bits on the LSB side when digitizing A (10.22) to A (16.16) and outputs the result to the cumulative addition register ΣR60.
[Processing step 3]
The general register file 20 is designated by RFA0 with the address where C (15.17) is stored, and C (15.17) is output.
At the same time, the general-purpose register file 20 is selected for the shifter input line, and C (15.17) is transmitted to the shifter 10.
At the same time, a right 1-bit arithmetic shift operation is designated for the shifter 10.
At the same time, the shifter output latch 30 is selected for the ALU input (1) line, and the B shift result in the processing step 2 is transmitted as the first data of the ALU 50.
At the same time, the cumulative addition register ΣR0 is selected for the ALU input (2) line, and the rounding result of A in the processing step 2 is transmitted as the second data of the ALU 50.
At the same time, a signed addition operation with a carry-in function with the carry-in as a latch r40 is designated for the ALU 50.
At the same time, write is designated to the cumulative addition register ΣR60.
With the above control, in processing step 3, data obtained by arithmetically shifting C (15.17) to the right by 1 bit is output to the shifter output latch 30, and the rounding evaluation result for 1 bit to be simultaneously discarded is output to the latch r40. . In addition, the ALU 50 rounds the 15 bits on the LSB side when digitizing B (1.31) to B (16.16) and adds to A (16.16) digitized in processing step 2. Are simultaneously output to the cumulative addition register ΣR60.
[Processing step 4]
The shifter output latch 30 is selected for the ALU input (1) line, and the C shift result in the processing step 3 is transmitted as the first data of the ALU 50.
At the same time, the cumulative addition register ΣR60 is selected for the ALU input (2) line, and the rounding / addition result of A and B in the processing step 3 is transmitted as the second data of the ALU 50.
At the same time, a signed addition operation with a carry-in function with the carry-in as a latch r40 is designated for the ALU 50.
With the above control, in processing step 4, the ALU 50 rounds the 1 bit on the LSB side when digitizing C (15.17) to B (16.16), and the digitized A in processing step 2 (16.16) and B (16.16) are added to the addition result at the same time and output to the ALU output latch 80.
[Processing step 5]
ALU output latch 80 is selected for the RF write line.
For the general-purpose register file 20, an address for storing X (16.16) is designated by RFA1, and writing is designated.
With the control as described above, in processing step 5, the rounding process is performed on (16.16) for A, B, and C, and the added result is output to the general-purpose register file 20, and the target X (16.16) is output. )
As described above, the addition of a plurality of data having different fixed-point positions can be processed with the processing step equal to the number of data and the overhead of two steps for the pipeline, and rounding to the rounded bits generated by digit alignment is performed. Processing steps for processing can be eliminated.
Next, a detailed circuit configuration of the shifter 10 in FIG. 1 will be described.
FIG. 2 is a block diagram showing a detailed circuit configuration of the shifter of FIG.
In FIG. 2, a barrel shifter 100 shifts n-bit data of a shifter input line according to a control signal and outputs n bits.
Of the control signals, the arithmetic shift / logical shift selection signal is not particularly limited, but 0 indicates an arithmetic shift and 1 indicates a logical shift to the barrel shifter 100.
The number of shift bits is not particularly limited, but is a signal (value m) obtained by encoding ± n in 2's complement format, and positive indicates the number of left shift bits and negative indicates the number of right shift bits.
The rounding mode selection signal is a signal instructing the rounding mode to the rounding evaluation circuit 110 and is not particularly limited. However, the rounding mode selection signal is 2 bits, B′00 is rounded in the −∞ direction, B′01 is rounded in the + ∞ direction, B '10 indicates rounding in the 0 direction, and B'11 indicates rounding to the nearest value. (B 'is a prefix to represent binary numbers)
Here, -∞ direction rounding means rounding to the nearest value (the closest value that satisfies the condition among the values that can be expressed by the fixed-point position of the output data) that is not larger than the true value (value represented by the input data). The rounding mode of the scheme.
The + ∞ direction rounding is a rounding mode that rounds to the nearest value that is not greater than the true value.
The zero-direction rounding is a rounding mode in which rounding is performed to the nearest value that is not larger than the absolute value of the true value.
Nearest rounding is a rounding mode that rounds to the nearest value unconditionally. However, when the two nearest values are equidistant from the true value, the LSB is rounded to the nearest value that becomes “0”.
When the indication of the shift bit number m is the right shift bit number (m <0), the rounding evaluation circuit 110 converts the lower | m | bit (that is, the bit to be truncated) of the input data into the shift result (barrel shifter 100). In the rounding mode indicated by the rounding mode selection signal, it is evaluated whether 1 addition is necessary for rounding to 1). Output.
FIG. 3 shows a truth table of operations in the rounding evaluation circuit 110 of FIG.
Based on the truth table shown in FIG. 3, the 1-bit output signal R as an evaluation result is expressed as a logical expression for each rounding mode as follows.
▲ 1 ▼ -∞ rounding: R = 0
(2) + ∞ rounding: R = (logical sum of bits to be rounded down)
= (OR of input data | m | -1 bit to 0th bit)
(3) Rounding to 0: R = (input data is negative) ∩ (logical sum of bits to be rounded down)
= (MSB of input data) ∩ (input data | m | -1 bit to 0th bit OR)
(4) Round nearest value: R = (Most significant bit of data to be rounded down)
｛{((Bits excluding the most significant of the data to be rounded down) ∪ (bit that becomes the LSB of the output data)}
= (Input data | m | -1 bit) ∩ {(logical sum of | m | -2 bits to 0th bit) ∪ (| m | bit of input data)}
Here, in the above logical expression, “∪” means a logical sum, and “∩” means a logical product. The “i-th bit” indicates a bit at a position of number i when the LSB of the input data is 0 and the MSB is n−1 and each bit is numbered with an integer from 0 to n−1.
As described above with reference to FIGS. 2 to 3, since the rounding function is provided in the shifter 10, the only terminals added to the shifter block are the rounding mode selection signal and the 1-bit output signal as the evaluation result. For example, it is possible to minimize inter-block wiring when a circuit is mounted on a semiconductor substrate while being divided into blocks. Furthermore, even if it corresponds to a plurality of rounding modes, it is possible to share logic such as (logical sum of | m | −2 bits to 0th bit) in the above logical expression, thereby suppressing an increase in mounting area. There is an effect that can be done.
Next, a configuration of a SIMD type parallel DSP including a plurality of processors configured to include the circuit configuration of FIG. 1 and a single control unit that controls these processors will be described.
FIG. 4 is a diagram showing a configuration of a SIMD type parallel DSP including the circuit configuration of FIG. 1, and is configured on, for example, a semiconductor substrate.
In FIG. 4, the control unit 200 is configured to include a program execution control unit 220 including a program memory 210 and a data control unit 240 including a data memory 230, although not particularly limited.
These program memory 210 and data memory 230 can input / output data from the outside, and can perform information processing according to a calculation procedure (calculation algorithm) set from the outside.
The processor array 250 includes a plurality of processors 260 having the same configuration, and all the processors 260 are connected to the control unit 200 by a common data bus via an instruction bus, a broadcast data bus, and a tristate buffer.
Further, each processor 260 receives a processor selection signal common to the control of a tristate buffer provided corresponding to each processor 260, and a single processor 260 is always selected by the control unit 200.
The processor 260 includes a processor control unit 270 and a data operation execution unit 280.
The data calculation execution unit 280 can have, for example, the circuit configuration illustrated in FIG.
The processor control unit 270 controls the data operation execution unit based on an instruction given from the control unit 200 via the instruction bus.
The command output by the program execution control unit 220 in the control unit 200 in synchronization with the processing steps is, for example, a VLIW (Very Long Instruction Word) system, and the operation of each unit is controlled horizontally. That is, a field corresponding to each part is provided in each step command output by the control unit 200, and a plurality of functional blocks can be controlled horizontally in one step.
Of the above instructions, an instruction for the processor 260 (processor instruction field) is transmitted to all the processors 260 via the instruction bus. That is, the control unit 200 controls all the processors 260 with the same command.
The processor instruction field transmitted to the processor 260 is transmitted to the processor control unit 270 in the processor 260.
The processor control unit 270 operates in accordance with an instruction (processor control unit instruction field) for the processor control unit 270 in the transmitted processor instruction field, and converts an instruction (data operation execution unit instruction field) for the data operation execution unit 280 into data. This is transmitted to the calculation execution unit 280.
At this time, if there is an address mask execution instruction in the instruction in the processor control unit instruction field, the processor control unit 270 masks all the write instructions in the data operation execution unit instruction field with the negation of the processor selection signal. To the data calculation execution unit 280. Thus, one of the processors 260 can be selected and operated. For example, data specific to each processor can be set in the general-purpose register file 20 in the data operation execution unit 280.
In addition, a condition code signal (CC) is input to the processor control unit 270 from the data calculation execution unit 280. When there is a group mask execution instruction in the processor control unit instruction field, the processor control unit 270 masks all the write instructions in the data operation execution unit instruction field with the specified condition code signal. And transmitted to the data calculation execution unit 280.
The condition code signal is not particularly limited, but is a signal indicating the calculation state of the data calculation execution unit 280, a carry (carry out) signal output from the ALU 50 in FIG. 1 via the latch CO70, Although not shown in FIG. 1, the sign (data MSB) signal output from the ALU 50 via the latch 80, the zero (asserted when the operation result is 0) signal, and the overflow (not shown in FIG. 1) MSB carry signal and MSB-1 bit carry signal exclusive OR) signal.
As a result, an operation according to the internal state of the processor 260 is possible. For example, only the processor 260 whose operation result is negative is group-masked, and the absolute value is obtained by inverting the sign of this data by subtraction from 0. Conditional execution is possible.
The data operation execution unit instruction field transmitted to the data operation execution unit 280 in the processor 260 includes a shifter instruction field for the shifter 10, an ALU instruction field for the ALU 50, and a general purpose register file instruction field for the general purpose register file 20. FIG. The rounding process exemplified in the above processing steps 1 to 5 can be realized by controlling each functional block of the circuit configuration described.
Here, the rounding mode selection signal for the rounding evaluation circuit in the shifter shown in FIG. 2 is controlled by the rounding mode selection register RMR 290 provided in the processor control unit 270. In the rounding mode selection register RMR 290, data in the broadcast data bus is written when there is an RMR write instruction by an instruction in the processor control unit instruction field.
At this time, although not particularly limited, since the rounding mode selection signal shown in FIGS. 2 to 3 is 2 bits, the rounding mode selection register RMR 290 has a 2-bit configuration, and the lower order of n (for example, 32) bit data input from the broadcast data bus. Two bits are written.
Since the rounding mode has few applications to be changed for each processing step, it is not necessary to provide a rounding mode selection field in the instruction bus, and register setting by the rounding mode selection register RMR 290 can be performed. The effect of reducing the increase in bus width is obtained.
The calculation result of the processor 260 is fetched to the outside by selecting the desired processor 260 with the processor selection signal, so that the tri-state buffer 300 of the processor 260 is in the drive state and is sent to the control unit via the data common data bus. It is done by being output.
As described above, in the SIMD parallel DSP semiconductor device shown in FIG. 4, a single instruction and data output from one control system are operated in parallel with specific data held by a plurality of processors 260. By performing the processing, it becomes possible to process a parallel algorithm based on addition and subtraction at high speed by an operation based on an appropriate rounding process.
In the embodiment described above, the explanation has been made focusing on the rounding process of the present invention, but it goes without saying that various modifications can be made according to the purpose of use.
For example, in each processor of the above SIMD type parallel DSP, data unique to each processor can be obtained by adding a storage means for designating the number of shift bits of the shift operation.
FIG. 5 shows an embodiment in which a storage means for designating the number of shift bits is added to the shifter according to the present invention described with reference to FIGS.
In FIG. 5, the shift bit register SBR400 as the storage means is composed of the number of bits necessary for expressing the number of shift bits in the shifter shown in FIG. 2 (for example, 6 bits when n = 32), Data is set in response to the write instruction added in the execution unit command field.
Data to be written to the shift bit register SBR 400 is not particularly limited, but is data in which output data of the ALU 50 is transmitted via the overflow processing circuit 410. The overflow processing circuit 410 inputs n-bit data output from the ALU 50 as a binary integer in 2's complement format, and rounds the upper bits to a binary integer in 2's complement format of the number of bits constituting the shift bit register SBR400. Output.
That is, when the number of constituent bits of the shift bit register SBR400 is 6 bits, the value is output when the output of the ALU 50 is −31 to 31, but when the output of the ALU 50 is 32 or more (positive overflow). 31 is output, and when the output of the ALU 50 is −32 or less (negative overflow), −31 is output.
Also, the output of the shift bit number to the shifter 10 is selected by the selector 420 from the instruction in the data operation execution part instruction field and the shift bit register SBR400. The control of the selector 420 is not particularly limited. For example, the shift bit number specified by the instruction in the data operation execution unit instruction field is a negative maximum value (-32 when the shift bit number is 6 bits). In some cases, the SBR output is selected. In other cases, the data compare circuit 430 selects the shift bit number specified by the instruction in the data operation execution unit instruction field. Are switched by "0" and "1".
In the embodiment described above, in order to perform high-speed processing of parallel algorithms such as image processing and neural networks, the processor is further distributed with multipliers for high-speed processing of product-sum operations and processor-specific data. A local memory for placement may be provided.
FIG. 6 shows a circuit configuration in which a multiplier and a local memory LM are added to the circuit configuration shown in FIG. 1 as another circuit configuration example of the data operation execution unit in the processor in FIG.
In FIG. 6, a multiplier 500 includes a first n-bit data transmitted from the shifter output latch 30, the general-purpose register file 20 or from the outside via a multiplier input (1) line, and a multiplier input. (2) Multiply the second n-bit data alternatively transmitted from the general-purpose register file 20 or the output latch 520 of the local memory LM510 via the line, and the result is 2n bits (when n is 32) 64 bits) data is transferred to the multiplier output latch 530. Here, selection of data on the multiplier input {circle around (1)} line and the multiplier input {circle around (2)} line is made by, for example, a control signal given from the outside, although not shown.
The output of the multiplier output latch 530 is transmitted to the shifter input line.
The local memory LM510 is composed of an n-bit × multiple-word RAM (Random Access Memory). Although not shown, for example, the shifter output latch 30, the ALU output latch 80, or the external memory LM510 responds to an external control signal. The n-bit data transmitted alternatively from is written in the address transmitted from the local memory pointer register LMPR 550 in the LM address control unit 540. Alternatively, the data stored at the address is read to the local memory output latch 520 at the subsequent stage.
The output of the local memory output latch 520 is transmitted to the multiplier input (2) line, shifter input line, and ALU input (2) line.
The LM address control unit 540 includes a local memory pointer register LMPR 550 that outputs a write / read address of the local memory LM510. Alternatively, the data transmitted from the ALU output latch 80 is written.
The output of the local memory pointer register LMPR 550 is transmitted to the RF write line in addition to the address to the local memory LM 510 and can be saved to the general register file 20 and can be operated by the ALU 50.
With the addition of the multiplier 500, the local memory LM 510, and the LM address control unit 540, the change in the functional block shown in FIG. 1 corresponds to the output data width of the multiplier 500 and the input data width of the shifter 600. Is an increase.
For 2n bits of data width of the shifter input line, when the data selected by the control signal is n-bit data of the general register file 20, external or local memory output latch 520, the MSB side n bits of the shifter input line At this time, n bits on the LSB side of the shifter input line become 0.
FIG. 7 is a block diagram showing a detailed circuit configuration of the shifter of FIG.
In FIG. 7, a barrel shifter 610 performs a shift operation similar to that of the barrel shifter 100 shown in FIG. 2 based on the MSB of 2n-bit input data, and outputs n bits. The difference from the barrel shifter 100 described with reference to FIG. 2 is that when overflow does not occur in the left shift, the output of the number of LSB side shift bits is 0 in FIG. 2, whereas the barrel shifter 610 in FIG. The upper bit of the lower n bits of the data is used.
FIG. 8 shows a truth table of operations in the rounding evaluation circuit shown in FIG. Since the above-described barrel shifter 610 in FIG. 7 shifts the input 2n-bit data with reference to the MSB and outputs n bits, truncation bits are generated even in the left bits (including 0-bit shift). Corresponding to this, the rounding evaluation circuit 620 in FIG. 7 performs the truncation bit in the 2n-bit input data regardless of the shift direction of the shift operation (that is, always) with respect to the operation of the rounding evaluation circuit 110 in FIG. The point to evaluate is different.
As described above, a processing step can be performed by adding a relatively small circuit to an information processing apparatus that processes a parallel algorithm such as image processing or a neural network at high speed with a SIMD parallel DSP including one control system and a plurality of processors. The rounding function can be incorporated without any increase in the number, and this achieves the object of the present invention to efficiently improve the numerical calculation accuracy of an information processing apparatus using a fixed point arithmetic unit.
FIG. 9 shows a configuration in which the rounding process of the present invention is applied to a conventional data processing apparatus.
In FIG. 9, the processor constituting the data processing device includes an arithmetic unit 11, a local memory unit 12, and a tristate buffer 13.
The arithmetic unit 11 includes a processor control circuit 1101 including the rounding mode selection register RMR290 of the present embodiment, latch circuits 1102, 1105, 1107, 1112, and 1114, a general register file 1103, a multiplier 1104, and a CO register of the present embodiment. 70, a condition code register (CCR) 1106, an accumulation register 1108, an ALU (arithmetic logic unit) 50 and selector 90 of this embodiment, an SBR (shift bit register) 1110, a shifter 10 and touch r40 of this embodiment. The difference absolute value calculator 1113 is included.
The local memory unit 12 includes local memories (LM0, LM1) 1202, 1204, an address calculation circuit 1201 for generating an address signal for the local memory 1202, an address calculation circuit 1203 for generating an address signal for the local memory 1204, a selector 1205, 1206, 1207, 1208, 1209.
In the operation of the data processing apparatus shown in FIG. 9, the shifter 10, the latch r40, the ALU (arithmetic logic unit) 50, and the selector 90 operate as described in this embodiment. The operation is the same as that of the data processing apparatus disclosed in Japanese Patent Application No. 2003-23076.
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
The effects obtained by typical ones of the inventions disclosed by the present invention will be briefly described as follows.
Since the shifter has a rounding evaluation function, the only terminal added to the shifter block is the rounding mode selection signal and the 1-bit output signal as the evaluation result, and the overhead of the rounding process can be reduced with an efficient circuit configuration. The numerical calculation accuracy of the information processing apparatus using the fixed point arithmetic unit is efficiently improved.

The present invention can be applied to a single processor, that is, a general DSP, and can be applied to a semiconductor device equipped with a DSP such as a SIMD type parallel DSP.
Further, the present invention can be applied to a circuit configuration for processing floating point arithmetic.
Furthermore, the present invention can be applied to an execution unit (Execution Unit) of a CPU represented by an SH microcomputer.
In addition, the present invention can be applied to all digital signal processing apparatuses that require rounding.

Claims (8)

A processor including a shifter having a right bit shift operation function, and an ALU having a carry-in function for adding 1-bit data to the least significant bit in addition of two input data;
A data processing apparatus comprising a control unit for controlling the processor with a single instruction,
The shifter outputs the data of the shift operation result, and at the same time, performs rounding evaluation on the bits that are discarded in the case of right bit shift, and indicates whether or not “1” addition is necessary for the least significant bit of the shift operation result A rounding evaluation means for outputting data;
The ALU is characterized in that one of two input data is output data of the shifter, and data used in the carry-in function is 1-bit data output from the rounding evaluation means of the shifter. 2. The data processing apparatus according to claim 1, wherein the right shift operation in the shifter and the addition of the carry-in function in the ALU are operations corresponding to two's complement data. 3. The data processing according to claim 1, further comprising a rounding mode selection unit, wherein the rounding evaluation unit performs rounding evaluation corresponding to each of a plurality of rounding modes selectable by the rounding mode selection unit. apparatus. The said processor consists of two or more, The said rounding mode selection means selects a rounding mode by the data storage means provided in each of the said several processors, The any one of Claim 1 thru | or 3 characterized by the above-mentioned. Data processing equipment. 5. The data processing apparatus according to claim 1, wherein the rounding evaluation is a logical sum of bits rounded down by the right bit shift. 5. The data processing apparatus according to claim 2, wherein the rounding evaluation is a logical product of a logical sum of bits rounded down by the right bit shift and a sign of shift operation data. 6. . The rounding evaluation is performed by calculating the logical sum of the bits other than the most significant bit of the bits that are truncated by the right bit shift and the least significant bit of the shift operation result, and the most significant bit of the bits that are truncated by the right bit shift. 5. The data processing apparatus according to claim 1, wherein the data processing apparatus is a logical product of 8. The data processing apparatus according to claim 1, wherein the data processing apparatus is configured on one semiconductor substrate.

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