JPH10105150A - Character storage circuit and display control unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the display control unit which improves the display quality of characters displayed on a screen and makes a multiple display of' characters without increasing the capacity of a character memory. SOLUTION: The control unit is equipped with a character memory 4 which store patterns corresponding to character codes and is equipped with a read data path for reading data of 2<k> lines including a line specified with a line number at the same time together with character codes and data, on the said specified line, 2<k> latches 20 to 23 which latch read data from the character memory 4 by every (n) bits, 2" PS converting means 24a to 24d which convert the contents of the latches into serial data, a smoothing means, and rearranging means 25a to 25d which rearranges the outputs of' the PS converting means according to the display vertical positions of characters to be displayed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device for displaying operation data and information of a device on a display screen using a pattern read from a character memory storing characters and figures in a bit map format.

[0002]

2. Description of the Related Art In video equipment such as a television receiver and a video tape recorder, a channel display and a volume display are displayed at the time of channel operation and volume adjustment. On Screen Display (On Screen)
n Display (hereinafter abbreviated as OSD) function.

Until now, it was sufficient to simply display the status of the device itself, such as channel position and volume display. However, in recent years, as the number of receivable broadcast services has increased, guidance displays have been provided to provide a better operation environment. And help functions have been sought. Also, with the spread of personal computers, the demand for improving the character quality of the OSD has been increasing.

[0004] A display control device for realizing the OSD function used in conventional video equipment has a vertical and horizontal display screen for displaying characters and figures on the display screen without using an expensive bitmap image memory. Display memory (also called text memory) corresponding to the squares divided in a grid pattern
It has. Then, the character code is read from the display memory specified in the horizontal and vertical cells corresponding to the scanning position of the television signal. Next, the display data corresponding to this character code is read out for one line from the character pattern data in the character memory (also called font memory) and superimposed on the video signal, thereby displaying characters and graphics on the screen.

By the way, if the number of dots in the character memory is smaller than the size of the displayed character, jaggies called jaggies appear when displaying oblique lines. In order to make such jaggedness inconspicuous and improve character quality, increase the number of points constituting each character,
That is, it can be realized by increasing the capacity of the character memory.

Further, a technique for improving the character quality without increasing the capacity of the character memory has been studied. For example, there is a "smoothing circuit" (Japanese Patent Application Laid-Open No. 60-202475) as a technique for improving the quality of displayed characters. FIG. 11 shows the configuration of this smoothing circuit, and FIG. 12 shows a timing chart.

In FIG. 11, reference clocks CP and C
The basic timing of this circuit is generated by a bit counter for counting P, and a byte counter, a line counter, and a field counter sequentially connected in series to the bit counter.

The byte counter 714 shown in FIG.
Indicates a period indicating the data address (X) of the character to be displayed, during which the memory address control in the vertical direction is applied at the output timing of the line generation counter 720 shown in FIG. Line (Y)
And the line data (Y-1, Y + 1) before and after it.

Hereinafter, the smoothing processing operation will be described step by step. Character memory (image memory) 71 in FIG.
FIG. 12 shows a part of the address of the character pattern read from 0.
It is held at the rising edge of the ADLP signal in (d). Next, according to the ADCK signal of FIG.
A line of a character pattern stored in the character memory 710 is specified, and one line of pattern data is read. The read data is put on the data bus, and the data latch timing signal PLP1 (FIG. 12 (f)), PLP2
(FIG. 12 (g)), the data is temporarily stored in the latches 722 and 726. The data stored respectively and the data currently on the data bus are converted to an inverted PLP signal (FIG. 12 (h)).
PS conversion circuits 724, 72 at the rising timing of
Write to 8,730. The switches 740 and 742 are used to replace the lines before and after the line on which the smoothing processing for interlace display is performed due to the processing circuit of the smoothing unit 750.

The operation of the circuit will be described with reference to FIG. Character memory 7 in FIG.
One of the bit image data 131 (FIG. 13) stored in No. 10, the data A one line before and the data C after one line are sequentially arranged in the horizontal direction with respect to the line B corresponding to the current horizontal scanning line. read out. The read data 132 is input to the latches at different timings, but is input at the same timing 133 for the parallel-to-parallel conversion, and the data 134 is sent to the smoothing unit 750 to obtain a smoothed signal 135. This data is displayed on the screen.

Here, as an example of the image display of the operation guide recently required, there is a display in which a part of an instruction manual as shown in FIG. 7 is expressed using various colors. Focusing on the button display among them, especially when the color of the button and the color of the character are different, only a character expression with conspicuous unevenness as shown in FIG.

Since this is a combination of the outer frame indicating the shape of the button and the numeral therein, it is stored in the character memory of FIG. 11 as bit image data in which the color can be designated in bit units in advance. Had to be.

In FIG. 12, since the data must be read three times during the period of displaying one character in order to perform the smoothing process, the button shape and the number are stored as different character patterns. Even if an attempt is made to superimpose the outer frame and the number during the display as shown in FIG. 8B, there is no period for reading out the button shape data.

Therefore, as shown in FIG. 8A, to display channel operation buttons, there are 12 fonts in a style in which button shapes and numbers (1 to 12) are superimposed in advance,
Apart from this, it is necessary to write all the explanatory numerals (1 to 12) in the character memory.

In this example, there is no period during which one character is displayed and there is no period during which another character is read out. Therefore, multiplex display of characters is abandoned, and a font in which two characters are superimposed in advance is used as the contents of the character memory. By preparing them, they are trying to improve their expression ability.

In the "smoothing processing circuit" of Japanese Utility Model Application Laid-Open No. 62-89054, data read from the character memory is delayed by a 1H shift register.
This is to obtain 1H data before and after the reference line. FIG. 14 shows a block diagram. In this example, the data for one line before and after one line for the smoothing process is obtained by the 1H shift register. Therefore, compared to the previous example, a period for reading out another character data can be made during the period in which one character is displayed. it can.

However, since the 1H shift register used here has a bit width, the circuit scale becomes considerably large. The clock is faster to read out data for two characters and to display characters as fine as possible, so a bit width of 8 bits or more is considered necessary, taking into account the memory access time. It is not used in general display control devices.

There is also a conventional example for displaying a plurality of characters on the OSD in a superimposed manner. For example, US Pat. No. 5,420,610, “Screen Display Circuit A
pparatus ". FIGS. 15 and 16 show configuration diagrams, and FIGS. 17 and 18 show display examples.

The display of FIG. 17, that is, the superposition of two types of characters is realized by the configuration of FIG.
However, the configuration shown in FIG. 15 has a configuration in which two display control devices are provided, and thus has a disadvantage that the circuit scale becomes large due to having redundant character data.
It is sufficient if the same characters are not included in the characters to be superimposed, but it may be necessary to superimpose them depending on the content to be displayed.

The configuration shown in FIG. 16 is suitable for displaying different data as shown in FIG.
When the display as shown in FIG. 17 is performed, the first font R
The data may be transferred from the OM in advance. However, considering that the RAM is incorporated in a one-chip integrated circuit, the memory capacity of the RAM that fits in the area of the memory capacity of the ROM is small. Also,
Since it is a RAM, it is necessary to transfer all data to be displayed from another memory, that is, a program memory of the CPU or an external device.

Nevertheless, if this conventional example is used, the display as shown in FIG. 9 can be performed, and the display pattern shown in FIG. 10A is expressed by overlapping the fonts shown in FIG. As a result, the amount of data stored in the character memory can be significantly reduced.

According to the configuration in which the two display control devices are combined as described above, characters can be multiplexed and displayed, but the number of multiplexed character memory blocks is required and the circuit scale cannot be reduced. .

[0023]

As described above,
In the above-described conventional display control device, in order to display characters or graphics in a superimposed manner, it is necessary to store font data in different character memories in advance, thereby increasing the capacity of the character memory. Was.

The character memory is stored in a ROM (Read Onl
y Memory), it is necessary to store data so as not to overlap as much as possible.
Memory), it takes time to transfer data from the ROM as needed, and there is a problem that the number of characters that can be stored is smaller than that of the ROM.

In view of the above problems, it is an object of the present invention to improve the display quality of characters displayed on a screen without increasing the capacity of a character ROM, and to provide a display control which enables multiple display of characters. It is to provide a device.

[0026]

To achieve the above object, the present invention has the following arrangement. That is, according to the first aspect of the present invention, in a character storage circuit for storing a character or graphic pattern corresponding to a character code in a bitmap format arranged in a matrix, data of a plurality of rows constituting the matrix are simultaneously read. The gist of the present invention is to provide a read data path capable of reading data.

According to a second aspect of the present invention, in a character storage circuit for storing a character or graphic pattern corresponding to a character code in a bitmap format arranged in a matrix, each is represented by k-bit data. The gist of the present invention is that a character or graphic pattern is stored as a group of points in m rows and n columns, and a read data path that can read data in each row with a data width of n × k is provided.

According to a third aspect of the present invention, a character or graphic pattern corresponding to a character code is stored in a bitmap format arranged in a matrix of m rows and n columns, and designated by a character code and a line number. Tagyo with data, 2 temporarily stores the character memory circuit having a read data path of 2 ^k rows of data can be read at the same time, the read data of the character memory circuit including the line ^k
N-bit temporary storage means, temporary storage control means for selecting one data from data read twice consecutively from the character storage circuit and storing the selected data in the n-bit temporary storage means, respectively, 2 ^k n-bit parallel-serial conversion means respectively connected to the temporary storage means, smoothing means for generating a display signal in which oblique lines are smoothed from serial inputs of adjacent rows of 2 ^k , interposed between the conversion means and the smoothing means, in accordance with the display vertical position of the character or graphics display, and rearrangement means replace the 2 ^k n-bit parallel-serial conversion means connecting line between said smoothing means, This is a display control device having a gist.

According to a fourth aspect of the present invention, a character or graphic pattern is stored as a set of points in m rows and n columns in which each point is represented by k-bit data, and the data in each row is represented by n × k data. A character storage circuit readable by a width, k n-bit temporary storage means for temporarily storing data read from the character storage circuit, and k parallel / serial converters respectively connected to the temporary storage means And a control unit for instructing the parallel-serial conversion unit to transfer data at a desired timing from the temporary storage unit.

According to a fifth aspect of the present invention, in the display control device of the fourth aspect, the k-bit data is data for specifying a color for displaying each point, and is a maximum of 2 k powers. The gist is to display color.

According to a sixth aspect of the present invention, in the display control device according to any one of the third to fifth aspects, two or more characters or figures are displayed during one character or figure display period. The gist is to have a function of reading from the storage circuit.

According to a seventh aspect of the present invention, in the display control device according to any one of the third to sixth aspects, a part or all of the character storage circuit is rewritable temporary storage means, And connection means for connecting a second character storage circuit for storing data for displaying a character or a graphic represented by a group of points in m rows and n columns, which is incorporated in the integrated circuit. Is the gist.

According to the present invention having the above structure, the data bus width of the character storage circuit is increased by the number of times required for smoothing processing and displaying one line of a dot-colored character.
Increase the amount of data read each time. Next, a timing signal for selecting necessary data from the read data is generated and input to a P / S (parallel / serial) converter at a predetermined timing. By rearranging the outputs in a predetermined order, a readout circuit common to character smoothing processing and dot coloring character display processing is used.

According to the present invention, a timing for reading out a plurality of character patterns occurs during a period in which one character is displayed, so that multiple display of characters can be performed, and display in which a plurality of characters are combined can be performed, thereby improving display quality. Can be done.

Further, the same data in the memory can be read out even when it is necessary to draw the same character in a superimposed manner. Therefore, there is no need to duplicate the data in the memory and to prepare a font in an overlapping format, thereby reducing the capacity of the character memory. Can be reduced.

[0036]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a display control device according to the present invention. In the figure, a display control device includes a timing generation circuit 1, a memory control circuit 2, a display memory 3 in which character information to be displayed is stored in a character code, and a character memory 4 in which character or graphic pattern data is stored. And the parallel-to-serial conversion block
/ S conversion) 5, a smoothing processing circuit 6, a color memory 7, a character memory 4, and a bus interface circuit (hereinafter, the bus interface is abbreviated as BUS-I / F) 8 for interfacing with the bus. A CPU 9 using a microprocessor, an extended interface 10, an extended character memory 11, an address
A control signal bus 12 and a data bus 13 are provided.

The timing generation circuit 1 generates a timing signal as an operation reference of the entire display control device from a horizontal synchronization signal H and a vertical synchronization signal V of the television and a clock CLK for operating the circuit. In the timing signal output from the timing generation circuit 1, the vertical position,
That is, the displayed line number and the counter value indicating the horizontal position are given to the memory control circuit 2 and the display memory 3
Is converted to a control signal.

The display memory 3 stores a character code of a character to be displayed corresponding to a coordinate position on the display screen and modification information for the character. That is, information on where, what character, what color, and what attribute (blink designation, tilting the character, underlining, etc.) on the display screen is stored beforehand by the CPU 9 in a ROM (Read Only Memory). Is written in accordance with the microcomputer program written in.

When data such as a character code number is read from the display memory 3 by the signals indicating the vertical and horizontal positions outputted from the memory control circuit 2, the character code number is given to the character memory 4 and the designated character is designated. Is converted to bit information expressing This bit information is converted from parallel data to serial data by the P / S conversion block 5. Here, the bit string converted to serial data is replaced by the smoothing processing circuit 6 with a bit string that smoothly expresses an oblique line, and is converted into RGB color data by the color memory 7 and displayed on the screen.

The color memory 7 shown in FIG.
CPU 9 via control signal bus 12 and data bus 13
, And the data of the color to be colored can be rewritten according to the scene under the control of the CPU 9. Of course, when the number of colors is limited and colors fixed in advance are used, there is no need to connect the color memory 7 and the CPU 9.

The bus interface 8, the extended interface 10, and the extended character memory 11 are not essential components in the present embodiment.

When at least a part of the character memory 4 is a RAM, the bus interface 8
9 is for rewriting the RAM section of the character memory 4.

The extended character memory 11 is used to add a character that could not be stored in the character memory 4. The extended character memory 11 can be connected to the buses 12 and 13 via the extended interface 10 for connecting with a small number of control lines. Connected.

Next, the operation of the display control device having the above-described blocks will be described. First, an operation in a case where characters subjected to smoothing processing are displayed in an overlapping manner will be described. The details of the character memory 4 and the P / S conversion block 5 are shown in FIG.

In FIG. 2, the P / S conversion block 5
Latches 20, 21, each having an 8-bit data width,
22, 23 and P / S converters 24a, 24b, 24c,
24d and 4-way selectors 25a, 25b, 25
c, 25d.

FIG. 2 shows an example in which one line of pattern data of a matrix of characters or graphics (hereinafter, also referred to as graphics) includes 8 bits. The data read from the character memory 4 is output to a 32-bit bus line having a bit width four times as large as the data for one row.

The character memory 4 is provided with an area address storing the bit image of the designated line code of the character based on the character designation code and the line designation code. Conventional general character memories output one line of 8-bit data for a given address.

The character memory used in the present invention has a bus width four times as large as that of the conventional one, and one data read out at one address is configured by combining data of four lines, and a character bit image is read. Are discarded and supplied to the character memory 4.

The structure of the P / S conversion block 5 is such that the bus is equally divided into four parts corresponding to the structure of the character memory 4, and the latches 20, 21, 22, 23, each having 8 bits.
Connected to. The data on the bus is latched at the timings (a), (b), (c) and (d) supplied to the respective latches, and the data is sent to the P / S converters 24a to 24d in accordance with the display timing. Is passed.

The P / S converters 24a to 24d output data of one bit at a time in accordance with the display timing, and send the data from the terminals A to D to the smoothing processing circuit by the selectors 25a to 25d. .

By the way, in order to perform a character smoothing process, bit image data of a line to be displayed and lines before and after the line to be displayed (up and down at positions on the screen) are required. Specific smoothing processing and the like are disclosed in JP-A-60-202475, "Smoothing Circuit" and JP-A-62-89054, "Smoothing Processing Circuit".

Further, since the P / S converter 501 shown in FIG. 2 has only one block corresponding to one character, such a block is used when multiple characters subjected to smoothing processing are displayed. Are required.
In the illustrated example, up to two characters subjected to smoothing processing can be displayed. Referring to FIG. 1, a block which increases when characters are superimposed and displayed will be described in which the P / S conversion block 5 and the smoothing processing block 6 are almost doubled.

However, although the number of circuits is increased, the circuit scale can be reduced as compared with expanding the character memory 4 for storing bit images of characters used for screen display. In particular, a control device for displaying characters indicating operation and information of a video device such as a television is integrated into one chip including the character memory 4, and generally, even if the number of control circuits increases, the capacity of the memory increases. It does not matter.

The operation of reading from the character memory 4 in the operation of the display control circuit will now be described with reference to FIG.

In the present invention, a smoothing process may be performed, and four lines of data are read at a time. However, although the memory is configured to collectively read data for four lines, it is not suitable for smoothing processing. That is, in the smoothing process, it is necessary to shift the display of characters from the upper line to the lower line one line at a time, but the data read from the memory cannot be shifted one line at a time and is in units of four lines.

Therefore, in the present invention, data is read twice in order to perform the smoothing process, and a total of eight lines of data are read. Four lines including a line to be displayed and lines before and after the selected line are selected from the selected lines, and a smoothing process is performed.

From the bit image 30 stored in the character memory 4, the bit images (1) and (2) of the 4-line portion are read, respectively. For example, if the necessary data is four data of A, B, C, and D out of 31 and 32, the data is used in order from the top using A, B, C, and D and selectors 25a, 25b, 25c, and 25d. The data 33 is obtained by rearrangement and P / S conversion. Thereafter, data 34 is obtained by smoothing processing, and 35 characters are displayed on the screen.

Next, a configuration for enabling multiple display of the same character without using a high-speed character memory will be described.

In FIG. 3, the characters to be displayed are described as bit image data in a matrix of 16 rows × 16 columns. P /
In order to reduce the circuit scale of the S converter, the horizontal data width to be read at one time is set to 8 bits. Therefore, in order to complete one line of one character, reading the left half and reading the right half of the character And two times.

Therefore, focusing only on the display of the left half,
The period 36 during which half of the characters are displayed is 1.12 μS. This is a size in which characters 35 to be displayed on the screen are arranged in 24 characters on the screen.

In general, as the capacity of the memory incorporated in the LSI increases (the number of character data), the wiring delay and the like increase, and the access time increases. At present, it is known that data can be sufficiently read if the cycle is 280 ns from the memory access time. In this case, the time required to read data once is 280n.
Since S is read twice, it takes 560 ns. Nevertheless, the period during which these data are displayed on the screen is 1.12 μS
Therefore, data for one character can be read.

FIG. 4 shows the timing so far. FIG.
The data 41 read from the character memory 4 is latched by the latches 20 to 23 in FIG. 2 by the timing signals 42 of (a) to (d). The latch timing signals (a) to (d) change according to the lines indicated by the timing signals in the table in FIG. In the table, n is a positive number.

The data latched by the latches 20 to 23 is input to the P / S converter 24 of FIG. 2 by a timing signal 43, converted into serial data 44, and replaced by data 45 by smoothing processing and output.

With such a configuration, it is possible to superimpose and display smoothed characters. Furthermore, since character data to be superimposed and displayed is read from the character memory at different timings, the same character can be superimposed and displayed. In particular, it is not necessary to create a superimposed character in advance and store it in the character memory. .

Next, a description will be given of a case where graphic characters are superimposed on each other, or a case where graphic characters and characters subjected to smoothing processing are superimposed on each other. The circuit configuration is the same as the above-described circuit configuration, and an embodiment will be described next.

In the above-described embodiment, the case where the characters to be subjected to the smoothing processing are superimposed and displayed has been described. Such a display control device has recently been able to display a character colored in units of one dot, such as an icon used for selecting functions of a personal computer.
Such a display can also be realized by the configuration of the above embodiment.

In order to perform the character smoothing display, it is necessary to generate different timing signals (a) to (d) for each line at the timing shown in FIG.

When the operation of the smoothing process is schematically represented, the data 51 in the character memory 4 in FIG.
For example, in the first reading, lines 5 to 8 are read,
Next, the data of the lines 9 to C is read. Among them,
The data represented by the solid circles is latched from the line data read out according to the display line, and the screen display 52 is obtained.
The data latch timing signals (a) to (d) of the data sets 53, 54, 55, 56 are 4n, 4n + 1, 4n +
2, 4n + 3 respectively.

When displaying a character colored in units of one dot, it is necessary to have color information for each dot, so that the circuit configuration is inevitably different. The colors to be displayed are 2 to the power of n. Here, the description will be made on the assumption that 16 colors, which is 2 to the fourth power, can be designated.

When the number of colors increases, rich color expression is performed by using as analog RGB output. At this time, there are those that output color data fixed in advance and those that can be freely changed according to the scene. However, in any case, the color information is converted from the color information to the displayed color by the last-stage color memory 7 in FIG. If the color information is a 16-color display, which of the 16 colors is displayed,
A number from 0 to 15 is specified. Then, the data is converted into color data to be actually displayed in the color memory 7.

By the way, the 16-color display here means the number of colors that are simultaneously generated in one screen, and if a different color palette is used when the screen is changed, another color can be expressed. Can also.

When displaying a character colored in dot units of the same size as the dots of the characters to be displayed, it is necessary to have color information for each dot.
It requires four times as much data as character data. This is schematically shown in FIG. The data 60 stored in the character memory 4 of FIG. 1 indicates the data amount of the left half of the character data 51 of FIG.

As described in the previous example, the character memory 4 of FIG. 1 reads four lines at a time,
All data read at one time is one line of data 6
Treat as 1. That is, the color of each bit is specified by the data of these four lines. Since four lines of data are required to represent one line,
With six lines of data, the number of lines obtained by the color conversion process is only four lines. In order to display the same size as a character, data four times as large as the data of one character is required.

Next, a case will be described in which graphic characters and character data are read out by changing the timing signal with the same circuit configuration.

The data read timing in this case will be described with reference to FIG. 4. In the case of a character that is colored in dot units, the memory is read out of "A" in the read cycle 41.
The data need only be read during the period of "E", and there is no particular need to read data during the period of "E". The data latch timing signals (a) to (d) need only be at the timing of 4n shown in the table. In the block of the P / S converter 501 in FIG.
The data latched by the data latch timing signals (a) to (d) may be output to the terminals A to D as they are. Since the smoothing processing circuit has a configuration corresponding to character data, it passes through without any processing.

In the case of a character colored in dot units, data is read out at one time, so that bit images of two or more characters can be read out while one character is displayed. Characters colored in units of dots can be superimposed and displayed. Furthermore, since the same configuration can be realized as a circuit for superimposing and displaying smoothed characters although the data format to be stored in the character memory is different, a character subjected to smoothing and a character colored in dot units are superimposed and displayed. It is also possible.

Next, a case will be described in which a character font is displayed in a multiplex manner so that a rich expression can be achieved with a small amount of data. With the above configuration, FIG.
Can be realized. When a number is displayed in a button as shown in FIG. 8, since it has not been possible to display a character pattern representing a button and a character pattern representing a number in a superimposed manner, as shown in FIG. It was necessary to store a pattern with a number inside the button and a pattern with only a number separately as bit images.

However, according to the present invention, since the outer frame of the button and the numeral can be combined at the time of display, the image representing the button is represented by a character that can be colored in dot units, and the character is smoothed by smoothing processing. 8 (b) can be displayed.
As a result, duplicate data stored in the character memory can be reduced.

Next, the CPU bus interface will be described. The character memory of the conventional display control device is generally a ROM (Read Only Memory),
It was also common that the CPU could not read data from the character memory. In particular, this was due to the fact that the bit image configuration of the character was different from that of the CPU bus and that the character memory had a large capacity and could not be loaded on the memory map of the CPU. Has increased,
One in which a character memory is arranged in a memory map of a CPU has also been developed.

As described above, arranging a character memory in the memory map of the CPU or providing a circuit for reading the character memory from the CPU requires that a part of the character memory be a RAM (Random Access Memory), and that the character memory be stored in advance. In order to express a motion by processing a part of the bit image data, the increase in the character memory is suppressed even if the expressive power is enhanced. For example, as an example of using a RAM for such a character memory, US Pat.
No. 20,610.

Now, in the case of the present invention, especially since the bus width of the character memory is wide, a functional circuit for converting the bus width is required.

The bus width conversion will be described with reference to FIG.
When the CPU reads data from the character memory 4, only the upper bits of the address output from the CPU except the lower 2 bits are connected to the character memory 4, and 32-bit data is read by one reading. Among them, the lower 2 of the address specified by the CPU
Depending on the bit, one-fourth 8-bit data of the 32 bits is selected. In this configuration, the character memory 4
The same applies to M.

A problem arises when data is written from the CPU. In this case, once the character memory 4
From the CPU, the data sent from the CPU is replaced with 8 bits out of the designated 32 bits, and then written again as 32-bit data. Since the memory access cycle of the CPU is longer than the minimum access timing of the memory, the data can be written at the same timing as when accessing the general memory from the CPU even if the data is read once and then written again. If necessary, there is no problem even if a wait is inserted in writing data to the memory.

Although the ROM and RAM inside the character memory are completely independent on the map of the CPU memory,
RO if part of PU map is used as window
The arrangement of M and RAM may be partially arranged in the same memory from the CPU, and switching by I / O control may be added from the CPU.

By the way, in this embodiment, 8
Although described with bit data, the bit image stored in the character memory used in the display control device is not always a multiple of 8 or 2n. Therefore, the BUS- shown in FIG.
The I / F 8 requires a process of converting the number of bits of the latch 20 into the data bus width of the CPU.

At this time, the missing bits on the CPU bus are filled with "0" or "1" data. This data is fixed to one of the display control circuits,
U has a configuration in which either “0” or “1” can be designated.

In particular, by reading data in the character memory from the CPU and writing data in the RAM of the character memory, a different character can be created only by rewriting a part of the character written in the ROM by program processing. Can be. Therefore,
The motion can be expressed by a small number of characters without requiring a data area occupied by a bit image of one character.

Next, an embodiment having the extended character memory shown in FIG. 1 will be described. A control block added to the first embodiment for extending bit image data of a character that cannot be stored in the character memory 4. In such a display control circuit, blocks 1 to 7 in FIG. 1 are generally housed in one integrated circuit. In addition, there is a type in which a CPU and a ROM and a RAM required for operating the CPU are incorporated. However, the number of characters in such an integrated circuit is limited, and is usually only about 500 characters. In order to support Japanese sentences, for example, teletext, alphanumeric characters, basic symbols, and corresponding kanji are considered. Data of about 3000 characters is required.

To respond to such a demand, it is necessary to connect a memory to the outside. However, the data width of the external memory is generally a multiple of 8, and the character data to be displayed and the bit structure Are different. In particular, in a configuration in which the bus width is expanded and the number of data read cycles is reduced as in the present invention, the expansion interface 10 is required because the bus width is completely different from that of an external memory. Due to external memory costs, this extended character memory is a general memory having a general bus width.

Therefore, the extension interface 10 is connected to the CPU
Although not shown in the drawing with the instruction from, the function of copying data directly to a predetermined address of the character memory
Transfer data at high speed. According to this function, data transfer can be performed at high speed, so that the time required for rewriting data can be reduced.

Even if such a transfer circuit is not provided, the character memory is stored in the character memory via the CPU buses 12 and 13.
Data can also be transferred by PU program processing. Regarding this data transfer, if at least one of the data transfers is possible, an external memory can be connected to increase the number of characters.

Further, all of the built-in character memories 4 may be RAMs (Random Access Memory). This is because, when character data is supplied from the outside, the external memory has a large capacity and it is not necessary to particularly have a few data inside.

As described above, when the internal character memory 4 is entirely a RAM, the number of characters written at a time is smaller than that of the ROM, but not only does the chip area not increase due to the unused character data, but also the screen size increases. The function of the control circuit of the display control circuit can be extended based on the number of characters that can be displayed at one time.

[0094]

As described above, according to the present invention, characters can be multiplexed and displayed, smoothing processing for improving the quality of characters and characters colored in dot units can be simultaneously and superimposedly displayed. Therefore, there is an effect that the displayed contents and quality are dramatically improved.

Furthermore, in the character memory, data duplication can be eliminated, so that many types of character and graphic pattern data can be stored with a small memory capacity, and the circuit size of the display control device can be reduced. It has the effect that it can be done.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a display control device according to the present invention.

FIG. 2 is a block diagram showing a main part of FIG.

FIG. 3 is a diagram for describing from character memory reading to screen display according to the embodiment of the present invention.

FIG. 4 is a timing chart for explaining a character memory data reading process according to the embodiment of the present invention;

FIG. 5 is a schematic diagram of data reading for smoothing processing in the embodiment of the present invention.

FIG. 6 is a schematic diagram of reading dot coloring data according to the embodiment of the present invention.

FIG. 7 is a diagram showing a sample of screen display according to the embodiment of the present invention.

FIG. 8 is a diagram showing a comparison between a conventional technique (a) and the present invention (b) for a screen display example and fonts to be used.

FIG. 9 is a diagram showing a screen display example according to the present invention.

FIG. 10 is a diagram showing a comparison of the number of characters between the conventional example (a) and the present invention (b).

FIG. 11 is a block diagram showing a configuration of a first conventional example of a smoothing processing circuit (Japanese Patent Application Laid-Open No. 60-202475).

FIG. 12 is a timing chart illustrating the operation of FIG.

FIG. 13 is an image diagram for explaining the operation of FIG. 11;

FIG. 14 is a block diagram showing the configuration of a second conventional example of the smoothing processing circuit (Japanese Utility Model Application Laid-Open No. 62-89054).

FIG. 15 shows a conventional example of multiplex display of characters (USP 5, 42).
No. 0,610).

FIG. 16 shows a conventional example in which characters and figures are multiplexed (USP
No. 5,420,610).

17 is a diagram showing a display example by the conventional device of FIG.

18 is a diagram showing a display example by the conventional device of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Timing generation circuit, 2 ... Memory control circuit, 3 ... Display memory, 4 ... Character memory, 5 ... P / S conversion block, 6 ... Smoothing processing and attribute processing block,
7: color memory, 8: CPU bus interface,
9 CPU, 10 extended memory interface, 11
Extended character memory, 12 address / control signal bus, 13 data bus, 20 to 23 data latch, 2
4 P / S converter, 25 selector, 30 bit image data in character memory, 31, 32 timing of data read from memory, 33 output of P / S converter, 34 smoothing process Circuit output, 35
... Screen display, 41 ... Timing of data read from memory, 42 ... Data latch timing signal, 43 ...
P / S converter input timing, 44: output of P / S converter, 45: output of smoothing processing circuit, 51: bit image data in character memory, 52: screen display, 53 to 56: read data block, Reference numeral 60: bit image data in the character memory, 61: screen display data, 131: bit image data in the image memory, 132: timing of data read from the memory, 133: timing of input to the P / S converter , 1
34 output of P / S converter, 135 output of smoothing processing circuit, 136 screen display, 501 P / S converter block.

Claims (7)

[Claims] 1. A character storage circuit for storing a character or graphic pattern corresponding to a character code in a bitmap format arranged in a matrix, wherein a plurality of rows of data constituting the matrix can be read simultaneously. A character storage circuit comprising a data path. 2. A character storage circuit for storing a character or graphic pattern corresponding to a character code in a bitmap format arranged in a matrix, wherein each of the m-row and n-column points represented by k-bit data is provided. Memorize characters or graphic patterns in a gathering,
A character storage circuit comprising a read data path through which data in each row can be read with a data width of n × k. 3. A character or graphic pattern corresponding to a character code is stored in a bitmap format arranged in a matrix of m rows and n columns, and is stored together with the data of the line specified by the character code and the line number. and 2 ^k rows and character storage circuit provided with a read data path data can be read at the same time, 2 ^k n-bit temporary storage means for temporarily storing the read data of the character memory circuit including a row, the character memory Temporary storage control means for selecting one data from the data read twice consecutively from the circuit and storing the selected data in the n-bit temporary storage means; and 2 ^k connected to the n-bit temporary storage means, respectively.
Pieces of n-bit parallel-serial conversion means, smoothing means for generating a display signal in which oblique lines are smoothed from serial inputs of 2 ^k adjacent rows, interposed between the n-bit parallel-serial conversion means and the smoothing means Display control means for switching 2 ^k n-bit parallel-serial conversion means and a connection line between the smoothing means in accordance with a display vertical position of a character or a figure to be displayed. apparatus. 4. A character storage in which a character or a graphic pattern is stored as a set of points in m rows and n columns in which each point is represented by k-bit data, and data in each row can be read with a data width of n × k. Circuit; k n-bit temporary storage means for temporarily storing data read from the character storage circuit; k parallel / serial conversion means respectively connected to the temporary storage means; And control means for instructing the parallel / serial conversion means to transfer data at a desired timing. 5. The display control device according to claim 4, wherein the k-bit data is data for designating a color for displaying each point, and displays a maximum of 2 k colors. . 6. The apparatus according to claim 3, further comprising a function of reading out two or more characters or figures from the character storage circuit during a display period of one character or figure. Display control device. 7. A character storage circuit in which part or all of the character storage circuit is rewritable temporary storage means, is incorporated in an integrated circuit, and is externally represented by a set of points of m rows and n columns. 7. A connection means for connecting a second character storage circuit for storing data for displaying graphics and graphics.
The display control device according to the item.