JPH05108056A - Variable power display device - Google Patents

Abstract

PURPOSE:To improve variable power and display response performance which do not depend upon software for display variable power display operation. CONSTITUTION:This invented variable power display device is equipped with storage means 1, and 6-9 where display data are converted into bit image data and stored. The bit image data stored in the storage means 1 are read out through read data specifying means 13 and 14 which perform shifting operation based upon a 1st clock and the bit image data at the parts specified by those read data specifying means 13 and 14 are read out by data read means 5, 6-9 which perform reading operation in synchronism with a 2nd clock. The bit image data read out with the 2nd clock are displayed by a display means 16 and the display magnification is set by varying the frequency ratio of the 1st and 2nd clocks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable-magnification display device for enlarging / reducing (magnifying / decreasing) a desired portion of a display screen on a display such as a workstation.

[0002]

2. Description of the Related Art There is a workstation in which a host function and a terminal function are integrated, which outputs a result of performing information processing of a predetermined application field as an image on a bitmap display.

Conventionally, in order to enlarge, for example, the display on the bitmap display of the workstation, a display scaling mechanism provided with software for enlargement display and VRAM (video RAM) which is a memory for display. It is used. In this system, data in the area designated by the terminal is subjected to processing such as coordinate conversion by software to be converted into enlarged display data and written in the VRAM. Then, the enlarged image is obtained by displaying the enlarged display data written in the VRAM on the bitmap display.

Further, as the bit map display becomes higher in resolution, the bit map display itself can be made smaller to downsize the entire apparatus. On the other hand, if you make the bitmap display smaller,
It is expected that the size of characters displayed on the display will become smaller, making it difficult to identify. Therefore, even in such a case, the above-described display scaling mechanism can be used. However, the above-described variable-magnification method has a drawback of low display responsiveness because the processing of enlarging display data is performed by software.

In addition, a magnified display mechanism of a desktop type workstation, which is generally equipped with a large display,
When it is applied as it is to a laptop workstation having a relatively small display, the operability is extremely poor, so that an enlargement display mechanism corresponding to the display had to be made for each software.

[0006]

As described above, since software is conventionally used to scale the display on the display, the display response performance is low, and a scaling display mechanism is created for each software. There was a problem that had to be.

The present invention has been made in view of the above circumstances, and provides a variable-magnification display device which realizes enlargement / reduction of a display image without using software and improves display response performance. The purpose is to

[0008]

In order to achieve the above object, the present invention provides a storage means for converting display data into bit image data and storing the display data, and a first clock for data to be read from the storage means. And a data reading means for reading bit image data of the portion instructed by the read data instructing means at a timing based on a second clock, and the data reading means. A configuration is provided that includes display means for displaying the bit image data read at the second clock, and display magnification switching means for changing the frequency ratio of the first clock and the second clock according to the display magnification. ..

[0009]

According to the present invention in which the above means are taken,
The data designated by the clock is read and displayed at the timing of the second clock. Therefore,
Depending on the frequency ratio between the first clock and the second clock, the same data may be read continuously or every other data may be read. The display data is enlarged by continuously reading the same data a plurality of times, and the display data is reduced by thinning and reading the data.

For example, if the first clock has a period twice that of the second clock, the second clock reads the data twice while the first clock specifies the data. And the resulting displayed image is magnified twice.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block configuration of a variable power display device according to an embodiment of the present invention. Hereinafter, the enlarged display will be described as an example.

The variable-magnification display device of this embodiment comprises a VRAM1 in which bit image data is written under the control of the operating system, and a VRAM1 for designating an enlarged area.
The address data in the vertical and horizontal directions are input by the coordinate instruction input device 2 such as a mouse. The address data of the enlarged area input from the coordinate instruction input device 2 is held in the enlarged area instruction address register 3,
The vertical address data of the VRAM 1 is applied to the first multiplexer 4, and the horizontal address data of the VRAM 1 is applied to the second multiplexer 5.

In the present embodiment, the expanded area can be designated by an arbitrary address in the vertical direction, and can be designated by the address of a line divided into four in the horizontal direction in the horizontal direction. Therefore, 4 in the horizontal direction
Corresponding to each area of the VRAM 1 to be divided
Shift registers 6 to 9 are respectively connected.

Further, in this embodiment, any key of the keyboard is used as the enlarged display key 10 for switching between the enlarged display mode and the normal display mode. The display mode signal input from the enlargement display key 10 is input to the flip-flop 11, and the flip-flop output signal indicates the enlargement display mode or the normal display mode. The display mode signal output from the flip-flop 11 is
Input to the first and second multiplexers 4 and 5 and the first and second selectors 12 and 13, respectively.

The first multiplexer 4 provides an initial address value in the vertical direction to the address register 14 as a read data designating means for designating the vertical read address of the VRAM 1, and the address register according to the display mode. The initial value given to 14 is switched. That is,
When the output of the flip-flop 7 indicates the enlarged display mode, the vertical address initial value is read from the enlargement instruction area address register 3 and input to the address register 10. When the normal display mode is indicated, the initial value 0 is given to the address register 14.

The address register 14 receives the address given from the first multiplexer 4 as the first selector 1
It counts up in synchronism with the clock A as the first clock which is output from 2.

The second multiplexer 5 receives the VRA from the enlargement instruction area address register 3 in the enlargement display mode.
It functions to read the horizontal address of M1 and take out only the outputs of the shift registers 6 to 9 corresponding to the expanded area.

The first selector 12 receives the clock A1 and a clock A2 which is a half of the clock A1, and selects the clock A1 in the normal display mode and selects the clock A2 in the enlarged display mode for addressing. Input to the register 14.

The second selector 13 receives the clock B1 and the clock B2 which is a half of the clock B1, and selects the clock B1 in the normal display mode and the clock B2 in the enlarged display mode. The transfer clock B is input to the shift registers 6 to 9.

The first to fourth shift registers 6 to 9 are synchronized with the read timing clock A1 input as the second clock through the first selector 12 and are read from the row designated by the address register 14. It has a function as a data reading means for reading bit image data.
Then, each read data is shifted by 1 bit to the adjacent shift registers sequentially from the first shift register 6 to the fourth shift register 9 in synchronization with the transfer clock B input via the second selector 13. At the same time, the respective shift registers 6 to 9 directly output to the second multiplexer 5. By the second multiplexer 5 taking out only the data from the predetermined shift registers 6 to 9, the data in the predetermined region in the lateral direction is taken out.

The outputs of the predetermined shift registers 6 to 9 fetched by the second multiplexer 5 are fetched by the display control circuit 15 in synchronization with the clock B1 as the second clock. The display control circuit 15 has a function of displaying the data taken in from the second multiplexer 5 on the display 16. Next, the operation of the present embodiment configured as described above will be described with reference to an equal size display and a 4 × enlarged display as examples.

In the normal display mode, the address register 1
4 is a clock A input via the first selector 12
1, the read addresses are sequentially shifted from A, B and C (FIG. 2 (a)).

When the row A is designated by the clock A1, the same clock A is applied to the first to fourth shift registers 6-9.
1 is input as a read timing clock (FIG. 2 (b)), and in synchronization with the read timing clock, the data A1 to An of the row A are read to the corresponding first to fourth shift registers 6 to 9. (FIG. 2 (c)).

The data of the row A taken into the first to fourth shift registers 6 to 9 is the clock shown in FIGS. 3A and 3B, and is the data in the state shown in FIG. 3C. Display 1
6 is transferred. That is, the second multiplexer 5 operates so as to pass only the output of the fourth shift register 9, and the output of the second multiplexer 5 is synchronized with the transfer clock B1 by An, A (n-1). The data in row A appears in the order of. The display control circuit 15 takes in this in synchronization with the read timing clock B1, and FIG.
The data indicated by is transferred to the display 16 and displayed.

Similarly, in the other rows, every time the clock A1 input to the address register 14 designates B, C ..., The data in that row is read and transferred to the display unit 16. As a result, the display 16 displays the data having the content shown in FIG.

On the other hand, an enlarged area is designated by the coordinate instruction input device 2 (in this embodiment, the area is shown in FIG. 4),
When the enlarged display mode signal is input from the enlarged display key 10, the enlarged display mode is set.

In the enlarged display mode, the address register 14 is supplied with the initial value (A in this embodiment) of the enlarged area from the first multiplexer 4 and the first register
The clock A2 (FIG. 2 (d)) is supplied from the selector 12 of FIG. On the other hand, the second multiplexer 5 has a shift register corresponding to the horizontal expansion area (for example, in the present embodiment, the horizontal expansion area corresponds to the first and second shift registers 6 and 7, and the second shift Register 7 will be described as corresponding). Further, the second selector 13 inputs the transfer clock B2 (FIG. 3 (d)) to each shift register 6-9.

As a result, the shift operation for designating the vertical read address has a double cycle as shown in FIG. On the other hand, since the read timing clock for reading from the VRAM 1 to each of the shift registers 6 to 9 is the same clock A1 as in the normal display mode, while the address register 14 designates the A line, the A line is 2 It is read out twice (FIG. 2 (e)). Therefore, as shown in FIG. 5, the data of each row transferred to the display 16 are arranged in rows of two rows, and are doubled in the vertical direction.

Further, the first and second shift registers 6 and 7 to which the data for one row in the enlarged area has been input, perform the shift operation at the clock B2 which is a half of the clock in the normal mode, and the display control circuit. Since 15 captures data at the same clock B1 as in the normal display mode, the same data is read twice in the horizontal direction as shown in FIG. 3E, and the same data is also read in the horizontal direction as shown in FIG. It will be doubled. As a result, the magnified area is magnified four times and displayed on the display 16.

As described above, according to this embodiment, the read timing clock A1 to the shift registers 6 to 9 is kept constant, and the clock A for shifting the vertical read address of the VRAM 1 is changed according to the display mode, and Since the read timing clock B1 to the display control circuit 15 is fixed and the data transfer clock B of the shift registers 6 to 9 is changed according to the display mode, a desired portion is enlarged and displayed without depending on software. can do. Therefore, the magnified display response performance can be improved, and the same software can be used on the large display of the desktop type workstation and the small display of the laptop type without changing the software for the magnified display. You can

In the above embodiment, the case where the image is enlarged by 4 times is described, but the image can be enlarged at an arbitrary magnification by changing the values of the clock A2 and the clock B2.

In the embodiment, the enlarged display is described as an example, but the reduced display becomes possible by shortening the cycle of the clock A2 and the clock B2. Further, the enlargement / reduction is performed by the frequency ratio between the clock A given to the address register 14 and the read timing clock A1 given to the shift registers 6 to 9,
Alternatively, it is determined according to the frequency ratio of the transfer clock B applied to the shift registers 6 to 9 and the clock read timing clock B1 applied to the display control circuit 15, and the frequency ratio is appropriately and selectively determined according to the enlargement ratio. Is.

[0033]

As described above in detail, according to the present invention, it is possible to display a display image at an arbitrary magnification by a very simple operation without depending on software, and to improve display responsiveness. It is possible to provide a variable power display device capable of

[Brief description of drawings]

FIG. 1 is a configuration diagram of a variable power display device according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining enlarged display in a vertical direction, which is an operation explanatory diagram of one embodiment.

FIG. 3 is a timing chart for explaining an enlarged display in a horizontal direction, which is an operation explanatory diagram of one embodiment.

FIG. 4 is a diagram showing a specific data example of an enlarged area.

FIG. 5 is a diagram showing an enlarged view enlarged by 4 times.

[Explanation of symbols]

1 ... Video RAM, 2 ... Coordinate instruction input device, 3 ... Enlarged area instruction address register, 4, 5 ... First and second multiplexers, 6-9 ... Shift register, 10 ... Enlarged display key, 11 ... Flip-flop, 12, 13 ... First and second selectors, 15 ... Display control circuit, 16 ... Display device.

Claims (1)

[Claims] 1. Storage means for converting display data into bit image data and storing the read data, read data instruction means for sequentially instructing data to be read from the storage means based on a first clock, Data reading means for reading the bit image data of the portion instructed by the read data instructing means at the timing based on the second clock, and a display for displaying the bit image data read by the data reading means at the second clock. A variable-magnification display device comprising: a display unit and a display-magnification switching unit that changes a frequency ratio between the first clock and the second clock according to a display ratio.