JPH08179279A - Liquid crystal display device - Google Patents

Abstract

PURPOSE: To realize a display controller for performing a satisfactory display to a liquid crystal panel in which a pixel pitch is made fine by using a conventional liquid crystal driving circuit. CONSTITUTION: Display data are rearranged in accordance with switching groups 118 to 121 by a display controller 102. Then, display data are successively outputted to a column circuit 110 for every data corresponding to respective switching groups. Then, switching groups 118 to 121 are made to be opened and closed by control signals 122 to 125 in accordance with display data to be displayed. Consequently, the display data can be outputted only to X electrodes connected to the switching group to which pertinent display data are made to correspond. Thus, this controller can cope with a high difinition liquid crystal panel without necessitating the increasing of the number of output terminals of the column circuit and the fining of the pich of the output perminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display controller suitable for displaying display data of a personal computer, a workstation or the like on a liquid crystal panel.

[0002]

2. Description of the Related Art For personal computers, workstations, etc.
Liquid crystal display devices are widely used.

The structure and operation of the liquid crystal display device will be described below with reference to FIGS. The explanation here is for a liquid crystal panel with a horizontal resolution of 640 pixels for each of R, G, and B pixels (total 1920 (= 640 × 3) pixels) and a vertical resolution of 480 lines, which is manufactured by Hitachi, Ltd. Controller (Product name) Column circuit HD6631
0 ") is used as an example.
For the contents of the explanation, Hitachi LCD Driver LSI Data Book p6 published by Hitachi, Ltd. Semiconductor Division
61, 662.

As shown in FIG. 17, the driver control means 2
Display data 2401 and a synchronization signal 2402 synchronized with the display data 2401 are input to 110 from a personal computer, a workstation, or the like. The sync signal 2402 includes a dot clock, a horizontal sync signal, and a vertical sync signal.

The data conversion circuit 2120 in the driver control means 2110 converts the display data 2401 so as to match the interface of the column circuit 2100 described later. Then, the converted data is output as driver display data 2103 (see FIG. 18).

The frequency divider circuit 2121 divides the dot clock included in the synchronizing signal 2402 to divide the dot clock, so that the display data fetch clock 21
11 is generated and is output (see FIG. 18).

Further, the delay circuit 2122 has a synchronization signal 24.
02, the horizontal sync signal is delayed to display the display data latch clock 2104 and the enable signal 2105.
And are generated and output (see FIG. 18).

Among these signals, the driver display data 2103 and the display data fetch clock 2111 are
It is output to the column circuit 2100. On the other hand, the enable signal 2105 is output to the scan drive circuit 2131. The display data latch clock 2104 is output to both the column circuit 2100 and the scan drive circuit 2131.

The column circuit 2100 captures the driver display data 2103 at the falling edge of the display data capture clock 2111. Here, since the column circuit HD66310 manufactured by Hitachi, Ltd. used as the column circuit 2100 has 160 outputs, in the liquid crystal display device, the HD663 is used.
Twelve 10 (= 1920/160) are used. Hereinafter, the column circuits 2100-1 to 2100-12 are collectively referred to as a column circuit group 2130. Column circuit 2100
The driver display data 2103 is fetched only when the enable signal input EIO1 is at a low level.

When the column circuit 2100 fetches the display data for 60 pixels, the enable signal output EI
O2 changes from high level to low level. Then, the enable signal input EIO1 of each column circuit 2100 is connected to the column circuit 210 located on the left side.
The enable output signal EIO2 of 0 is input. The enable signal input EIO1 of the column circuit 2100-1 located at the leftmost end is grounded. Regarding the internal configuration of the column circuit HD66310,
A detailed description will be given later.

When the column circuit 2100-1 completes fetching the display data 2103 for 160 pixels, the enable output signal EIO2 changes from the high level to the low level. Then, the column circuit 210 of the next stage (on the right side)
0-2 are enabled. Then, this column circuit 2100-2 starts fetching the display data 2103.

Thereafter, similarly, the display data is sequentially fetched by 160 pixels from the column circuit 2100 located on the left side.

When the driver display data 2103 for one line has been fetched, the column body warmer group 213
0 applies a display voltage corresponding to the display data for the one line to the liquid crystal panel 2132.

On the other hand, the scan drive circuit 2131 sequentially scans vertical lines in synchronization with the enable signal 2105.

Then, the display data output by the column circuit 2100 (data latched by the latch circuit 2303 described later) is displayed on the line selected by the scan drive circuit 2131 at that time.

Even when the display data does not change line by line, the data writing is performed.

Next, the outline of the column circuit HD66310 will be described with reference to FIG.

The input display data 2103 for four pixels is input in parallel to the column circuit HD66310. The input display data 2103 is 3 bits of gradation data for each pixel. Also, 160 signal lines 2101 for outputting the liquid crystal drive voltage are provided.

The latch address counter 2301 counts the falling edge of the display data fetch clock 2111 and generates a latch signal. It should be noted that the display data acquisition clock 2111 uses the enable signal input EIO1.
You can mask with. When the enable signal input EIO1 is at high level, no latch signal is generated. Also, the display data acquisition clock 2111 is set to 40
After counting the number of times, the enable signal output EIO2 is set to the low level. As will be described later, since display data for four pixels can be captured at one time, counting 40 times corresponds to capturing display data for 160 (= 4 × 40) pixels.

The latch circuit 2302 is divided into 40 stages every 4 pixels. The latch circuit 2302 fetches driver display data 21003 for four pixels at the same time in synchronization with the latch signal from the latch address counter 2301.

The latch circuit 2303 is composed of a latch circuit for 160 pixels. The latch circuit 2303 latches the display data taken in by the latch circuit 2302 in synchronization with the display data latch clock 2104. Then, the latched data is held for one line time.

The level shifter circuit 2304 decodes the display data latched by the latch circuit 2303 and generates a select signal for selecting the liquid crystal applied voltage.

The liquid crystal drive circuit 2305 selects one of eight kinds of liquid crystal drive voltages 2306 according to a select signal, and outputs the selected voltage as an applied voltage 2101 to the X electrode of the liquid crystal panel.

As described above, most of the display operation in the liquid crystal display device is the repetition of the latch operation of the display data to the column circuit 2100.

In addition to this, as a driving method of the liquid crystal display device, there is a method in which the horizontal direction of the liquid crystal panel is divided into two areas and the display data for each area is transferred simultaneously. In the driving method, two display memories are provided, and when the display data is written in one, the display data is read from the other display memory and the read display data is output in parallel. Such techniques are described in, for example, Japanese Patent Application Laid-Open Nos. 1-1113793, 2-126285, and 5-232898.

[0026]

At present, liquid crystal panels are also required to have high-definition display. In order to deal with this, not only the pixel pitch must be reduced, but also the output pitch of the column circuit must be reduced. This is because the above-mentioned cascade connection of column circuits cannot be performed. Further, it is necessary to reduce the area of the column circuit itself, and to reduce the pitch of the TAB that connects the output of the column circuit to the liquid crystal panel.

However, if the TAB and the liquid crystal panel are miniaturized, a high level of technology is required for the alignment of the bonding portion and the bonding technology, which causes another problem that the production cost becomes high. For this reason, there has been a demand for a technique that can be applied to a liquid crystal panel for high definition display while using a conventional liquid crystal drive circuit.

An object of the present invention is to provide a display controller which can be applied to a liquid crystal panel having a fine pixel pitch while using a conventional liquid crystal drive circuit.

[0029]

The present invention has been made to achieve the above object, and a first aspect thereof is as follows.
An active matrix type liquid crystal panel having M Y electrodes and N X electrodes, a function of generating a selection voltage, a non-selection voltage, and a plurality of types of gradation voltages, A power supply circuit including a selection voltage terminal that outputs a voltage, a non-selection voltage terminal that outputs the non-selection voltage, and a gradation voltage terminal that outputs the gradation voltage, and n (n <N) outputs A terminal is provided, and any one of the grayscale voltages output from the power supply circuit is selected for each of the output terminals corresponding to a separately given data string, and the selected grayscale voltage is output to the output terminal. Output from the column circuit, common means for applying the selection voltage to any one of the Y electrodes, and the non-selection voltage to the other Y electrodes, and a plurality of components having n or less constituent elements. The above X electrodes are classified into groups,
Any one of the groups is selected, and only the X electrodes belonging to the selected group are connected to the output terminals of the column circuit in a predetermined correspondence relationship.
Display in which at least display data and a horizontal synchronizing signal are input from the outside, and the order of the display data input from the outside is rearranged so that the groups to which the corresponding X electrodes belong are matched with each other. There is provided a liquid crystal display device including a display controller that sequentially outputs to each column circuit for each collection of data.

The display controller incorporates a first memory capable of storing at least one line of data, a second memory capable of storing at least one line of data, and display data input from the outside. , Above first
Of the first memory and the second memory that is not the target of the write operation by the writing means at that time, and Readout means for sequentially reading and outputting the stored display data for each set of display data in which the corresponding groups to which the corresponding X electrodes belong to each other and the column circuit are arranged on the X electrodes belonging to a certain group. After the output of the adjusted voltage is completed and before the output of the gradation voltage corresponding to the X electrode of the next group is started, the selection of the group by the X electrode switch means is performed to select the X electrode and the column of the next group. Selection instructing means for changing so as to connect to the output terminal of the circuit, and a memory which is a target of the writing operation of the display data by the writing means. Re, as a trigger for the horizontal sync signal is enabled, and control means to switch alternately between the first memory and the second memory may be configured to include.

Input of the display data from the outside is performed in parallel, and the display data input from the outside is received by a predetermined number of pixels,
The received display data is further classified based on the group to which the X electrode to which the display data corresponds corresponds, and the conversion means further outputs the classification data, and the writing means outputs the display data output by the conversion means. , And may be written in the first memory or the second memory.

The write means performs the write operation in synchronization with a separately generated write clock, and the read means is synchronized with a separately generated read clock that is asynchronous with the write clock. The above-mentioned control means is for performing the above-mentioned reading.
Switching the memory to which the display data is written by the writing means is performed after confirming that one screen of display data has been written instead of the horizontal synchronization signal. The memory and the second memory may have a storage capacity capable of storing display data for one screen of the liquid crystal panel.

The common means is provided with m (m <M) output terminals, one of the output terminals is sequentially selected, and the selected voltage is supplied from the selected output terminal to the other output terminals. The common circuit that outputs a non-selection voltage from the terminal and the Y electrode are divided into a plurality of groups each having m or less constituent elements,
Only the Y electrodes belonging to any of the groups are selectively connected to the output terminals of the common circuit in a predetermined correspondence relationship, and the Y electrodes that are not connected to the common circuit at that time are connected to the power supply circuit. Y electrode switch means connected to a non-selected voltage terminal, and the display controller changes the selection of the group by the Y electrode switch means every time the common circuit finishes selecting all the output terminals. Is preferred.

More preferably, the storage capacities of the first memory and the second memory are changeable.

According to a second aspect of the present invention, an active matrix type liquid crystal panel having M Y electrodes and N X electrodes and n (n <N) output terminals are provided. A column circuit which outputs a grayscale voltage corresponding to a data string separately given from the output terminal, and the X electrodes are classified into a plurality of groups each having n or less constituent elements. A liquid crystal display device configured to select one and connect only the X electrodes belonging to the selected group to the output terminals of the column circuit in a predetermined correspondence relationship. In the display controller used to drive the first memory, a first memory capable of storing at least one line of data, a second memory capable of storing at least one line of data, and an external input Writing means that takes in display data and writes it in the first memory or the second memory, and among the first memory and the second memory, the writing means is the execution target of the writing operation at that time point. From the other side, the display data already stored in the memory is sequentially read and output for each set of display data in which the groups to which the corresponding X electrodes belong to each other, and the column circuit. ,
After the output of the gray scale voltage to the X electrodes belonging to a certain group is finished and before the output of the gray scale voltage corresponding to the X electrodes of the next group is started, the selection of the group by the X electrode switch means is performed. The horizontal synchronizing signal is effective for the selection instruction means for changing the X electrode of the next group so as to be connected to the output terminal of the column circuit and the memory for which the writing operation of the display data is performed by the writing means. The first memory and the second memory
And a control means for alternately switching between the display controller and the memory of the display controller.

[0036]

[Function] The power supply circuit supplies the selected voltage from the selected voltage terminal.
The non-selection voltage terminal outputs the non-selection voltage, and the gradation voltage terminal outputs the gradation voltage terminal.

The X electrode switch means classifies the X electrodes into a plurality of groups each having n or less constituent elements, selects any one of the groups, and selects the X electrodes belonging to the selected group. Are connected to the output terminal of the column circuit in a predetermined correspondence relationship.

The display controller rearranges the order of the display data input from the outside, and sequentially outputs the display data to the column circuit for each set of display data in which the groups to which the corresponding X electrodes belong coincide with each other. The display controller can be configured as follows, for example.

The writing means takes in the display data input from the outside and writes the display data in the first memory or the second memory. The reading unit corresponds to the display data already stored in the memory from the one of the first memory and the second memory which is not the target of the writing operation by the writing unit at that time. The above groups to which the X electrodes belong are sequentially read out and output for each set of display data that match each other. At this time, the control means sets the memory targeted for the write operation of the display data by the write means between the first memory and the second memory in response to the activation of the horizontal synchronization signal. They are switching alternately. As a result, the display data is alternately written / read out for each line in the first memory and the second memory. The rearrangement is performed by designating an address corresponding to each group when writing or reading.

The column circuit selects one of the gradation voltages for each output terminal corresponding to the data string given from the display controller, and outputs the selected gradation voltage from the output terminal. At this time, the selection instructing means of the display controller causes the column circuit to finish outputting the grayscale voltage to the X electrodes belonging to a certain group, and before starting to output the grayscale voltage corresponding to the X electrodes of the next group. The selection of the group by the X electrode switch means
The electrodes are changed so that they are connected to the output terminals of the column circuit. As a result, the gradation voltage output from the column circuit at that time is applied to the X electrodes belonging to the group selected at this time.

When the input of the display data from the outside is parallel, the display data is classified into groups by the conversion means and is output for each classification. Then, the writing means may write the display data output by the converting means into the first memory or the second memory. Further, when the clock synchronized with the writing unit and the clock synchronized with the reading unit are asynchronous with each other, the control unit switches the memory to which the display data is written by the writing unit by one. Make sure that you have written the display data for the screen. The first memory and the second memory have a storage capacity capable of storing display data for one screen of the liquid crystal panel.

On the other hand, the common means applies the selection voltage to any one of the Y electrodes and the non-selection voltage to the other Y electrodes. The common means can be configured as follows, for example. The common circuit sequentially selects one of the output terminals, and outputs the selected voltage from the selected output terminal and the non-selected voltage from the other output terminals.
The Y electrode switch means divides the Y electrodes into a plurality of groups each having m or less constituent elements, and selectively associates only the Y electrodes belonging to any of the groups with the output terminals of the common circuit in a predetermined correspondence relationship. To connect. Further, the Y electrode which is not connected to the common circuit at that time is connected to the non-selected voltage terminal of the power supply circuit. Then, the display controller changes the selection state by the Y electrode switch means each time the common circuit finishes selecting all the output terminals.

[0043]

Embodiments of the present invention will be described with reference to the drawings.

A first embodiment of the present invention will be described with reference to FIGS. 1 to 6.

As shown in FIG. 1, the liquid crystal display device of the present embodiment has a liquid crystal panel 101, a column circuit 110 for driving the X electrodes of the liquid crystal panel 101, and a liquid crystal panel 10.
1, a common circuit 112 for driving the Y electrode, a display controller 102 for operating the column circuit 1110 and the common circuit 112 according to various signals and display data input from the outside, and a power supply circuit 109. Has been done. Of course, these are signal lines 103, 104, 105, 106, 1 for transmitting and receiving various signals and the like.
08, 127, 122-125 and buses 111, 1
They are connected by 13, 115, 126, 117 and 107. Further, in this embodiment, the liquid crystal panel 101 and the column circuit 110 are connected by the display controller 102.
Switch groups 118 to 121 that operate according to instructions from
Have gone through. In this embodiment, this switch group 11
8 to 121 are provided and the display control corresponding thereto is the greatest feature.

In the following description, in order to make it easier to understand the correspondence between the explanatory text and the drawings, signals transmitted and received through these signal lines and buses may be referred to by the numbers of the signal lines and buses. is there. For example, the display data input via the bus 107 will be referred to as display data 107. The same applies to the description of the other embodiments.

The liquid crystal panel 101 is of an active matrix type in which 320 X electrodes and 240 Y electrodes form a matrix, and switching elements are provided at the intersections thereof.

The display controller 102 displays the display data 1 for displaying on the liquid crystal panel 101 based on the display data 107 and various control signals input from the outside.
26 and various signals. The control signals input from the outside include a vertical synchronizing signal 103, a horizontal synchronizing signal 104, a blank signal 105 indicating the effective range of display data, and a dot clock 106. The display data 107 is serially sent in synchronization with the dot clock 106 in the order according to the display position on the screen.

The display controller 102, based on these control signals 103 to 106 and the display data 107, the alternating signal 108, the column control signal 115, the common control signal 117, the display data 126, and the switch group 118 to.
The switch control signals 122 to 125 for controlling 121 are generated and output.

The display controller 102 of this embodiment has a function of rearranging the display data 107 in accordance with the connection relationship of the switch groups 118 to 121 and outputting it as display data 126. In this embodiment, there are four switch groups.
Corresponding to that, after rearranging the display data,
The output is divided into four groups. This grouping is performed by classifying the display positions on the screen according to the remainder system of 4. This is each switch group 11
This corresponds to that the connection relationship between 8 to 121 and the X electrode follows the remainder system of 4. Within each group, the leftmost display position is output first. Details of the display controller 102 and the rearrangement will be described later.

The power supply circuit 109 is for generating various voltages applied to the liquid crystal panel (counter electrode voltage 127, gradation voltage 111, selection / non-selection voltage 113). The gradation voltage 111 is generated in synchronization with the alternating signal 108 and is supplied to the column circuit 110. The gradation voltage 1
11 has a positive polarity and a negative polarity with respect to the counter electrode voltage 127. Selection / non-selection voltage 113
Are output to the common circuit 112.

The column circuit 110 selects one of the gradation voltages input through the bus 111 for each pixel,
The selected one is output to the output bus 114 (output terminals s0 to s
80). The gradation voltage is supplied by the above-described switch 118 group 118 to 121 only to a predetermined X electrode which is in a conductive state with the output bus 114 at that time. The operation state of the column circuit 110 is controlled by the column circuit control signal 115 output from the display controller 102.

The common circuit 112 outputs the selection voltage / non-selection voltage input through the bus 113 to the Y electrode of the liquid crystal panel 101 through the output bus 116. The operation state of the common circuit 112 is controlled by the common circuit control signal 117 output from the display controller 102.

The switch groups 118 to 121 are output terminals s0 to s8 which form the output bus 114 of the column circuit 110.
0 and the X electrodes (electrodes x0 to x31) of the liquid crystal panel 101.
It is for appropriately changing the connection relationship with 9).
Each of the switch groups 118 to 121 is composed of 80 switches. Electrodes x0 of the liquid crystal panel 101
The x319 are divided into four groups by classifying the positions from the left side according to a predetermined rule (in this embodiment, a remainder system of 4). Switch group 118-12
1 is turned on according to the instruction from the control signals 122 to 125.
By changing the ON / OFF states respectively, only the X electrodes belonging to any one of the groups are appropriately output bus 11 of the column circuit.
It is designed to connect with 4. Here, the switches belonging to the first switch group 118 are referred to as a switch 1-1, a switch 1-2, ..., A switch 1-80 in order from the left side. The switches belonging to the second switch group are the switches 2-
1, switch 2-2, ..., Switch 2-80. The switch terminals belonging to the third switch group 120 and the fourth switch group 121 are also called output terminals s0 to s.
80, switch groups 181-121, and electrodes x0-x3
The specific connection relationship between 19 and is as follows. The output terminal s0 can be connected to the electrode x0 by the switch 1-1, the electrode x1 by the switch 2-1, the electrode x2 by the switch 3-1, and the electrode x3 by the switch 4-1. Similarly, the output terminal s1 is connected to the electrode x by the switches 1-2, 2-2, 3-2 and 4-2.
4, x5, x6, x7 can be connected. The output terminals s2 to s80 and the electrodes x8 to x319 are also connected in the same relationship.

Therefore, only the first switch group 118 (switches 1-1 to 1-80) is turned on, and the other switch group 11 is turned on.
By turning off 9, 120 and 121, the output terminal s
The gradation voltage output from 0 to s80 is set to the electrodes x0, x.
, X8, x12, ..., X316 can be applied. Only the second switch group 119 (switches 2-1 to 2-80)
When turned on, the grayscale voltages output from the output terminals s0 to s80 are similarly set to the electrodes x1, x5, x9, x113,
..., can be applied to x317. The same applies to the third switch group 120 (switches 3-1 to 3-80) and the fourth switch group 121 (switches 4-4 to 3-80).

The state of the first switch group 118 (ON / OF
F) is changed by the first control signal 122 output from the display controller 102. The state (ON / OFF) of the second switch group 119 is changed by the second control signal 123. State of the third switch group 120 (ON / OF
F) is modified by the third control signal 124. Fourth
The state (ON / OFF) of the switch group 121 is configured to be changed by the fourth control signal 125.

Next, regarding the display controller 102,
This will be described in more detail with reference to FIG. The display controller 102 includes a clock control unit 201, a memory system control bus 202, a memory control unit 203, a memory control bus 204,
Memory control bus 205, bus control line 206, memory 20
7, a memory 208, data buses 209 and 210, a bus selector 211, and a latch circuit 213.

The clock control unit 201 uses the vertical synchronization signal 1
03, the horizontal synchronizing signal 104, the blank signal 105, and the dot clock 106, the alternating signal 108, the column control signal 115, the common control signal 117, and the switch control signals 122-125 are produced | generated. further,
The clock control unit 201 includes a memory control signal 202 for controlling the display controller 102 and a latch clock 21.
4 is also generated.

The memory system control signal 202 includes a read clock. Latch clock 214
Is synchronized with the data transfer clock in the column control bus 115. The data transfer clock and the output clock in FIGS. 4 and 6 described later are included in the column control signal 115. Further, the FLM and line signal in FIG. 6 are included in the common control signal 117.

The memory control unit 203 includes the memories 207 and 2
08 for writing / reading data to / from the bus 08 and controlling the state of the bus selector 211. Therefore, the memory control unit 203 generates the memory control signals 204 and 205 synchronized with the memory system control signal 202 and outputs them to the memories 207 and 208. Memory control signal 2
04 and 205 are the memories 207 and 20 in FIG.
A write enable signal for setting 8 to a writable state,
It includes a read enable signal for setting a read enable state and an address signal for designating a write address for data.

Further, the memory control section 203 outputs the bus control signal 206 to the bus selector 211. The memory control unit 203 sets the bus control signal 206 to “high” when writing to the memory 207, and the bus control signal 206 when writing to the memory 208.
To "low".

Each of the memories 207 and 208 has a storage capacity capable of storing display data for one line. Data is written to and read from the memories 207 and 208 through the data bus 209 and the data bus 210.

The above-mentioned rearrangement of the display data is configured so as to be accompanied by storing and reading the display data in the memory 207 (or 208).

The bus selector 211 includes the memories 207 and 2
The display data 107 is written by selecting any one of 08. In addition, either the memory 207 or the memory 208 is selected, the display data stored in the selected memory is read and output as the display data 212 to the latch circuit 213.

When the bus control signal 206 is "high", the bus selector 211 connects the display data bus 107 and the data bus 209, and the output bus 212 and the data bus 210.
And are connected. On the other hand, when the bus control signal 206 is “low”, the display data bus 107 and the data bus 210
And the output bus 212 and the data bus 209.

The latch circuit 213 uses the latch clock 21
4, the display data 212 is temporarily stored. After that, the latch circuit 213 outputs the stored data as the display data signal 126 to the column circuit 110.

In the present embodiment, the “selection voltage terminal”, “non-selection voltage terminal”, and “gradation voltage terminal” mean that the power supply circuit 109 selects the selection voltage, the non-selection voltage, and the gradation. It corresponds to a terminal that outputs a voltage, a signal line connected to the terminal, and a bus. The "X electrode switch means" corresponds to the switch group 118 to 121. Further, the group into which the X electrodes are divided is defined by which switch group is connected.

"First memory" and "second memory"
Is equivalent to the memory 207 and the memory 208 in this embodiment. The "writing means" and the "reading means" mean the clock control unit 201 and the memory control unit 20.
2. The bus selector 211, the bus connecting them, and the like operate in close cooperation. The “selection instruction means” corresponds to the clock 201. The “control means” means the memory control unit 202,
It is realized by the clock control unit 201 and the bus selector 211 operating in cooperation with each other.

The operation of the liquid crystal display device of this embodiment will be described.

First, the operation of the display controller 102 and the column circuit 110 will be described with reference to FIGS. Here, the display data 10 input from the outside
7 is written in the memory 207, and at the same time, the display data stored in the memory 208 is read out.

The blank signal 105 goes to a low level which means "valid". Then, the memory control circuit 203
Causes the bus control signal 206 to go "high". At the same time, the memory control unit 203 causes the memory control signal 20
The write enable signal in 4 is set to "valid" and the address for storing the data is designated.

Then, since the bus control signal 206 becomes "high", the bus selector 211 causes the display data 10
7 is output to the memory 207. In response to this, the memory 207 stores the display data at the address designated by the memory control signal 204.

In this case, if the data to be written is the first data (0th data), the memory control circuit 203 specifies the address "0". The address 80 is designated for the next data (first data). Further, the address 160 is designated for the second data input next, and the address 240 is designated for the third data. The fourth data is address 1
Is specified. Address 81 for the fifth data
The address 161 is designated for the sixth data, and the address 241 is designated for the seventh data. That is, the start address of each group is shifted by 80 or more, and then the address is incremented by 1 in each groove.

By performing the addressing in this way, as shown in FIG. 5, the data output to the X electrode through the first switch group 118 is stored in the area from address 0 to address 79. . Also, address 8
The data output through the second switch group 119 is stored in the area from 0 to 159. Similarly, the third switch group 12 is assigned to the addresses 160 to 239.
The data corresponding to 0 also has addresses 240 to 319.
Stores the data corresponding to the fourth switch group 121.

In parallel with the write operation of the display data to the memory 207 described above, the data stored in the memory 208 is also output to the latch circuit 213.

In FIG. 3, when the horizontal synchronizing signal 104 becomes "valid", the clock control unit 201 outputs 80 read clocks (not shown) in the memory control signal 202.

Further, the memory control unit 203 specifies an address for reading data in the memory control signal 205 in synchronization with the read clock. In this case, the address designation is performed by sequentially incrementing the addresses from 0 to 1.

Then, first, the display data corresponding to the first switch group 118 is output from the memory 208 to the latch circuit 213 through the bus selector 211. Then, the second switch group 119, the third switch group 120,
Data corresponding to the fourth switch group 121 is sequentially output.

The latch circuit 213 stores the output data in synchronization with the latch clock 214. The latch circuit 213 continues to output the latched data to the display data bus 126 until the next latch clock 214 becomes valid.

After outputting 80 read clocks, the clock control unit 201 sets the output clock contained in the column control signal 115 to "valid". The output clock is for instructing the column circuit 110 when to output the grayscale voltage. Further, in parallel with this, the clock control unit 201 turns on the corresponding switch group of the data currently output as the display data 126 by the switch control signals 122 to 125.
In addition, the other switches are turned off. For example, the display data 126 at that time corresponds to the first switch group 118 (addresses 80 to 159 in FIG. 5).
If so, the first switch group 118 is turned on and the second, third, and fourth switch groups 119, 120, and 121 are turned off. As a result, the column circuit 110 outputs the gradation voltage corresponding to the display data signal 126 at that time to only the predetermined X electrode until the next output clock becomes valid. The switch control signals 122 to 12
The output timing of 5 is not particularly limited as long as the column circuit 110 finishes outputting the gray scale voltage corresponding to the previous display data and starts outputting the gray scale voltage of the next display data. Not done. In some cases, it may be after the output of the target display data gradation voltage is started. It may be set as appropriate according to the actual characteristics of each circuit.

While the gradation voltage is being applied to the X electrodes (electrodes x0, x4, x8, ..., X316) through the first switch group 118, data corresponding to the second switch group 119 (in FIG. 5, Addresses 80 to 159) are read from the memory 208. After this, similarly, the second
While the grayscale voltage is being output through the switch group 119, the data (addresses 160 to 239 in FIG. 5) corresponding to the third switch group 120 is read out through the third switch group 120. While the voltage is being output, the data (addresses 240 to 319 in FIG. 5) corresponding to the fourth switch group 121 is read. The fourth control signal 125 is the common circuit 11
2 is disabled before selecting the next Y electrode. In this way, the writing of the display data 107 to the memory 207 and the output of the display data 126 from the memory 208 are completed for one line.

After that, when the next horizontal synchronizing signal 104 becomes valid, the display data 107 is written in the memory 208 this time. Then, the display data of the next row is read from the memory 207. In this way, the memories 207, 208
The read / write operation is alternately repeated between the display controller 102 and the display data 10
The display data 126 is output with a delay of one horizontal period from 7.

By repeating the above operation, the gradation voltage corresponding to the display data is sequentially output to the liquid crystal panel 101.

Next, regarding the operation of the common circuit 112,
This will be described with reference to FIGS. 1 and 6.

As shown in FIG. 6, when the first line marker (hereinafter abbreviated as "FLM") indicating the first line of the common control signal 117 and the line signal for instructing the switching of the selected line become valid, the common circuit is activated. 112
Outputs a selection voltage to the electrode y0 through the output bus 116. On the other hand, other Y electrodes (here, electrodes y1 to y23
The non-selection voltage is output to 9). Then, only the switching element of the electrode y0 becomes conductive. As a result, the gradation voltage applied to the X electrode at that time is applied only to the pixel in the row corresponding to the electrode y0.

When the line signal becomes valid next time, the common circuit 112 outputs the selection voltage to the electrode y1 this time. A non-selection voltage is output to the electrode y0 and the electrodes y1 to y239. As a result, the gray scale voltage applied to the X electrode at that time is applied only to the pixels in the row corresponding to the electrode y1.
By repeating this operation up to the electrode y239, the display for one screen is completed. After this, the display controller 102
Activates the FLM and outputs the selection voltage from the electrode y0 again sequentially.

By repeating the above-described operation, the liquid crystal display device of this embodiment can perform display corresponding to the display data.

A second embodiment of the present invention will be described with reference to FIGS. 7 to 10.

The present embodiment is different from the first embodiment in that the display data is input to the display controller and the display data is output from the display controller in parallel. Note that the following description will be focused on the differences from the first embodiment, and description of the same functional parts may be omitted.

First, the outline will be described.

As shown in FIG. 7, the liquid crystal display device of this embodiment has a liquid crystal panel 701, a column circuit 704 for driving the X electrodes of the liquid crystal panel 701, and a liquid crystal panel 70.
A common circuit 112 for driving the first Y electrode, a display controller 702 for operating the column circuit 704 and the common circuit 112 according to display data input from the outside, and a power supply circuit 109. Further, between the column circuit 704 and the X electrode of the liquid crystal panel 701, the switch groups 118 to 1 in the first embodiment are arranged.
A switch group 707 to 710 having the same configuration as that of
Is provided. Naturally, these and each part described below,
It is connected by a signal line and a bus for transmitting and receiving various signals.

The liquid crystal panel 701 has 960 pixels × 240.
It is an active matrix type of line.

The display controller 702 has a vertical synchronizing signal 103, a horizontal synchronizing signal 104, a blank signal 105,
The dot clock 106 and the display data 703 are input. Based on these inputs, the display controller 702 controls the alternating signal 108, the column control signal 115, the common control signal 117, the display data 705, and the switch control signals 122 to 122 to control the switch groups 707 to 710.
125 is generated and output.

In the display data 703 in this embodiment, three pixels are transferred simultaneously (in parallel) in synchronization with the dot clock 106. The display controller 702 transfers the display data 703 to each switch group 70.
The data are rearranged in the order corresponding to 7 to 710 and are output to the column circuit 110 as display data 705. As for the display data 705, three pixels are simultaneously sent in parallel. The display data buses 703 and 705 are naturally compatible with this.

The column circuit 704 stores the display data 705, and outputs the gradation voltage corresponding to the stored display data,
By outputting from the output bus 706 in synchronization with the output clock in the column control signal bus 115, the liquid crystal panel 7
01 is displayed. The column circuit 704 of this embodiment is capable of storing the display data 705, which is sent together for three pixels, at one time. Since the column circuit 704 has 240 outputs, the column circuit 704 repeats this storage operation 80 times,
The display data for 240 outputs is stored.

Since the common circuit 112 and the power supply circuit 109 are the same as those in the first embodiment, their explanations are omitted.

Next, the display controller 702 will be described in more detail with reference to FIG.

As shown in FIG. 8, the display controller 702 has a clock control unit 201, a memory control unit 801, a latch clock bus 802, a data latch circuit 803, a bus 804, and memory control signal buses 805 and 806 each for one line. 80 that can store display data
7, 808, data bus 80 of memories 807, 808
9, 810, bus selector 811, bus selector 812
Output bus 812, data latch circuit 813, and bus control signal line 206.

The memory control unit 801 is the clock control unit 2
01 based on the memory system control signal 202, the latch clock 802 and the memory control signals 805, 8
06 is generated. The latch clock 802 is sent to the data latch circuit 803, and the memory control signal 80
5, 806 are output to the memories 807, 808. The latch clock 802 defines the timing for fetching the display data 705 by the data latch circuit 803, and includes a signal synchronized with the dot clock 106. The memory control signals 805 and 806 are signals for designating / changing the operating states (read / write) of the memories 807 and 808, a clock for defining the read / write timing, and an address for reading / writing. And are included.

The data latch circuit 803 is for rearranging the display data 703 input in parallel for every three pixels in correspondence with the switch groups 707 to 710. The data latch circuit 803 outputs the rearranged display data from the output bus 804. The data latch circuit 803 will be described later in more detail with reference to FIG. The "converting means" referred to in the claims corresponds to the data latch circuit 803 in this embodiment.

The memories 807 and 808 are each capable of storing display data for one line. The memory 8
The operation states (writing / reading) of 07 and 808 are changed by the memory control signals 805 and 806 input from the memory control unit 801. In addition, input / output of display data is performed by the data buses 809 and 810.
Is done through.

Display data 80 in the memories 807 and 808
4 is stored in synchronization with the clock in the memory control signals 805 and 806. The display data is read from the memories 807 and 808 by using the memory control signals 805 and 805.
The configuration is performed in synchronization with the read clock 806.

The bus selector 811 outputs the output bus 804.
, The output bus 812, the data bus 809, and the data bus 810 are changed in accordance with the bus control signal 206. That is, the display data 804
Is stored in the memory 807 and display data is read from the memory 808 at the same time, the output bus 804
And the data bus 809, and the output bus 812 and the data bus 810. Conversely, when the display data 804 is stored in the memory 808 and the display data is read from the memory 807 at the same time, the output bus 804 is used.
And the data bus 810, and the output bus 8112 and the data bus 809.

The latch circuit 813 latches the display data read from the memory 807 (or 808) through the output bus 812 and outputs it as display data 705. The latch is performed according to the latch clock 214. The output of the display data 705 is performed in synchronization with the data transfer clock included in the column circuit control signal 115.

The data latch circuit 803 will be described in more detail with reference to FIG.

The data latch circuit 803 is the latch circuit 9
01-904, latch circuits 910-913, output bus 9
05 to 908, output buses 914 to 917, and a data selector 918.

The latch circuits 901 to 904 and the latch circuits 910 to 913 can latch the display data for three pixels at one time. These output the latched data from the output buses 905 to 908 and 914 to the output buses 914 to 914, respectively.
It is possible to output from 917.

The data selector circuit 918 is connected to the output bus 9
A predetermined one is selected from the display data output through 14 to 917, and this is output as display data 804 in synchronization with the latch clock 802. In the selection, the display data 804 is the switch group 707.
.About.710 are performed in an order so as to correspond to them.
The order of selection is actually specified by the latch clock 802 output from the memory control unit 801.
Details of the designation will be described in the operation description.

The operation of this embodiment will be described with reference to FIGS. The description here is centered on the display controller 702.

In FIG. 8, display data 703 is sent to the display controller 702 in synchronization with the dot clock 106. Then, the data latch circuit 803 outputs the display data 703 to 4 according to the latch clock bus 802.
Twice, that is, display data for 12 (3 × 4) pixels is latched. Further, the data latch circuit 803 is
The display data for two pixels is rearranged in the order corresponding to the switch groups 707 to 710 and output as the display data 804.

In the display data 804, the display data belonging to a certain switch group is collected every 3 pixels. That is, first, only the data corresponding to the first switch group 707 is output for three pixels. Then, only the data corresponding to the second switch group 708 is output for three pixels. After this, similarly, only the data corresponding to the third switch group and the fourth switch group are output for each three pixels. The operation of the data latch circuit 803 will be described in more detail later with reference to FIGS. 9 and 10.

The display data 804 is stored in either the memory 807 or the memory 808. If the bus control signal 206 is "low", the bus selector 81
1 makes the output bus 804 and the output bus 809 conductive. Therefore, the display data 804 output from the data latch circuit 803 at this time is written in the memory 807. When the bus control signal 206 is "high", the display data 804 output at this time is the memory 8
08 is written.

The address for writing the data is designated by the memory control unit 801 in correspondence with each of the switch groups 707 to 710. For example, since the data for the first three pixels corresponds to the first switch group 707, address 0 is designated. The data for the following three pixels is the second switch group 7
Since it corresponds to 08, the address 80 is designated. Next, the address 160 is designated for the data corresponding to the third switch group 709, and the address 240 is designated for the data corresponding to the fourth switch group 710. Since the liquid crystal panel of this embodiment has 960 X electrodes, the initial values of the addresses assigned to each switch group must be spaced by 80 or more.

In FIG. 10, the memory control unit 80
1 is synchronized with the trailing edge of the fifth clock of the dot clock 106 after the blank signal 105 becomes valid,
The write enable signal of the memory control signal 805 is validated. After that, the state (valid (low) / invalid (high) of the write enable signal is controlled in synchronization with the dot clock 106. In FIG.
4 is written in the memory 807 and the read operation described below is performed on the memory 808.

In parallel with the above storage operation, the memory 808
The display data is read from the memory cell and transferred to the column circuit 704.

The address of the data to be read is specified by the memory control signal 806 input from the memory control section 801. When the horizontal synchronization signal 104 becomes valid, the memory control unit 801 sequentially increments the designated address from 0 to 79 in synchronization with the read clock in the memory system control signal 202. The read clock is masked after output of 80 clocks. The read data is output to the output bus 810 and the bus selector 8
11, through the output bus 812, the data latch circuit 81
3 is output.

The data latch circuit 813 latches the display data 812 according to the latch clock 214.
After that, this is output to the column circuit 704 as display data 705 in synchronization with the data transfer clock in the column circuit control signal 115.

The column circuit 704 sequentially stores the display data 705. Then, the column control signal bus 115
When the output clock of 1 is enabled, the grayscale voltage is output to the output bus 706.

After the output clock becomes valid, the read clock becomes "valid" again for 80 clocks. At this time, the memory control unit 801 causes the display data from addresses “80” to “159” to be read from the memory 808. After this, the same processing is repeated.

By repeating the above read operation, the gradation voltage corresponding to the display data for one line stored in the memory 808 can be output.

Next, the operation of the data latch circuit 803 will be described.
This will be described in more detail with reference to FIGS. 9 and 10.

Here, in order to clarify the position displayed on the liquid crystal panel 701, the display data includes n-
We will use the number m. n is 960 X
When the electrodes (electrode x0 to electrode x959) are divided into four parts in order from the left side, the number indicates the area from the left side to which the electrode to which the display data is output belongs. m is a number indicating the position of the electrode to which the display data is output from the left side in the area. However, n and m shall start from 0. The position of the electrode, which outputs certain display data nm, in the entire X electrode can be represented by 3n + m. In other words, display data n-
m is data output to the electrode x (3n + m). For example, the display data 0-0 corresponds to the electrode x0 of the liquid crystal panel 701.
Is the display data. The display data 0-1 is to be output to the electrode x1, and the display data 0-2 is to be output to the electrode x2.

The operation timing of each part of the data latch circuit 803 is determined according to the latch clock 802. The latch clock 802 includes five types of latch clocks (hereinafter referred to as “first latch clocks”).
~ "Fifth latch clock") is included.

As shown in FIG. 10, the first to fourth latch clocks are validated every four cycles of the dot clock 106. These are sequentially delayed from the first clock by one cycle of the dot clock 106. The fifth latch clock is validated once every four cycles of the dot clock 106. The fifth latch clock is delayed in phase from the fourth latch clock by a half cycle of the dot clock 106.

In FIG. 10, when the blank signal 105 becomes valid, the first latch clock becomes valid in synchronization with the first falling edge of the dot clock 106. Then, in synchronization with this, the latch circuit 901 latches the display data 0-0 to the display data 0-2 of the display data 703. Following this, similarly, the latch circuits 902 to 904 also latch the display data of 12 pixels of the display data 1-0 to 3-2 in synchronization with the second latch clock to the fourth latch clock. .

The latch circuits 901 to 904 output the latched display data to the latch circuits 910 to 914 at once in synchronization with the fifth latch clock. Latch circuit 9
10 to 914 latch this, and continue to output from the output buses 914 to 917 until the fifth latch clock becomes "valid" next time.

The data selector 918 is a latch circuit 90.
Of the data of 12 pixels which are simultaneously output from 1 to 904, the display data string corresponding to the first switch group 707 (here, the display data 0-0, 1-1 corresponding to the electrodes x0, x4, x8). , 2-2) is selected and output as display data 804 to the bus selector 811.
The output in this case is executed in synchronization with the next first latch clock.

Subsequently, the data selector 918 selects only the display data string corresponding to the second switch group 708,
This is output to the bus selector 811 as display data 804. In this case, the output is performed in synchronization with the second latch clock. Similarly, the data selector 918
Is the third switch group 70 in synchronization with the third latch clock.
The display data corresponding to No. 9 is output as the display data 804 in synchronization with the fourth latch clock, and the display data corresponding to the fourth switch group 710 is output.

According to the second embodiment described above, it is possible to cope with the high definition of the liquid crystal panel for the display data input in parallel without changing the column circuit 704 or the like.

A third embodiment of the present invention will be described.

The third embodiment is different from the second embodiment in that the data read clock from the memory and the data write clock to the memory are asynchronous with each other.

As shown in FIG. 11, the liquid crystal display device of this embodiment has a liquid crystal panel 701, a column circuit 704 for driving the X electrodes of the liquid crystal panel 701, and a liquid crystal panel 7.
The common circuit 112 for driving the Y electrode 01, the display controller 1101 for operating the column circuit 704 and the common circuit 112 according to the display data input from the outside, the power supply circuit 109, and the switch group 70.
7 to 710 are included. Furthermore, in the present embodiment, the external clock 1 is added to the display controller 1101.
An oscillator 1102 for supplying 103 is provided. As will be described later, the external clock 1103 is used as a basis of a read clock of display data from the memory.

As described above, the display controller 11
01 is various input signals 103, 104, 105, 10
6. In addition to the display data 703, the external clock 1103 input from the oscillator 1102 is input. The display controller 1102, based on these inputs, displays data 705 and various signals 115, 122 to 125,
108, 117, etc. are generated and output in synchronization with the external clock 1103.

Details of the display controller 1101 are shown in FIG.
Will be explained.

As shown in FIG. 12, the display controller 1101 includes a clock controller 1201 and a clock controller 1.
203, memory control unit 1205, bus selector 120
8, memories 1213, 1214, data latch circuit 80
3. The data latch circuit 813 is included.
Further, each of these units is connected to each other, and various buses and signal lines for exchanging data and signals are provided. Note that, in order to simplify the drawing, in FIG. 12, the signals 115, 122 to 125, 108, 117 in FIG. 11 are collectively shown as a signal 1126.

The clock controller 1201 writes the write control signal 1 based on the vertical sync signal 103, the horizontal sync signal 104, the blank signal 105, and the dot clock 106.
202 and a latch clock 802 are generated.

The write control signal 1202 includes a vertical synchronizing signal 103, a horizontal synchronizing signal 104, and a write clock. The vertical synchronization signal 103 and the horizontal synchronization signal 104 are used by the memory control unit 1205 to determine which line the display data 804 is. The write clock is for notifying the memory control unit 1205 of the time range in which the display data 804 is valid.

The clock control unit 1203 synchronizes with the external clock 1103 and reads the memory read control signal 120.
4, the signal 1216 and the latch clock 214 are generated.

The memory control unit 1205 uses the memory 121
It controls writing of data to and reading of data from them. The memory control unit 1205 uses the write control signal 1202 and the read control signal 1204 to control the dot clock 106.
Memory write control signal 1206 synchronized with the memory read control signal 12 synchronized with the external clock 1103
07 and the bus control signal 206 are generated and output to the selector 1208.

The memory write control signal 1206 and the memory read control signal 1207 are composed of a read enable signal, a write enable signal, an address signal and a data signal, respectively (see FIG. 13). The read enable signal is for indicating the completion of reading. The bus control signal 206 and the read enable signal are also output to the clock control unit 1203 via the bus 1204.

The data latch circuit 803 and the data latch circuit 813 have the same functions as in the second embodiment.

Each of the memories 1213 and 1214 has one
It has a capacity capable of storing display data for the screen. The way of arranging the display data in the memories 1213 and 1214 is basically the same as in the first and second embodiments (FIG. 5).
reference). However, in this embodiment, since data for one screen is stored, as shown in FIG. 14, the data of each line is equal to the number of scanning lines of the liquid crystal panel (240 in this embodiment). ) Are arranged side by side. Such data arrangement is performed by the memory control unit 1205.
It is realized by the method of specifying the address from.

The bus selector 1208 uses the bus control signal 2
According to 06, bus 804, bus 1215, bus 1
The connection relationship between the 211 and the bus 1212 is changed. Also, a write control signal bus 1206, a read control signal bus 1207, and memory control buses 1209, 1
The connection relationship with 210 is changed.

When the bus control signal 206 is "high", the bus selector 1208 writes the display data 804 in the memory 1213 and reads the display data from the memory 1214. That is, the memory control bus 1209 and the write control signal bus 1206 and the output bus 8804 and the data bus 1211 are brought into conduction. Further, the output bus 1215 and the memory data bus 1212 are connected to each other, and the memory control bus 12 is
10 and the memory write signal bus 1207 are brought into conduction.

On the other hand, when the bus control signal 206 is "low", the display data 804 is written in the memory 1214 and the display data is read from the memory 1213. That is, the memory control bus 1210 and the write control signal bus 1206, and the output bus 80
4 and the data bus 1212 are brought into conduction. Further, the output bus 1215 and the memory data bus 1211 and the memory control bus 1209 and the memory write signal bus 1207 are brought into conduction.

The operation of this embodiment will be described with reference to FIG.

In FIG. 11, the operation of this embodiment is performed by the alternating signal 108, the column control signal bus 115, the common control signal bus 117, the first control signal 122, and the second control signal 1.
23 is the same as the second embodiment except that the third control signal 124, the fourth control signal 125, and the display data 705 are output in synchronization with the external clock 1103. Therefore, only the internal operation of the display controller 1101 will be described here.

The clock control units 1201 and 1203 have signals 103, 104, 105 and 1 input from the outside.
Based on 06, 1103, various signals 802, 120
2, 11204, 214, and 1216 are output.

The memory controller 1205 also generates a memory write control signal 1206 and a memory read control signal 1207 from the write control signal 1202 and the read control signal 1204, and outputs them to the selector 1208. Also, the bus control signal 206 is output to the selector 1208.

The data latch circuit 803 fetches the display data 703 in synchronization with the latch clock 802 input from the clock controller 1201, rearranges the display data 703, and then displays the display data corresponding to each of the switch groups 707 to 710. Output as 804. The details of the rearrangement are the same as in the second embodiment. 3 corresponding to a certain switch group
Data for pixels are sequentially output as display data 804 for each switch group.

The memory control unit 1205 has the selector 120.
8, the display data 804 for one screen is stored in the memory 1
213 or memory 1214. In parallel with this, the memory 121 is synchronized with the read clock output from the clock controller 1203.
The display data for one screen is read from 3 (or 1214). The display data is read from the memory in which the data writing operation is not performed at that time, as in the other embodiments.

The data latch circuit 813 is connected to the memory 121.
The display data read from No. 3 (or 1214) is latched in synchronization with the latch clock 214. And
The display data is output as the display data 705 in synchronization with the transfer clock included in the column control signal 115 (the signal 1216 in FIG. 12).

As shown in FIG. 13, the memory controller 120
5 completes the read operation, the memory control signal 1207
The read enable signal therein is made invalid ("low" in this embodiment). The clock control unit 1203 receiving this read enable signal suspends the output of the read clock.

Memory 1213 of display data for one screen
Upon completion of storage in and read from the memory 1214, the memory control unit 1205 changes the state (high / low) of the bus control signal 206, as shown in FIG.

Then, in response to this, the selector 1208
The memory for storing the display data 804 and the memory for reading the display data are switched next time. Further, the clock control unit 1203 initializes itself in response to the state change of the bus control signal 206.
Then, in preparation for the display of the next screen, the generation of the signal 1216 is started again. Further, the clock control unit 1203 restarts the output of the read clock to the memory control unit 1205. The memory control unit 120 that has received the read clock
5 is the address "0" in synchronization with the read clock
The display data is sequentially read from.

By repeating the above operation, the liquid crystal display device of the present embodiment is capable of displaying on the liquid crystal panel 701 while having two asynchronous clocks.

A fourth embodiment will be described.

The fourth embodiment is characterized in that a switch group for selecting the output of the common circuit is arranged between the common circuit and the Y electrode of the liquid crystal panel, and this is controlled by the display controller. Is different from. Other points are basically the same as in the first embodiment. This embodiment is applied when the number of outputs of the common circuit is smaller than the number of lines of the liquid crystal panel.

The liquid crystal display device of this embodiment will be described with reference to FIG.

The liquid crystal panel 101 itself is the same as that in the first embodiment. However, in this embodiment, 240 Y are provided.
The electrodes are divided into two groups, and application of the selection / non-selection voltage is controlled. Hereinafter, the Y electrodes located in the upper half region in FIG. 15 will be referred to as a first common bus 1610,
On the other hand, the Y electrode located in the lower half area is called the second common bus 1611.

The switch groups 1606 to 1609 include the Y electrodes of the liquid crystal panel and the output bus 160 of the common circuit 1603.
4 and the non-selection voltage signal line 1605 from the power supply circuit 109
It is for changing the connection relationship with.

The non-selection voltage generated by the power supply circuit 109 is
It is also output through the non-selection voltage signal line 1605 that branches out from the middle of the scanning voltage bus 113. The non-selection voltage signal line 1605 is connected to the second switch group 1 described above.
607 through the liquid crystal panel first common bus 1610,
Further, it is configured to be connectable to the second common bus 1611 through the fourth switch group 1609.

The common circuit 1603 outputs a selected voltage to any one of the output terminals y0 to y119 forming the output bus 1604 and a non-selected voltage to the other.
The common control signal 16 input from the display controller 1601 determines which output terminal outputs the selected voltage.
02.

The output bus 1604 of the common circuit 1603 of this embodiment can be connected to the first common bus 1610 through the first switch group 1606 and the second common bus 1611 through the third switch group 1608.

The display controller 1601 generates and outputs a common control signal 1602 for controlling the common circuit 1603. Furthermore, switch groups 1606 to 16
It is configured to output a first control signal 1612 and a second control signal 1613 for controlling 09. These control signals 1612 and 1613 correspond to the clock control unit 2 of FIG.
01 is generated. The internal configuration of the display controller 1601 is basically the same as that of FIG. Naturally, the first control signal 122 for controlling the switch groups 118 to 121 is
~ The fourth control signal 125 is also output.

When applying the selection voltage to any of the Y electrodes belonging to the first common bus 1610, the display controller 1601 turns on the first switch group 1606 and the fourth switch group 1609, while turning on the second switch group 1609. The switch group 1607 and the third switch group 1608 are turned off. Accordingly, the first common bus 161
The output from the common circuit 1603 is applied to 0, and the non-selection voltage signal 1605 is applied to the second common bus 1611. On the contrary, when the selection voltage is applied to any of the Y electrodes belonging to the second common bus 1611, the first switch group 1606 and the fourth switch group 1609 are turned off.
On the other hand, the second switch group 1607 and the third switch group 1608 are turned on. As a result, the non-selection voltage signal 1605 is applied to the first common bus 1610,
The output from the common circuit 1603 is applied to the common bus 1611.

The "Y electrode switch means" referred to in the claims is realized by the switch groups 1606 to 1609. What is a "group" of Y electrodes?
It corresponds to the first common bus 1610 and the second common bus 1611.

The operation of this embodiment will be described with reference to FIGS.

The operation of this embodiment is basically the same as that of the first embodiment except the operation of the common circuit 1603. Therefore, only the operation of the common circuit 1603 will be described here.

During the period in which any of the Y electrodes belonging to the first common bus 1610 should be selected, the display controller 1601 sets the first control signal 1612 to “valid” (high).
In addition, the second control signal 1613 is set to "invalid" (low). As a result, the first switch group 1606 and the fourth switch group 1609 are turned on (conduction state), while the second switch group 1607 and the third switch group 1608 are turned off.
F (blocking state). In this state, the Y electrode belonging to the first common bus 1610 receives the selection / non-selection voltage 1604 output from the common circuit 1603, while the Y electrode belonging to the second common bus 1611 has the non-selection voltage 1605.
Will be applied. During this time, the common circuit 1603 scans within the range of the first common bus 1610 by sequentially changing the output terminals that output the selection voltage in the order of y0 → y1 → y2 → ... → y199 in synchronization with the line signal. It is carried out.

After the scanning of the Y electrodes (electrodes y0 to y119) belonging to the first common bus 1610 is completed (that is, after the electrode y199 is selected), the display controller 1601 turns the second control signal 1613 "valid". ”
(High), and the first control signal 1612 is set to "invalid".
(Low) As a result, the first switch group 1606 and the fourth switch group 1609 are turned off (cutoff state),
On the other hand, the second switch group 1607 and the third switch group 1
608 is turned on (conductive state). In this state, the first
The non-selection voltage 1 is applied to the Y electrodes belonging to the common bus 1610.
605, on the other hand, the selection / non-selection voltage 1604 output from the common circuit 1603 is applied to the Y electrode belonging to the second common bus 1611. As a result, the Y electrodes to which the selection voltage output from the common circuit 1603 is applied are y120 → y121 → y122 → ... → y239.
Then, it will be changed sequentially.

The display controller 1601 is the first
The valid (high) / invalid (low) change of the control signal 1612 and the second control signal 1613 is performed based on the timings of the FLM and line signals. In the example shown in FIG. 16, the common circuit 1603 outputs the selection voltage to the output terminal y0 when the line signal becomes valid while the FLM signal in the common control signal 1602 is high. It is supposed to do. Common circuit 1603
Next time, the selection voltage is output to the output terminal y0 after 120 clocks of the line signal 1602 have been output, that is, when the selection voltage is applied to the electrode y120.

In the present embodiment, even if the output bus of the common circuit 1603 is smaller than the number of Y electrodes of the liquid crystal panel, the electrodes y0 to y239 of the liquid crystal panel can be sequentially scanned.

According to the first to fourth embodiments described above, it is possible to easily cope with the high definition of the liquid crystal panel. Also,
Even if the number of pixels or lines of the liquid crystal panel is changed, it can be dealt with by increasing the storage capacity of the memory according to the increase.

When the number of valid data items of display data is larger than the number of display items on the liquid crystal panel, it is possible to display only a predetermined area portion of the display image on the liquid crystal panel. To achieve this, the display controller is provided with a register that stores coordinate values indicating the range of the image area to be displayed on the liquid crystal panel. Then, the display position of the input display data is compared with the coordinate value stored in the register, and only the display data for the image area designated in the register may be stored in the memory.
By doing so, an image having an aspect ratio different from that of the liquid crystal panel can be displayed.

In the above embodiment, the rearrangement is performed when the display data is written in the memory, but the rearrangement may be performed when the display data is read. For example, at the time of writing, display data are arranged and stored in the order of input as usual. Then, when reading a series of display data corresponding to a certain switch group at the time of reading, the address may be incremented by four. When reading the data corresponding to the first switch group, addresses 0, 4, 8 ... Are designated.

In the present embodiment, the display controller can be miniaturized by using one LSI.

[0178]

According to the present invention, high definition of a liquid crystal panel can be achieved without reducing the output pitch of the common circuit and the column circuit which are liquid crystal drive circuits.

Even if the write clock and the read clock are asynchronous clocks, it is possible to handle them by having a memory for one screen.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a liquid crystal display device that is a first embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a display controller 102.

FIG. 3 is a timing chart of writing / reading data to / from memories 207 and 208.

FIG. 4 is a timing chart of control signals 122 to 125 for activating switch groups 118 to 121.

FIG. 5 is a map showing an arrangement state of display data in memories 207 and 208.

FIG. 6 is a timing chart of signals for controlling the common circuit 112.

FIG. 7 is an overall block diagram of a liquid crystal display device that is a second embodiment of the present invention.

8 is a block diagram showing an internal configuration of a display controller 702. FIG.

9 is a block diagram showing an internal configuration of a data latch circuit 803. FIG.

FIG. 10 is a timing chart of an operation of storing / reading display data in the memories 207 and 208.

FIG. 11 is an overall block diagram of a liquid crystal display device that is a third embodiment of the present invention.

12 is a block diagram showing an internal configuration of a display controller 1101. FIG.

FIG. 13 is a timing chart of a storage / readout operation of display data in the memories 1213 and 1214.

FIG. 14 is a memory map showing a layout of display data in memories 121 and 1214.

FIG. 15 is an overall block diagram of a liquid crystal display device that is a fourth embodiment of the present invention.

FIG. 16 is a timing chart showing the relationship between the output voltage of the common circuit 1603 and the voltage applied to the y electrode.

FIG. 17 is a configuration diagram of a liquid crystal display device of a conventional example.

FIG. 18 is a timing chart of a conventional example.

FIG. 19 is a configuration diagram of a conventional column circuit HD66310.

[Explanation of symbols]

101 ... Liquid crystal panel, 102 ... Display controller, 10
3 ... Vertical sync signal, 104 ... Horizontal sync signal 105 ... Blank signal, 106 ... Dot clock, 107 ... Display data bus, 108 ... Alternate signal 109 ... Power supply circuit, 110
... column circuit, 111 ... gradation voltage bus, 112 ... common circuit, 113 ... scanning voltage bus, 114 ... output bus, 11
5 ... Column control signal bus, 116 ... Output bus, 117 ...
Common control bus 118 ... First switch group, 119 ... Second
Switch group, 120 ... Third switch group, 121 ... Fourth switch group, 122 ... First control signal, 123 ... Second control signal, 124 ... Third control signal, 125 ... Fourth control signal, 1
26 ... Display data bus, 127 ... Opposing voltage line, 201 ...
Clock control unit, 202 ... Memory system control bus, 203 ...
Memory control unit, 204 ... Memory control bus, 205 ... Memory control bus, 206 ... Bus control signal, 207 ... Memory,
208 ... Memory, 209 ... Data bus, 210 ... Data bus, 211 ... Bus selector, 212 ... Output bus, 21
3 ... Latch circuit, 214 ... Latch clock, 701 ... Liquid crystal panel, 702 ... Display controller, 703 ... Display data bus, 704 ... Column circuit, 705 ... Display data bus, 706 ... Output bus, 707 ... First switch group, 70
8 ... 2nd switch group, 709 ... 3rd switch group, 710
... Fourth switch group, 801 ... Memory control unit, 802 ... Latch clock bus, 803 ... Data latch circuit, 804
Output bus 805 Memory control signal bus 806 Memory control signal bus 807 Memory 808 Memory
809 ... Data bus, 810 ... Data bus, 811 ... Bus selector, 812 ... Output bus, 813 ... Data latch circuit, 901-904 ... Latch circuit, 905-908 ...
Output bus, 910-913 ... Latch circuit, 914-91
7 ... Output bus, 918 ... Data selector circuit, 1101
Display controller 1102 Oscillator 1103 External clock 1201 Clock control unit (1) 120
2 ... Write control signal bus, 1203 ... Clock control unit (2), 1204 ... Read control signal bus, 1205 ...
Memory controller 1206 ... Memory write signal bus, 1
207 ... Memory read control signal bus, 1208 ... Bus selector, 1209 ... Memory control signal bus, 1210 ...
Memory control signal bus, 1211 ... Memory data bus, 1
212 ... Memory data bus, 1213 ... Memory, 121
4 ... Memory, 1215 ... Data bus, 1216 ... Control signal bus, 2100 ... Column circuit, 2101 ... Signal line, 2
103 ... Latch circuit, 2104 ... Clock, 2105 ...
Enable signal, 2110 ... Driver control means, 211
1 ... Clock, 2120 ... Data conversion circuit, 2121 ...
Frequency divider circuit, 2122 ... Delay circuit, 2130 ... Column circuit group, 2131 ... Scan drive circuit, 2132 ... Liquid crystal panel,
2401 ... Display data, 2402 ... Sync signal, 2301
... Latch address counter 2302 ... Latch circuit, 2
303 ... Latch circuit, 2304 ... Level shifter circuit, 2
305 ... Liquid crystal drive circuit, 2306 ... Liquid crystal drive voltage

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Makiko Ikeda 1099 Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Ltd. System Development Laboratory, Hitachi, Ltd. (72) Inventor Yasushi Ikegami 292, Yoshida-cho, Totsuka-ku, Yokohama Inside the Hitachi Imaging Information System (72) Inventor Takeshi Tanaka 7-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Toshio Futami 3300 Hayano, Mobara-shi, Chiba Co., Ltd. Hitachi, Ltd. Electronic Devices Division (72) Inventor Satoru Tsunekawa 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Division

Claims (7)

[Claims] 1. An active matrix type liquid crystal panel having M Y electrodes and N X electrodes, and a function of generating a selection voltage, a non-selection voltage, and a plurality of kinds of gradation voltages. A power supply circuit including a selection voltage terminal for outputting the selection voltage, a non-selection voltage terminal for outputting the non-selection voltage, and a gradation voltage terminal for outputting the gradation voltage; <N) output terminals are provided, and any one of the grayscale voltages output from the power supply circuit is selected for each output terminal corresponding to a separately given data string, and the selected grayscales are selected. A column circuit for outputting a voltage from the output terminal, a common means for applying the selection voltage to any one of the Y electrodes, and a non-selection voltage for the other Y electrodes, and n constituent elements. The X electrodes are classified into the following groups. Select one of the groups,
X electrode switch means for connecting only the X electrodes belonging to the selected group to the output terminals of the column circuit in a predetermined correspondence relationship, and at least display data and a horizontal synchronizing signal are externally input. A display controller that rearranges the order of the display data input from the outside and sequentially outputs the display data to the column circuit for each set of display data in which the groups to which the corresponding X electrodes belong match each other. Liquid crystal display device characterized by. 2. The display controller comprises: a first memory capable of storing at least one line of data; a second memory capable of storing at least one line of data; and display data input from the outside. Of the first memory and the second memory, the writing means for writing into the first memory or the second memory, and the one that is not the execution target of the writing operation by the writing means at that time. From the above, the display data already stored in the memory is sequentially read and output for each set of display data in which the groups to which the corresponding X electrodes belong to each other, and the column circuit is provided in a certain group. After the output of the gray scale voltage to the X electrodes belonging to the above is finished and before the output of the gray scale voltage corresponding to the X electrodes of the next group is started, Selection instructing means for changing the selection of the group by the X electrode switch means so that the X electrode of the next group and the output terminal of the column circuit are connected, and a target of the writing operation of the display data by the writing means And a control means for alternately switching between the first memory and the second memory when the horizontal synchronization signal becomes valid. Characteristic liquid crystal display device. 3. The liquid crystal display device according to claim 1, wherein the display data is input from the outside in parallel, and the display data input from the outside is equal to a predetermined number of pixels. It further comprises a conversion unit that receives and classifies the received display data based on a group to which the X electrode to which the display data corresponds corresponds, and outputs the classification data for each classification. The writing unit outputs the writing unit. A liquid crystal display device, wherein display data is written in the first memory or the second memory. 4. The liquid crystal display device according to claim 1, wherein the write means performs the write operation in synchronization with a separately generated write clock, and the read means is the write clock. The reading is performed in synchronism with an asynchronously generated read clock, and the control unit switches the memory to which the display data is written by the writing unit instead of the horizontal synchronization signal. And confirming that the display data for one screen has been written, and the first memory and the second memory are storage capacities capable of storing the display data for one screen of the liquid crystal panel. A liquid crystal display device comprising: 5. The liquid crystal display device according to claim 1, wherein the common means includes m (m <M) output terminals, one of the output terminals is sequentially selected, and the selected one of the output terminals is selected. A common circuit that outputs the selected voltage from the output terminal and a non-selected voltage from the other output terminal and the Y electrode are divided into a plurality of groups each having m or less constituent elements, and a Y belonging to any one of the groups. Only the electrodes are selectively connected to the output terminal of the common circuit in a predetermined correspondence relationship, and the Y electrode which is not connected to the common circuit at that time is connected to the non-selected voltage terminal of the power supply circuit. Y electrode switch means, and the display controller changes the selection of the group by the Y electrode switch means each time the common circuit finishes selecting all output terminals. A liquid crystal display device characterized by: 6. The liquid crystal display device according to claim 1, wherein the storage capacities of the first memory and the second memory are changeable. 7. An active matrix type liquid crystal panel having M Y electrodes and N X electrodes, and n (n <N) output terminals, which are separately provided from the output terminals. A column circuit which outputs a grayscale voltage corresponding to the selected data string, and the X electrodes are classified into a plurality of groups each having n or less constituent elements, and any one of the groups is selected,
A display used for driving a liquid crystal display device including X electrode switch means for connecting only the X electrodes belonging to the selected group to the output terminals of the column circuit in a predetermined correspondence relationship. In the controller, the first memory that can store at least one line of data, the second memory that can store at least one line of data, and the display data that is input from the outside A writing unit that writes to the memory or the second memory, and one of the first memory and the second memory that is not the target of the writing operation by the writing unit at that time, and is already stored in the memory. The displayed display data is sequentially read for each set of display data in which the above-mentioned groups to which the corresponding X electrodes belong match each other. The reading means for outputting and outputting and the column circuit after outputting the gradation voltage to the X electrodes belonging to a certain group and before starting the output of the gradation voltage corresponding to the X electrodes of the next group, Selection instructing means for changing the selection of the group by the X electrode switch means so that the X electrode of the next group and the output terminal of the column circuit are connected; and a writing operation of the display data by the writing means. Control means for alternately switching the target memory between the first memory and the second memory when the horizontal synchronization signal becomes valid. Display controller characterized by.