JPH096319A - Picture display device - Google Patents

Abstract

PURPOSE: To provide a picture display device which can scroll with a dot as unit without using such constitution that character data loaded in a storage means is selected by a multiplexer in accordance with scroll quantity, because that constitution causes occurrence of delay. CONSTITUTION: A shift register 14 stores (loads) character data from a latch 13. Since its timing is changed by offset quantity of a horizontal offset register 3 indicating scroll quantity by a load signal of a load timing generation section 9, output data of the shift register 14 can be preceded by a time (dot) in accordance with scroll quantity from display start timing ('H' level state of DISP), in display start timing, display is performed from a dot of a prescribed order constituting one line of a character, scroll in the horizontal direction of a dot unit can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device such as a personal computer or a video game machine capable of screen scroll display.

[0002]

2. Description of the Related Art As a conventional image display device of this type, Japanese Patent Publication No. 63-32472 proposes a display symbol winding device. This device divides a register for designating a scroll amount into two parts, a first part and a second part, in horizontal scrolling, and maps a displayed character based on a first part and a horizontal counter value. The address for the memory (stadium RAM) that is currently stored is specified, and the data in this stadium RAM is given as an address to the character image memory (graphic PROM) to extract the image data of the character. Then, the image data of the extracted character is converted from parallel to serial data, further held in a shift register, the signal from the second portion is input to a multiplexer, and the output of the shift register is selected, whereby the horizontal direction is changed. I am trying to scroll.

[0003]

However, in the above-mentioned conventional image display device, scroll image data is obtained by passing the output of the shift register through the multiplexer, so that a delay occurs due to the time of the selection operation by the multiplexer. This delay is a major drawback when considering the following. That is, in consideration of colorization of image display, normally, the output of the shift register once becomes an address of the color look-up table, the output of the table receiving this address is converted into RGB signals, and the display screen height is increased. Although the speeding up of the color conversion is required due to the finer definition, the delay of the selection process becomes an obstacle to the speeding up.

Further, in order to cope with colorization and high definition of image display, it is necessary to increase the amount of data fetched from the image memory at one time and to provide a plurality of shift registers. Due to the increase in the amount of data, the number of bits of the multiplexer increases, and it is necessary to provide the multiplexers in multiple stages, which increases the circuit scale.

In view of the above circumstances, that is, a delay occurs in the configuration in which the character data loaded in the storage means is selected by the multiplexer according to the scroll amount, the present invention does not rely on the configuration, but in dot units. An object is to provide an image display device capable of horizontal scrolling.

[0006]

An image display device of the present invention is an image display device for displaying a plurality of characters each having a predetermined number of dots on a display screen, and stores a display array of the characters. First storage means, character data forming an image of a character are stored, and second storage means for outputting character data in accordance with the data of the first storage means and second storage means for output. A third storage means for storing the character data, a fourth storage means for storing the character data output from the third storage means, and sequentially outputting the character data according to a dot display timing; Fifth storage means for holding data indicating at least the horizontal offset amount of the display array of the storage means, and at least water in display dots on the display screen. Position and a counter for counting,
Address generation means for generating an address for the first storage means based on the offset amount indicated by the data of the fifth storage means and the counter value of the counter;
First character timing generation means for generating a timing at which the character data output from the second memory means is stored in the third memory means based on the counter value of the counter, and output from the third memory means. Second storage timing generation means for generating the timing for storing the character data to be stored in the fourth storage means based on the counter value of the counter and the offset amount, and the character sequentially output from the fourth storage means. Means for displaying a character on the display screen based on the data.

The first storage means has a storage capacity corresponding to or greater than the number of characters displayed on the display screen, and is writable. Good.

Further, the second storage means has a storage capacity for holding display data for each type of the character, and may be configured to be read-only or writable.

The third storage means may be at least one register having the same bit amount as the bit amount of the character data output from the second storage means. It may be configured.

Further, the fourth storage means loads the data of the third storage means by the timing signal from the second storage timing generation means, and loads the loaded data in the non-input state of the timing signal. May be configured by a shift register that shifts according to the dot display timing.

Further, the fifth storage means includes the number of dots forming the character and the number of horizontal dots and vertical lines in a display space formed by the display arrangement of each character shown by the first storage means. It may be configured by a register having a bit amount corresponding to.

Further, two or more sets of the third storage means, the fourth storage means, and the fifth storage means are provided for each of a plurality of images, and the first storage timing generation means is the third storage means. The first storage timing may be output to each of the storage means, and the second storage timing generation means may be configured to output the second storage timing to each of the fourth storage means.

[0013]

According to the above construction, the third storage means stores the character data from the second storage means at the first storage timing, and the fourth storage means stores the character data from the third storage means. Is changed by the offset amount of the fifth storage unit, which indicates the scroll amount, at the second storage timing. Therefore, the output data of the fourth storage unit is set to a time (dot) corresponding to the offset amount. Can be preceded only by the display start timing, and at the display start timing, the character 1
It is possible to realize horizontal scrolling in dot units by displaying from the predetermined number of dots forming the line. In this way, the data loading timing of the fourth storage means is controlled (that is, the offset is considered in advance when the data is loaded into the fourth storage means). It is possible to avoid a delay such as a configuration in which all the data of one line is loaded and the output of the loaded data is selected.

[0014]

【Example】

(Embodiment 1) The present invention will be described below with reference to the drawings showing the embodiment.

FIG. 1 shows the configuration of a display screen in the image display device of this embodiment. The display screen is horizontal 25
It consists of 6 dots and 256 lines in the vertical direction.
The character is composed of 8 dots × 8 dots. Of course,
This is an example, and it is not limited thereto.

FIG. 2 is a table memory 1 shown in FIG. 5, which will be described later.
0 is an explanatory diagram of the image memory 12, FIG. 3 is an explanatory diagram of the image memory 12 of FIG. 5, and FIG. 4 is an explanatory diagram of the offset registers 3 and 4 of FIG.

FIG. 5 is a block diagram showing a schematic configuration of a display data generating section in the image display device of this embodiment.

The horizontal counter 1 counts a dot clock (dot display timing) indicating one dot display period. This count value becomes data (9 bits) corresponding to the horizontal dot display position in one horizontal period including the horizontal blanking period. The horizontal counter 1 outputs a vertical count enable signal each time the count value makes one round (corresponding to one horizontal period including the horizontal blanking period).

The vertical counter 2 is the horizontal counter 1 described above.
Each time it receives a vertical count enable signal from, the dot clock is counted. This count value becomes data (9 bits) corresponding to the dot display position in the vertical direction in one screen display period including the vertical blanking period.

The horizontal counter 1 is the same as that shown in FIG.
As shown in, the counter value becomes “008H” when the first display dot in the horizontal direction is output, and the counter value becomes “1” when the 256th display dot is output.
It operates so as to become 07H ". Also, the vertical counter 2
Indicates that the counter value becomes “000H” at the time of output of the first vertical display line,
It operates so that the counter value becomes "0FFH" at the time of outputting the line.

The horizontal offset register (fifth storage means) 3 is a register for outputting a horizontal scroll amount (offset amount) of character display as a 9-bit signal (see FIG. 4 (a)). The register (fifth storage means) 4 is a register for outputting a vertical scroll amount (offset amount) of character display as a 9-bit signal (see FIG. 4B).

The carry generating means 5 outputs the low-order 3 bit signal HO [2: 0] from the horizontal offset register 3 to "0".
In the case of "00", "L" is output, and in other cases, "H" is output.

The horizontal adder 6 inputs the upper 6-bit signal HO [8: 3] from the horizontal offset register 3 and the upper 6-bit signal H [8: 3] from the horizontal counter 1,
Add these. This addition output becomes an address indicating the horizontal display position in character units, which takes into account the horizontal scroll amount in character units, and forms a part of the address for the table memory 10 described later.

The vertical adder 7 receives the 9-bit signal V [8: 0] from the vertical offset register 4 and the vertical counter 2
The 9-bit signal V [8: 0] from is input and these are added. The high-order 6-bit signal SV [8: 3] of the addition output SV [8: 0] becomes an address indicating the vertical display position in character units in consideration of the vertical scroll amount in character units, and is an address for the table memory 10. Become part of. Also, the lower 3 bits SV [2:
0] becomes a part of the address (lower address) of the image memory 12, and specifies one of the eight lines forming the character.

The display timing generator 8 inputs the 9-bit signal of the horizontal counter 1 and the 9-bit signal of the vertical counter 2, and inputs a vertical synchronizing signal (VSYNC), a horizontal synchronizing signal (HSYNC), and a display period signal DISP. Is output. As can be seen from FIG. 1, the output of the display period signal DISP is such that the counter value of the horizontal counter 1 is “008H ...
The counter value of the vertical counter 2 becomes "H" level during 107H "and between" 000H-0FFH ".

The load timing generator 9 is configured to lower the lower 3 bits H of the 9-bit signal of the horizontal offset register 3.
O [2: 0] and the lower 3 bits H [2: 0] of the 9-bit signal of the horizontal counter 1 are input, and a load signal is output based on these signals. The load signal is output because the inverted value of each bit of the lower 3 bits HO [2: 0] and each bit of the lower 3 bits H [2: 0] match (the inverted value of HO [2] = Inverted value of H [2], HO [1] = H [1], HO

Inversion value of [0] = H

[0]). By the output of this load signal, data loading of the shift register 14 described later is instructed.

For example, when the horizontal offset is "0",
The inverted value of the lower 3 bits HO [2: 0] is “111”, and the lower 3 bits H [2: 0] is “111”, that is,
As shown in FIG. 6, when the horizontal counter value becomes "7", the load signal becomes "H", and when the horizontal counter value becomes "8", the output of the latch 13 described later is loaded. . If the horizontal offset is “3”,
The inverted value of the lower 3 bits HO [2: 0] is "100", and the lower 3 bits H [2: 0] is "100", that is,
As shown in FIG. 7, when the horizontal counter value becomes "4", the load signal becomes "H", and when the horizontal counter value becomes "5", the output of the latch 13 described later is loaded. . That is, the load is performed before the display period signal DISO becomes "H" by the horizontal offset amount (scroll amount).

The table memory (first storage means) 10 is
A composite signal A [11: 0] of the output SH [5: 0] of the horizontal adder 6 and the output SV [8: 3] of the vertical adder 7 is input as an address, and the address (corresponding to the display screen position) is input. 8-bit data (00H to FFH) indicating the type of character stored in () is output. As shown in FIG. 2, the table memory 10 has a capacity of, for example, 64 words × 64 words, which corresponds to the background screen.

The latch timing generation section (first storage timing generation means) 11 generates a latch timing signal based on the lower 3 bits data H [2: 0] of the horizontal counter 1. Specifically, the lower 3 bits data H [2:
While the value of [0] becomes "111", the signal of "H" level is output. The latch timing signal is a signal that determines the timing at which the latch 13 stores the character data output from the image memory 12.

The image memory (second storage means) 12 stores character data for forming images of various characters. The 8-bit data (character specification) output from the table memory 10 and the vertical adder are stored. An 11-bit composite signal of the lower 3 bits SV [2: 0] (specifying what line of the character) of 9 is used as an address, and one line (8 bits) of the character data at that address is output. Therefore, as shown in FIG. 3, the image memory 12 has an address of 000 to 7FFH (11 bits).
, For example, a character having the figure "A" is
It is stored in the addresses 208H to 20FH.

The latch (third storage means) 13 stores one line of the character data output from the image memory 12. The latch 13 is the latch timing generation unit 11
The timing signal is input to the gate signal G terminal, and the data is held at the falling edge. Also,
While the input signal of the gate signal G terminal is "H" level, the input data is passed through to the output.

The shift register (fourth storage means) 14 is
One line of the character data output from the latch 13 is stored, and the character data is sequentially output for each dot according to a dot clock (dot display timing). The loading of the shift register 14 is started according to the load signal from the load timing generator 9.

The AND circuit 15 ANDs the display start signal (DISP) generated by the display timing generator 8 and the output of the shift register 14 to generate display data. That is, the output of the shift register 14 is output as display data only when the display start signal is at "H" level.

Next, the operation will be described with reference to FIGS. 6 and 7. FIG. 6 shows the case where the horizontal offset is “0”, and FIG. 7 shows the case where the horizontal offset is “3”.

When the horizontal offset is "0", the output of the carry generation section 5 is "0", so the output SH [5: 0] of the horizontal adder 6 is HO [8: 3] and H [8]. 8: 3]
Is the value obtained by adding. Therefore, the output H of the horizontal counter 1
When [8: 0] is "0" to "7", the output SH [5: 0] of the horizontal adder 6 is "0" and the output H of the horizontal counter 1 is H.
When [8: 0] is "8" to "F", the output SH [5: 0] of the horizontal adder 6 becomes "1".

Then, the latch timing generator 11
When the value of H [2: 0] is "111", a gate signal (latch signal) of "H" level is output, and the latch 13 receives this gate signal and outputs H [8: 0] of the horizontal counter 1.
Holds "7" or "F", the output of the image memory 12 is held. When the horizontal offset is "0", the lower 3 bits HO [2: 0] of the horizontal offset register are "000", and the load signal to the shift register 14 is also the output H [8: 0] of the horizontal counter 1. ] Becomes "H" when "7" or "F" is shown. Therefore, the latch 13
The held data of is immediately loaded to the shift register 14, and the shift register 14 is based on the dot clock.
Image data for each dot is output.

The display period signal DISP is the horizontal counter 1
Output H [8: 0] rises when it becomes "8", so that the characters A, B, C, and
Data of the first line of ... (A0 to A7, B0 to B7, C
0 to C7, ...) are sequentially output. The above characters A, B, C, ... Are shown in association with FIGS. 2 and 3.

On the other hand, when the horizontal offset is "3",
Lower 3 bits of horizontal offset register HO [2: 0]
Is "011". Since the output of the carry generator 5 is "1", the output SH [5:
0] is a value obtained by adding “1” to a value obtained by adding HO [8: 3] and H [8: 3]. Therefore, when the output H [8: 0] of the horizontal counter 1 is "0" to "7", the horizontal adder 6
Output SH [5: 0] of the horizontal counter 1 is "1", and when the output H [8: 0] of the horizontal counter 1 is "8" to "F", the output SH [5: 0] of the horizontal adder 6 is "2". It becomes like “ That is, when there is a horizontal offset, the character to be read is preceded by one character.

Then, the latch timing generator 11
Similar to the case where the horizontal offset is “0”, when the value of H [2: 0] is “111”, a latch signal of “H” level is output, and the latch 13 receives this latch signal and the horizontal counter 1 When the output H [8: 0] is "7" or "F", the output of the image memory 12 is held. However, in the case where there is a horizontal offset, this case is described as a horizontal offset “3”. However, since the lower 3 bits HO [2: 0] of the horizontal offset register 3 is “011”, the shift register 14 is loaded. As for the signal, the output H [8: 0] of the horizontal counter 1 is "4" or "C" (the lower 3 bits are "10").
0 "), it becomes" H "level.
The held data of 3 is loaded into the shift register 14 with a delay of 4 dot clocks.

Then, the shift register 14 outputs the image data of each dot based on the dot clock, and the display period signal DISP is the output H of the horizontal counter 1.
Since it rises when [8: 0] becomes “8”, of the data (A0 to A7) of the first line of the character A,
"A0, A1, A2" cannot pass through the AND circuit 15 and will not be output as display data. Therefore, as the display data output, the characters A, B,
Data of the first line of C, ... (A3 to A7, B0 to B
7, C0 to C7, ...) are sequentially output, and 3
This means that the horizontal offset for the dots has been made.

As described above, according to the configuration of this embodiment,
The latch 13 stores the character data from the image memory 12 at the timing of "H" of the gate signal, and the shift register 14 stores the character data from the latch 13 at the timing of "H" of the load signal of the load timing generation unit 9. Is changed by the offset amount of the horizontal offset register 3 indicating the scroll amount, the output data of the shift register 14 is displayed at the display start timing (DI) for a time corresponding to the offset amount.
SP), and at the display start timing, display is performed from the predetermined number of dots that form one line of the character that is positioned on the leftmost side of the display screen, and the display is performed in the horizontal direction in dot units. Scrolling can be realized. Since the data loading timing of the shift register 14 is controlled in this manner, it is possible to avoid a delay such as a configuration in which all the data of one line of a character is loaded and the output of the loaded data is selected as in the conventional case. You can

(Embodiment 2) Another embodiment of the present invention will be described below with reference to FIG. In addition, in order to avoid duplication of description, the same reference numerals are given to the functional portions having the same functions as those of the first embodiment, and the description thereof is omitted.

The image display device of the present embodiment is constructed so as to be able to perform a composite display of two screens, and in order to correspond to the image data of two screens, the first and second horizontal offset registers 3a, 3b ,. First and second vertical offset register 4
a, 4b, first and second latches 13a and 13b, and first and second shift registers 14a and 14b. Further, a selector 21 for switching which output of the first and second horizontal offset registers 3a and 3b is adopted, a selector 22 for switching which output of the first and second vertical offset registers 4a and 4b is adopted, And a screen synthesizing means 23 for synthesizing the outputs of the first and second shift registers 14a and 14b. Then, the load timing generator 9'generates the first and second load signals,
The load signal is output to the first shift register 14a and the second load signal is output to the first shift register 14b.
The latch timing generator 11 'also generates the first and second gate signals and outputs the first gate signal to the first latch 13a.
Then, the second gate signal is output to the second latch 13b.

With such a configuration, for example, H [2:
0] is “0 to 3”, the first image data is generated,
The second image data can be generated when H [2: 0] is “4 to 7”. That is, when generating image data for two screens in this manner, the first gate signal is set to "H" when H [2: 0] is "3", and when H [2: 0] is "7". By setting the second gate signal to “H”, the output data of the image memory 12 is held in the first latch 13a when the output data of the first screen is the data of the first screen, and the output data of the image memory 12 is set to the second data. The holding timing may be made different between the two so that the second latch 13a holds the data of the screen.

When generating the first image data, the first horizontal offset register 3a, the first vertical offset register 4a, the first latch 13a, and the first shift register 14a are adopted, and the first load signal is used. And the first gate signal is output, the timing at which the first shift register 14a stores the character data from the first latch 13a is the load timing generation unit 9
Is changed by the offset amount of the first horizontal offset register 3a, which indicates the scroll amount of the first screen, at the timing of "H" of the first load signal.

When generating the second image data, the second horizontal offset register 3b, the second vertical offset register 4b, the second latch 13b, and the second shift register 14b are adopted, and at the same time, the second shift register 14b is used. By outputting the load signal and the second gate signal, the timing at which the second shift register 14b stores the character data from the second latch 13b is set to "H" of the second load signal of the load timing generation unit 9. Is changed by the offset amount of the second horizontal offset register 3b indicating the scroll amount of the second screen.

Then, each shift register 14a, 14b
Output data is preceded by the display start timing (DISP) for a time corresponding to each offset amount, and both images are combined (addition of screens or priority of one screen) by the screen combining unit 23. In addition, the display is performed from the predetermined dot forming one line of the character located on the leftmost side of the screen of this composite image, and horizontal scrolling in dot units is realized in the two-screen composite image. You can

Cycle stealing can also be performed by using the same structure as that shown in FIG. That is, when H [2: 0] is “0 to 3” when the CPU and the display data generation unit of FIG. 7 alternately access the table memory for the reason of increasing the display rewriting speed. Is accessed by the CPU, and when H [2: 0] is “4 to 7”, the display data generation unit may access.

[0049]

As described above, according to the present invention, since the data loading timing of the fourth storage means is controlled, as in the conventional case, all the data of one line of the character is loaded and the loaded data Since it is possible to avoid a delay such as a configuration for selecting an output, a margin when connecting a color look-up table RAM or the like becomes large, and it is possible to easily cope with colorization and high definition of screen display. Further, since the multiplexer for selecting the output is not used, there is an effect that the circuit scale is less likely to increase as compared with the related art.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a configuration example of a display screen.

FIG. 2 is an explanatory diagram showing a relationship between a display screen and a background screen.

FIG. 3 is a memory map diagram of an image memory.

FIG. 4 is an explanatory diagram of an offset register.

FIG. 5 is a block diagram showing a configuration of a display data generation unit of the image display device according to the first embodiment of the present invention.

FIG. 6 is a timing chart illustrating the operation of FIG. 1 when the horizontal offset is “0”.

FIG. 7 is a timing chart illustrating the operation of FIG. 1 when the horizontal offset is “3”.

FIG. 8 is a block diagram showing a configuration of a display data generation unit of the image display device according to the second embodiment of the present invention.

[Explanation of symbols]

1 horizontal counter 2 vertical counter 3 horizontal offset register (fifth storage means) 4 vertical offset register (fifth storage means) 5 carry generator 6 horizontal adder 7 vertical adder 8 display timing generator 9 load timing generator (Second storage timing generation unit) 10 Table memory (first storage unit) 11 Latch timing generation unit (first storage timing generation unit) 12 Image memory (second storage unit) 13 Latch (third storage) Means) 14 shift register (fourth storage means) 15 AND circuit

Claims (7)

[Claims] 1. An image display device for displaying a plurality of characters composed of a predetermined number of dots on a display screen, the first storage means storing a display array of characters, and forming an image of the character. Second storage means for storing the character data to be stored and for outputting the character data according to the data of the first storage means, and a third storage means for storing the character data output from the second storage means. A fourth storage means for storing the character data output from the third storage means and sequentially outputting the character data according to the dot display timing, and at least a horizontal offset of the display array of the first storage means. Fifth storage means for holding the data indicating the amount, a counter for counting at least the horizontal position of the display dots on the display screen, The address generation means for generating an address for the first storage means based on the offset amount indicated by the storage means data and the counter value of the counter, and the character data output from the second storage means for the third storage means. The storage timing of the first storage timing generation means for generating the storage timing of the second storage means based on the counter value of the counter, and the storage timing of the character data output from the third storage means by the fourth storage means. A second storage timing generation means for generating the counter value of the counter and the offset amount, and means for displaying a character on the display screen based on the character data sequentially output from the fourth storage means. An image display device characterized by being provided. 2. The first storage means has a storage capacity corresponding to or greater than the number of characters displayed on the display screen, and is writable. The image display device according to claim 1, wherein: 3. The second storage means has a storage capacity for holding display data for each type of the character, and is configured to be read-only or writable. Alternatively, the image display device according to claim 2. 4. The third storage means comprises at least one register having the same bit amount as the bit amount of the character data output from the second storage means. The image display device according to any one of claims 1 to 3. 5. The fourth storage means loads the data of the third storage means with a timing signal from the second storage timing generation means, and loads the loaded data in the non-input state of the timing signal. 5. The image display device according to claim 1, wherein the image display device is configured by a shift register that shifts the pixel based on a dot display timing. 6. The fifth storage means stores the number of dots forming the character and the number of horizontal dots and vertical lines in a display space formed by the display arrangement of each character shown by the first storage means. 6. The image display device according to claim 1, wherein the image display device is configured by a register having a bit amount corresponding to. 7. The third storage means, the fourth storage means,
Further, two or more sets of fifth and fifth storage means are provided for a plurality of images, respectively, and the first storage timing generation means outputs the first storage timing to each of the third storage means, and the second storage timing. The image display device according to any one of claims 1 to 6, wherein the timing generation means is configured to output the second storage timing to each of the fourth storage means.