JPH098794A - Synchronizing signal detection circuit and detecting method for the same - Google Patents

Abstract

PURPOSE: To prevent the leading part of an acoustic signal from being lost by improving probability for a synchronizing pattern, which is first detected, to be a true synchronizing signal in the synchronizing detection of MPEG audio bit stream. CONSTITUTION: A bit rate 2 measured by a bit rate measuring circuit 1 is transformed to the code of the same format as a bit rate index by an encoder 3, bit stream data 50 are inputted to a shift register 103, and a synchronizing pattern and a header are extracted. Then, a bit rate index in the header is compared with a code based on the measured bit rate and by ANDing this compared result and a synchronizing pattern detect signal 105, a synchronizing pattern detect signal 7 having much higher certainty is provided. When a frequency incoming confirming circuit 107 confirms that the synchronizing pattern detect signal 7 is cyclically incoming, a synchronism establish signal 108 is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for detecting a synchronizing signal from a bit stream and a method for detecting the same, and more particularly to, for example, ISO / IEC 11172-3 (hereinafter referred to as "M").
The present invention relates to a sync signal detection circuit suitably applied to an apparatus for detecting a sync signal from a bit stream of a compressed acoustic signal according to a method defined by the "PEG audio standard") and a detection method thereof.

[0002]

2. Description of the Related Art ISO / I is used as a compression technique for acoustic signals.
MPEG (Movi) installed in EC SC29 / WG11
ng Picture Experts Group), there is a system commonly called MPEG audio (standard number is “ISO / IEC 11172-3”) standardized in parallel with the coding of moving images. This is the acoustic signal (Psychacoustic)
s) The number of quantization bits is optimized based on the characteristics to realize highly efficient compression.

A compressed audio signal of MPEG audio is transmitted in the form of a bit stream in which a bit string obtained by encoding information such as a bit rate and a synchronization signal are added to a code string obtained by compression encoding the audio signal.

In a bitstream sync signal in MPEG audio, a sync pattern consisting of 12 consecutive "1" s is arranged at the beginning of the bitstream.

However, the MPEG audio standard permits 12 bits or more of "1" to continue in places other than the synchronization signal. Such a pattern refers to a compressed acoustic signal (audio data) or ancillary data (external data; the remaining portion when the audio data does not reach the end of AAU described later), and any data other than MPEG audio. Can be inserted everywhere) in the bitstream (ie, any bit pattern can appear in parts other than the header).

Therefore, in MPEG audio, synchronization cannot be established only by detecting the synchronization pattern, and it is necessary to establish synchronization after recognizing that the synchronization pattern periodically arrives. Has been done.

FIG. 3 shows the structure of a bit stream (1 frame) of MPEG audio and a header. In addition,
One frame of an MPEG audio bit stream is called an AAU (Audio Access Unit) and is a reference unit that can be decoded independently.

Referring to FIG. 3, the header has a total of 32 bits, of which the leading 12 bits are a synchronization pattern (also referred to as a "synchronization word"), and thereafter various information (ID) indicating the identity of the bit stream. , Layer specification, protection bit that specifies the presence / absence of error check,
Bit rate index, sampling frequency, stereo / monaural, copyright display, etc.) are included.

1 of MPEG audio bitstream
The number of bits in a frame is determined by three values, that is, bit rate, sampling frequency, and padding, and these values are included in the header.

For example, the bit rate is 192 kbps
(The “bit rate index” arranged in the 17th to 20th bit fields of the header is “1010”), and the sampling frequency is 48 kHz (the 21st and 22nd bit bit fields of the header are “0”).
1 "), the number of bits in one frame is defined as 4608 bits.

In order to confirm that the synchronization pattern periodically arrives, 1 is obtained by referring to the table from the information of the header.
It suffices to obtain the number of bits per frame and confirm that the synchronization pattern is detected for each number of bits.

FIG. 4 is a block diagram showing the structure of such a conventional synchronization detecting circuit.

Referring to FIG. 4, bit stream data 50 and a bit stream clock 51, which is a transfer clock, are supplied as a bit stream.

The shift register 103 is configured as a 32-bit shift register that takes in bit stream data in synchronization with the rising edge of the bit stream clock and shifts the data, and is a 12-bit shift register 103-for detecting a synchronization pattern. a and
It consists of a 20-bit shift register 103-b for detecting the remaining 20 bits of the header.

The logical product (AND) circuit 104 outputs "1" as the synchronous pattern detection signal line 105 when the data held in the shift register 103-a is "1" for all the bits.

The periodic incoming confirmation circuit 107 is a circuit for confirming that the synchronization pattern detection signal 105 periodically comes in. The periodic arrival confirmation circuit 107 outputs the synchronization establishment signal 108 when it confirms that the synchronization pattern comes in periodically.

The audio signal processing circuit 109 is synchronized by the synchronization establishment signal 108, and the bit stream data 50
The compressed acoustic signal of 1 is expanded and the acoustic signal 110 is output.

FIG. 5 shows the configuration of the cycle incoming confirmation circuit 107 of FIG.

Referring to FIG. 5, the periodic incoming confirmation circuit 107
Is cleared by the sync pattern detection signal 105,
A counter circuit 201 that counts the bitstream clock 51 and a header value held in a latch circuit 202 (first header value stored in the shift register 103-b).
The content of 3 to 32nd bits) is compared with the number of bits of one frame obtained by decoding with the decoder 203 by the comparator 204, and if they match, a match pulse 205 is output, and the match pulse 205 is further output. If the sync pattern detection signal 105 comes in again at the same time, the AND gate 5-
The synchronization establishment signal 108 is output from b.

The RS flip-flop 206 transmits the incoming sync pattern detection signal 105 to the counter circuit 201 until the first coincidence pulse 205 is generated after the sync pattern detection signal 105 is input. It is for prohibition. The RS flip-flop 206 is reset at the falling edge of the sync pattern detection signal 105 from "1" (high level) to "0" (low level), the output Q becomes "0", and the output Q and the sync pattern are detected. The AND gate 5-a that receives the signal 105 is "0"
, And the coincidence pulse 205 output from the comparator 204 is set to RS flip-flop 206 at the rising edge from "0" (low level) to "1" (high level), and the output Q is "1". Then, the AND gate 5-a conducts the synchronization pattern detection signal 105 and transmits it to the clear terminal of the counter circuit 201 and the input terminal of the AND gate 5-b.

FIG. 6 shows a timing waveform of each signal terminal of the cycle incoming confirmation circuit shown in FIG.

When the sync pattern is not a true sync signal (for example, when "1" is continuously detected in 12 bits in the ancillary data), the shift register 103-b for storing the 13th to 32nd bits of the header. The value of the latch circuit 202 that holds the output data of the counter becomes a meaningless value (data of a predetermined bit field of the header is not held), and after a time different from the frame length, the counter circuit 201 and the latch circuit 202. A match pulse 205 is generated from the comparator 204 in accordance with the value decoded by the decoder 203. At this time, since the synchronization pattern is not detected, the synchronization is not established.

When the sync pattern is a true sync signal, a coincidence pulse 205 is generated at a time equal to the frame length after the sync pattern detection signal 105, and the next sync pattern detection signal 105 is input at the same time. The synchronization establishment signal 108 is generated.

[0024]

In such a conventional synchronization detecting circuit, the control sequence until the synchronization is established is as follows.

(1) A 12-bit continuous "1" (synchronization pattern) is detected from the bit stream.

(2) The 32 bits starting from the synchronization pattern detected in the above sequence (1) are interpreted as a header, and the number of bits in one frame is obtained.

(3) After the first synchronization pattern, if the synchronization pattern is present again by the number of bits obtained in the above sequence (2), it is considered that the synchronization has been established. Start over from sequence (1).

Until synchronization is established, the acoustic signal is expanded (ex
pansion) processing is not performed and the data is skipped. That is, in the sequence (3), one frame of data is always skipped.

Therefore, the sync pattern detected the first time is not the true sync signal, but the above sequence (1) again.
If you start over, more data will be skipped.

Moreover, the "one frame" skipped in the sequence (3) is a numerical value obtained based on the data which is not the true header (the bit rate stored in a predetermined bit field of the header). And the frame length is obtained from the information that is not the sampling frequency), it is a value different from the true frame length.

If this value is longer than the true frame length,
More than one frame of data will be skipped. As a result, it takes a long time until the synchronization is established, and the audio signal at the beginning of the bit stream is lost due to skipped data.

FIG. 7 is a diagram schematically showing how a bitstream is skipped.

Referring to FIG. 7, 5 of A, B, C, D and E
There is a sync pattern at a point, and the point A among them is not a true sync signal (false sync signal).

When a sync pattern (12 consecutive bits are all "1") is detected at point A, the subsequent 20 bits are interpreted as a header, and a value different from the true frame length is obtained.

That is, referring to FIG. 7, the value obtained as the frame length at point A is longer than the true frame length,
In this case, it is at point F that the next synchronization pattern is confirmed.

Then, the bit stream up to the point F is skipped and there is no synchronization pattern at the point F, so
Here, it returns to the state of waiting for the synchronization pattern.

After that, a sync pattern is detected at point D. Since this is a true sync signal, a normal header can be obtained, and E
Synchronization is established by skipping the data up to the point and detecting the synchronization pattern again at point E.

As described above, when the synchronization pattern at the point A is not a true synchronization pattern, much data is skipped.

If the first synchronization pattern to be detected is always the synchronization signal, the above problem does not occur.

However, as described above, MPEG
According to the audio standard, in addition to the sync signal, sync patterns exist everywhere in the bitstream, so a large amount of data may be skipped depending on the sync pattern that arrives before synchronization is established. There is always the problem of losing the beginning.

Therefore, the present invention solves the above problems,
In a sync detection of an MPEG audio bitstream, a sync signal detection circuit and a detection method for increasing the probability that a sync pattern to be detected first is a true sync signal and preventing loss of the beginning portion of an audio signal are provided. To aim.

[0042]

In order to achieve the above object, the present invention provides a sync signal and a numerical value (hereinafter referred to as "bit rate") indicating the number of bits transmitted per unit time (hereinafter referred to as "bit rate index"). )) And acoustic information in a predetermined bit sequence, respectively, and arranged so that the bit rate index exists after a predetermined bit of the synchronization signal (hereinafter referred to as “bitstream”). A sync signal detection circuit for detecting the sync signal and outputting a sync signal detection signal, the sync pattern detection circuit detecting a sync pattern having a bit arrangement in the same format as the sync signal existing in the bit stream; The same number as the number of bits of the bit rate index starting from the position after the predetermined bit of the synchronization pattern A bit rate index extraction circuit that extracts bits, a bit rate measurement circuit that measures the number of bits that the bit stream enters per unit time, and outputs a measured bit rate, and the bit rate measurement circuit that outputs the bit rate. An encoder that inputs a measured bit rate and outputs the bit rate index corresponding to the bit rate, a comparator that compares the output of the bit rate index extraction circuit and the output of the encoder, and A logic circuit that outputs a combinational logic of the detection result of the synchronization pattern detection circuit and the comparison result of the comparator, and the detection result of the synchronization pattern detection circuit and the comparison result of the comparator are both true. In this case, the synchronization signal detection circuit outputs the synchronization signal detection signal.

In the present invention, preferably, the synchronization pattern detection circuit responds to the incoming of the bit stream and sequentially stores each bit of the bit stream, a stored value of the shift register and the shift register circuit. A determination circuit that determines whether or not the synchronization pattern matches.

Also, in the present invention, it is preferable that the bit rate measuring circuit is excited by the timer circuit for generating an excitation signal of a predetermined unit time width, and the bit stream is received by the excitation circuit. And a counter for counting events.

In the present invention, the synchronization signal and the number of bits transmitted per unit time (referred to as "bit rate")
Numerical value (referred to as "bit rate index")
And audio information are represented by a predetermined number of bits respectively, and are arranged so that the bit rate index is present after a predetermined number of bits of the synchronization signal. In the method of detecting a signal and detecting a sync signal, the number of bits that the bit stream enters per unit time is measured, an index code corresponding to the measured bit rate is derived, and the derived index code And a bit rate index extracted from the incoming bit stream are compared, and when both match and the sync signal in the bit stream matches a predetermined sync pattern, a sync signal detection signal is output. There is provided a method for detecting a synchronization signal.

The present invention is preferably characterized by monitoring the periodic arrival of the synchronization detection signal to detect the establishment of synchronization.

[0047]

According to the present invention, the bit rate is measured by the bit rate measuring circuit and the expected value of the bit rate index is created, so that the bit rate index is expected from the temporary header starting from the detected synchronization pattern. Only those that match the value are set as candidates for the true synchronization signal, and the probability that the synchronization pattern detected first is the true synchronization signal is increased.

[0048]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 1, elements having the same functions as the elements shown in FIG. 4 are designated by the same reference numerals.
The differences from the conventional example shown in FIG. 4 will be described below,
The description of the same parts is omitted.

Referring to FIG. 1, bit rate measuring circuit 1
Measures the frequency of the bitstream clock 51,
The measured bit rate 2 is output.

In this embodiment, the bit rate measuring circuit 1 is composed of a general timer / counter circuit for measuring the frequency. FIG. 2 shows an example of the circuit configuration of the bit rate measuring circuit 1 in this embodiment.

Referring to FIG. 2, bit rate measuring circuit 1
Is a timer circuit 501 that generates a clock signal 504 of 1 [kHz], a counter circuit 502, and a latch circuit 50.
Counter circuit 5 according to the clock signal 504.
The value of 02 is latched in the latch circuit 503 and the counter circuit 502 is cleared (for example, the rising edge of the clock signal 504 is used as the latch timing of the latch circuit 503 to clear the counter circuit 502 at the falling edge of the clock signal 504. ).

In this case, the bit rate is 192 [kbp
[s], the frequency of the bit stream clock 51 is 192 [kHz], and therefore "192" is output as the measured bit rate 2.

Referring to FIG. 1, the encoder 3 is a circuit for encoding the input measured bit rate 2 and outputting it. Encoding rules are defined in the MPEG audio standard. Table 1 shows the encoding rule (for MPEG audio, layer 2).

The comparator 5 includes the bit rate index extraction value 4 from the shift register 103-b and the encoder 3
The output is compared with the output of 1 and the bit rate match signal 6 is output when they match. In the present embodiment, the comparator 5 uses 4 bits from the 4th bit to the 7th bit of the shift register 103-b as the bit rate index extraction value 4.
Is being entered.

If the sync pattern is a true sync signal, the 4 bits extracted from the shift register 103-b and supplied to the comparator 5 are the bit fields from the 17th bit to the 20th bit of the header, and the bit rate. The index will be extracted.

[0057]

[Table 1]

The other structure of the present embodiment shown in FIG. 1 is basically the same as that of the conventional example shown in FIG. In the following, further differences from the conventional example will be described.

In the above-mentioned conventional example, the synchronization pattern detection signal 105 is input to the cycle arrival confirmation circuit 107 as it is, but in the present embodiment, the synchronization pattern detection signal 105 is input.
And the bit rate match signal 6 are both "1",
The synchronization pattern detection signal 7 is generated, and the cycle incoming confirmation circuit 1
07. That is, referring to FIG. 1, the input terminal of the cycle arrival confirmation circuit 107 is connected to the synchronization pattern detection signal 10
5 and the bit rate coincidence signal 6 are connected to the output terminal of an AND gate 9.

Next, the operation of this embodiment will be described. Here, the bit rate of the input bit stream is 192 [k
bps].

The bit rate measuring circuit 1 measures the frequency of the bit stream clock and outputs "192" as the measured bit rate. The encoder 3 inputs the bit rate measuring circuit 1 and encodes it into "1010" based on Table 1 above.

Here, when the synchronization pattern is input to the shift register 103-a, an AND gate (logical value circuit)
The synchronization pattern detection signal 105 output from 104 becomes active (becomes "1").

If this synchronization pattern is a true synchronization signal, synchronization is established in the same manner as in the conventional example.

That is, from the 17th bit of the header to the 2nd
The bit rate index is stored in bit 0, and the bit rate index extraction value 4 becomes the correct bit rate index value “1010”.

Therefore, the bit rate coincidence signal 6 becomes "1", and the synchronization pattern detection signal 7 output from the AND gate 9 becomes active (becomes "1").

Since the true sync pattern exists again after this one frame, the sync pattern detection signal 105 is output. At this time as well, the bit rate index value is normal, so that the bit rate coincidence signal 6 is "1" at the same time.
From AND gate 9 to sync pattern detection signal 7
(= “1”) is output.

Since it has been confirmed that the synchronization pattern detection signal 7 periodically arrives, the periodic arrival confirmation circuit 1
The synchronization establishment signal 108 is output from 07.

Next, the case where the sync pattern is not a true sync signal will be described.

Since the sync pattern is not a true sync signal, there is no bit rate index at the positions from the 4th bit to the 7th bit of the shift register 103-b.

Therefore, in many cases, the bit rate extraction value becomes a value different from the correct bit rate index value "1010", and the bit rate coincidence signal 6 does not occur (remains "0"). Therefore, the synchronization pattern detection signal 7 is not output. That is, the state of waiting for the synchronization pattern continues.

Referring again to the example shown in FIG. 7 referred to in the description of the data discarding in the conventional example, the present embodiment will be described. The synchronization pattern at point A (not a true synchronization signal)
Then, since the bit rate coincidence signal 6 does not become "1", the synchronization pattern detection signal 7 is not output and the state of waiting for the synchronization pattern continues, and the synchronization pattern at point B (true synchronization pattern) is not skipped. Can be detected. Therefore, the periodic arrival confirmation circuit 107 confirms that the synchronization pattern periodically arrives at the point C, and the synchronization is established.

As described above, according to this embodiment, it is possible to prevent a large amount of data at the beginning of the bit stream from being skipped.

When the sync pattern is not a true sync signal and the bit rate extraction value 4 happens to be "1010", the bit rate coincidence signal 6 becomes "1" and the sync pattern detection signal 7 is generated. However, synchronization is not established unless there is a synchronization pattern and a normal bit rate index again after one frame. Such an operation is similar to that of the conventional example, and one frame of data is skipped.

However, the probability that the bit rate extraction value 4 happens to be "1010" by chance is as small as 1/2 ⁴ = 1/16 because all 4 bits must match.

That is, the probability that a large amount of data will be discarded due to the synchronization pattern that is not the synchronization signal is reduced to 1/16 of that in the conventional example. Therefore, the loss of the beginning of the acoustic signal is greatly reduced.

Although the present invention has been described with reference to the above embodiments, the present invention is not limited to the above embodiments,
It goes without saying that various embodiments according to the principles of the present invention are included. For example, in the above embodiment, ISO / IEC 11
172-3 (MPEG1 audio) has been described as an example, but it is described as a preferred embodiment of the present invention, and the present invention is not limited to this standard.

[0077]

As described above, in the sync signal detection circuit according to the present invention, in addition to the detection of the sync pattern, the comparison of whether or not the bit rate index is normal is made based on the actually measured bit rate. The probability that one frame of data will be skipped due to a synchronization pattern that is not a true synchronization signal is greatly reduced compared to the conventional example.
Therefore, according to the present invention, there is an effect that the loss of the beginning portion of the acoustic signal is significantly suppressed and reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a bit rate measuring circuit according to an embodiment of the present invention.

FIG. 3 is a diagram schematically showing the structure of an MPEG audio bitstream.

FIG. 4 is a block diagram showing a configuration of a conventional example.

FIG. 5 is a diagram showing an example of a configuration of a cycle incoming confirmation circuit 107 in a conventional example.

FIG. 6 is a timing diagram for explaining the operation of the periodical incoming confirmation circuit 107 in the conventional example.

FIG. 7 is a diagram for explaining that data is discarded depending on the position of a periodic pattern in a conventional example.

[Explanation of symbols]

 1 bit rate measurement circuit 2 measured bit rate 3 encoder 4 bit rate index extraction signal 5 comparator 6 bit rate coincidence signal 7 sync pattern detection signal 50 bit stream 51 bit stream clock 103, 103-a, 103-b shift register 104 logical product (AND) circuit 105 synchronous pattern detection signal 107 periodic incoming probability signal 108 synchronization establishment signal 109 acoustic signal processing circuit 110 acoustic signal 201 counter circuit 202 latch circuit 203 decoder 204 comparator 205 coincidence pulse 206 RS flip-flop 501 timer Circuit 502 Counter circuit 503 Latch circuit 504 Clock signal

Claims (5)

[Claims] 1. A synchronization signal, a numerical value (hereinafter, referred to as "bit rate") indicating the number of bits transmitted per unit time (hereinafter, referred to as "bit rate"), and acoustic information are arranged in predetermined bits and respectively. , A synchronization for detecting the synchronization signal and outputting the synchronization signal detection signal from a series of bit strings (hereinafter referred to as “bitstream”) arranged such that the bit rate index exists after a predetermined bit of the synchronization signal. In the signal detection circuit, a sync pattern detection circuit for detecting a sync pattern which is a bit sequence of the same format as the sync signal existing in the bit stream; and the bit rate index starting from a position after the predetermined bit of the sync pattern. Bit rate index extraction times to extract the same number of bits as And a bit rate measuring circuit that measures the number of bits that the bit stream comes in per unit time and outputs a measured bit rate, and inputs the measured bit rate output from the bit rate measuring circuit and inputs the bit An encoder that outputs the bit rate index corresponding to a rate, a comparator that compares the output of the bit rate index extraction circuit and the output of the encoder, a detection result of the synchronization pattern detection circuit, and the A logic circuit that outputs a combinational logic with a comparison result of a comparator; A synchronization signal detection circuit, which outputs a signal. 2. A shift register circuit, wherein the sync pattern detection circuit responds to the incoming of the bit stream and sequentially stores each bit of the bit stream, and a value stored in the shift register and the sync pattern are unified. The synchronization signal detection circuit according to claim 1, further comprising: a determination circuit that determines whether or not the synchronization signal is detected. 3. A bit rate measuring circuit, a timer circuit for generating an excitation signal of a predetermined unit time width, a counter which is excited by the excitation signal and counts an incoming event of the bit stream, The sync signal detection circuit according to claim 1, further comprising: 4. A synchronization signal, a numerical value (referred to as “bit rate index”) indicating the number of bits transmitted per unit time (referred to as “bit rate”), and audio information are represented as predetermined bits, respectively. A method of detecting the synchronization signal and detecting the synchronization signal detection signal from a series of bit strings (hereinafter referred to as “bitstream”) arranged such that the bit rate index exists after a predetermined bit of the synchronization signal, Measure the number of incoming bits of the bitstream per time, derive the index code corresponding to the measured bitrate, the derived index code and the bitrate index extracted from the incoming bitstream And are compared, and both match, and the synchronization signal in the bit stream Detection method of synchronizing signal and outputting a synchronization signal detection signal if they match the predetermined synchronization pattern. 5. The detection method according to claim 4, wherein the establishment of synchronization is detected by monitoring the periodic arrival of the synchronization detection signal.