JPH0795192A - Synchronizing signal detector of digital audio device - Google Patents

Abstract

PURPOSE: To provide a synchronizing signal detector for preventing malfunctions by detecting only synchronizing signals in data transmitted from the outside by an audio data form and outputting frame pulse signals. CONSTITUTION: Synchronizing signals in inputted audio data are detected and frame pulses for reporting the start of the audio data are generated from a system decoder. At the time of detecting the synchronizing signals, an internal synchronization counter 100 is provided, the erroneous detection of signals by the data similar to the synchronizing signals present over the entire area of the audio data is prevented and the frame pulses of a fixed synchronization period are outputted even when the synchronizing signal detection error of the frame of a prescribed part is present. Thus, the effect of improving the reliability and performance of a high definition television and a digital audio equipment is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a high definition television,
The present invention relates to a sync signal detecting device in a digital audio device such as a compact disc player or a digital video cassette recorder, and in particular, by detecting only the sync signal in the data transmitted from the outside in the audio data format and outputting a frame pulse signal. The present invention relates to a synchronization signal detection device that prevents malfunction.

[0002]

2. Description of the Related Art FIG. 1 shows a coded audio data format for one frame. Explaining the audio data format of FIG. 1, the size of one channel has 3072 bits, 3344 bits, and 4608 bits depending on the sampling frequency. One channel of audio data has header data (10),
Error check data (20), bit allocation information (3
0), scale factor information (40), scale factor (50), subband sample (60), and additional information (70).

The header data (10) has a size of 32 bits and contains a synchronizing signal and information necessary for a digital audio device. Error check data (2
0) has a size of 16 bits and includes header data (1
0), bit allocation information (30), scale factor (5
It has a function to check the error that occurs from 0). The bit allocation information (30) is 88 bits or 92 bits.
This is the size of a bit, and is represented by allocating data compression information according to the sampling frequency, the number of channels, and the data transmission rate transmitted to the digital audio device. The scale factor information (40) divides all audio subbands that can be represented when the audio data is displayed in the frequency domain into 32 equal parts, and the largest of the 12 samples in each subband is called the scale factor. , When dividing 12 samples with this scale factor and amplifying the absolute value to a fixed amount and normalizing,
Coding is performed to reduce the information for these scale factors, and the information is represented by 2 bits. All scale factors (50) are transmitted in 6 to 16 bits. Subband samples (60) represent a quantized version of the sample with bits allocated among all 16 bits according to the principle of bit allocation. The additional information (70) includes various information, that is, a frame number, information characters, etc., in addition to the encoded audio data. Table 1 shows each bit data information of the header data (10).

[0004]

[Table 1]

[0005]

SUMMARY OF THE INVENTION The problem to be solved by the present invention is to decode encoded audio data by detecting a sync signal in the audio data frame and generating a frame pulse. It is an object of the present invention to provide a synchronization signal detecting device that can perform the signal processing.

[0006]

In order to solve the above problems, a sync signal detecting apparatus of the present invention includes a sync signal detecting section (80) for detecting a 12-bit sync signal pattern of input audio data, and an input. Number of data channels,
The count value is determined by using the sampling frequency and the data transmission rate as information, and the synchronous count data value is loaded (Loa
The data loading unit (90) for d) and the synchronization counting unit (10) for counting the clock for one frame from the data loaded by the output of the data loading unit (90).
0), and the outputs of the synchronization signal detection unit (80) and the synchronization count unit (100) are compared, and a logical operation unit (110) that performs a logical product operation is counted by the output of the logical operation unit (110). Output enable signal (enabling signal) each time a predetermined count is completed after
frame counting unit (120) for generating
And a delay unit (130) for delaying the output of the synchronization counting unit (100) by a predetermined time, and an output of the logical operation unit (110) in synchronization with the output signal of the delay unit (130). A sync signal discriminating section (140) for discriminating the sync signal, a control section (150) for controlling the entire system by the sync detection signal discriminated by the sync signal discriminating section (140), and a normal detection of the sync signal. A display unit (160) for displaying availability by using a light emitting element,
Composed of.

As described above, according to the present invention, a frame pulse signal is detected in one of the various data formats by detecting the sync signal pattern in the externally transmitted digital audio data. To detect and correct an error that occurs when the sync signal is detected so that it does not affect the whole system.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings. FIG. 2 is a block diagram of a sync signal detecting apparatus according to the present invention. The operation of FIG. 2 will be described with reference to FIGS.
I will explain it in connection with. In FIG. 4, (A) is an input audio data signal, (B) is a data transmission clock signal, and (C) is a sync signal detection unit (80).
Output signal (SYNC_EQ), (D) is an output signal (CNT_F) of the synchronization counting unit (100),
(E) is an output signal (SYN) of the synchronization signal determination unit (140)
C_OK), (F) is the output signal (FP_CK) of the delay unit (130), (G) is the output signal (LD1) of the control unit (150), and (H) is the logical operation unit (11).
0) Output signal (LD2) of the first arithmetic unit (110A)
Where (I) is the output signal (FP) of the second arithmetic unit (110B) of the logical operation unit (110), and (J) is the audio data output signal (DATA_OUT) obtained by delaying the input audio data by 11 bits. ).

When the audio data signal of FIG. 4 (A) is input to the sync signal detecting section (80), the sync signal detecting section (80) causes the sync signal pattern ('1111 1111 1111') of the head portion of the data signal. ) Is detected and FIG.
Of the synchronization detection signal (SYN) whose logical value of (C) is “0”
C_EQ) is output.

The count value of the data load unit (90) is determined by the number of channels of input data, the sampling frequency, and the data transmission rate information, and the output signal (LD1) of the control unit (150) as shown in FIG. ), The determined count value (LDDT) is input to the synchronization count unit (100).

The synchronous count unit (100) counts the count value (LDDT) loaded in the data load unit (90) by the output signal (LD1) of the control unit (150), and the count value is "FFFF". At time (D) of FIG.
A count completion signal (CN
T_F) is output.

The first arithmetic unit (1) of the logical operation unit (110)
10A) performs a logical product operation of the sync detection signal (SYNC_EQ) of the sync signal detection unit (80) and the count completion signal (CNT_F) of the sync count unit (100), and the calculated logical value is "1". In that case, the sync signal is normally detected and the value is output to the sync signal discriminating unit (140). When the logical value is "0", the value is output to the frame counting unit (120). Logical operation unit (110)
The second computing unit (110B) of the first computing unit (110B)
4A and the sync detection completion signal (SYN) of FIG. 4E output from the sync signal discriminating unit (140).
C_OK) is compared, the logical product is calculated, and a frame pulse (FP) signal as shown in FIG. 4 (I) is output.

In the frame counting section (120), the logical value of the value (LD2) output from the first arithmetic unit (110A) is "0", and the signal output from the synchronization signal determining section (140) is calculated. When the logical value is "1", the counting is started, and when the counting of the predetermined number of times is completed, the output signal (RQ
A logical value "0" is output to ST) to operate the control unit (150).

The delay unit (130) includes a synchronization counting unit (1
00), the count completion signal (CNT_F) of FIG. 4D is delayed for each operation circuit for a predetermined time to output a delay signal (FP_CK) of FIG. 4F,
The delayed signal (FP_CK) is sent to the frame counting unit (12
It is used for the clock of 0) and the system lock of the synchronizing signal discriminating unit (140).

The sync signal discriminating unit (140) delays the signal output from the first arithmetic unit (110A) from the delay unit (130).
The synchronization detection completion signal (SYNC_OK) of FIG. 4E is output in synchronization with the delay signal (FP_CK) output from the. The synchronization detection completion signal (SYNC_OK) clears the reset circuit in the control unit (150) so that the entire system operates normally.

The control unit (150) is provided with a synchronization signal discriminating unit (1
40) outputs the signal (SYNC_OK) to normally operate the entire system and synchronizes with the delay signal (FP_CK) of the delay unit (130) to determine the synchronization signal determination unit (14).
0) output signal (SYNC_OK) is output as the load signal (LD1) of FIG.
0) is enabled. In addition, after inputting the output signal (RQST) of the frame count unit (120) to prohibit the operation of the synchronization count unit (100) and inputting the load data (LDDT) from the data load unit (90), the synchronization is performed again. The counting unit (100) is operated.

The display unit (160) detects the frame pulse period using the output frame pulse (FP) and the delayed signal (FP_CK), and when the frame pulse is normally output, the light emitting element "LED". Is turned on to display that the sync signal is normally detected, and when the sync signal is not detected normally, the light emitting element "LE
"D" is turned off to notify that this device is not operating normally.

FIG. 3 is a detailed configuration diagram of the data load unit (90) and the synchronization count unit (100) of FIG. The data load unit (90) selects a load data storage unit (90A) that stores a fixed count load value, and one of a plurality of load values according to the number of channels, the sampling frequency, and the data transfer rate. And a first selector (90C) that selects one of a plurality of inputs according to the control signal output from the control unit (90B). .

The synchronization counting section (100) synchronizes the load data selected by the first selector (90C) with a clock signal to start counting, and a first synchronization counter (100A) and a second synchronization counter. (100
B), a second selector (100C) that selects the output of the second synchronization counter (100B) by the control signal of the control unit (90B), and the output of the second selector (100C) as the clock signal. Synchronize and count complete signal (CNT_
F) and a count completion signal generator (100D).

Next, the operation of FIG. 3 will be described. The count load value stored in the load data storage unit (90A) is controlled by the control unit (90B) by the first selector (90C).
At this time, the load data values and the like input to the control unit (90B) at this time are as shown in Table 2, and the output data (SK1, SK2) by the input data are as shown in Table 3. .

[0021]

[Table 2]

[0022]

[Table 3]

When the control unit (90B) outputs control signals (SK1, SK2) for controlling one of a plurality of load data values according to the number of channels, sampling frequency, and data transmission rate, the first signal is output. Selector (90
C) selects one of a plurality of inputs according to the control signal output by analyzing the input data from the control unit 90B.

The load data selected and output from the first selector (90C) is stored in the first synchronization counter (10C).
0A) and the second synchronization counter (100B), synchronized with the clock “CK” to start counting, and when the counting is completed, the second selector (100
C) selected by the count completion signal generator (100
A count completion signal (CNT_F) as shown in FIG. 4D is output through D).

[0025]

As described above in detail, according to the present invention, a sync signal is detected in transmitted digital audio data to output a frame pulse, and when a sync signal is detected, the audio data is transmitted through an internal sync counter. It is possible to prevent erroneous detection due to data similar to the sync signal that exists over the entire area, and even if a sync signal detection error for a predetermined number of frames occurs, output a frame pulse of a predetermined sync period to ensure system reliability. There is an effect that the property and the performance can be improved.

[Brief description of drawings]

FIG. 1 is an encoded audio data format for one frame.

FIG. 2 is a block diagram of a synchronization signal detecting device according to the present invention.

FIG. 3 is a detailed configuration diagram of a data load unit and a synchronization count unit in FIG.

FIG. 4 is an operation timing chart according to FIG.

[Explanation of symbols]

 80 sync signal detection unit 90 data load unit 100 sync count unit 110 logical operation unit 120 frame count unit 130 delay unit 140 sync signal determination unit 150 control unit 160 display unit

Front Page Continuation (72) Inventor Yoon Jong Sik Republic of Korea Kyung Ki Toe Choong Bun Ubu Amilisan 136-1 Hyun Dae Jong Ja Sang of Jusik Fesa

Claims (6)

[Claims] 1. A digital audio apparatus detects a 12-bit sync signal pattern in audio data input to the digital audio apparatus, and if all the logical values of the detected sync signal pattern are "1". , A sync signal detecting section (80) for outputting an active signal
A data load unit (90) for loading one count data among the synchronous count data stored with the number of audio data channels, sampling frequency, data transmission rate, etc. as information; and the data load unit (90). A synchronous count unit (100) that counts a clock of one frame of audio data when the count data loaded from the
And a synchronization signal detected by the synchronization signal detection unit (80) and a count completion signal output from the synchronization count unit (100) are ANDed to output a frame pulse signal. A sync signal detecting device for a digital audio device, comprising: 2. The data loading unit (90) comprises a load data storage unit (90A) for storing a fixed count load value, and a plurality of load values according to a number of channels, a sampling frequency and a data transfer rate. A control unit (90 that outputs a control signal for controlling one to be selected)
B) and a first selector (9) for selecting one of a plurality of inputs according to a control signal output from the control unit (90B).
0C) and the above-mentioned claim 1
A synchronizing signal detecting device for a digital audio device according to claim 1. 3. The synchronization counter (100) includes a first synchronization counter (100A) and a second synchronization counter (100A) for counting the load data selected by the first selector (90C) in synchronization with a clock signal. Synchronous counter (100
B), a second selector (100C) that selects the output of the second synchronization counter (100B) by a control signal of the control unit (90B), and an output of the second selector (100C). 3. The sync signal detecting apparatus for a digital audio apparatus according to claim 2, further comprising a count completion signal generator (100D) that outputs a count completion signal in synchronization with a clock signal. 4. A digital audio device, wherein a 12-bit sync signal pattern is detected in audio data input to the digital audio device,
If all the logical values of the detected sync signal pattern are "1", the sync signal detection unit (8
0), a data load unit (90) for loading one count data among the synchronous count data stored with the number of channels of the audio data, the sampling frequency, the data transmission rate, etc. as information, and the data load unit (90). 90), when the loaded count data is input, a synchronization count unit (100) that counts a clock of one frame of audio data, a synchronization signal detected by the synchronization signal detection unit (80), and the synchronization count. A logical operation unit (110) that performs a logical product operation of a count completion signal output from the unit (100) and outputs a frame pulse signal; and a frame counting unit (which performs frame counting for a predetermined time when a synchronization signal is erroneously detected ( 120) and a signal output from the synchronization counting unit (100) with a delay of a predetermined time. Delay unit for providing system clock (130)
A sync signal discriminating section (140) for discriminating whether or not the detected sync signal is normal, and a sync counter section (100) for discriminating a normal sync signal from the sync signal discriminating section (140). When the frame count unit (120) is enabled and the count is completed from the frame count unit (120), the operation of the synchronous count unit (100) is prohibited and the load data is input from the data load unit (90). After that, the control unit (150) for operating the synchronization counting unit (100) again.
A sync signal detecting device for a digital audio device, comprising: 5. The synchronization signal detecting device detects a frame pulse period using the output frame pulse and delay signal, and when the frame pulse is normally output,
Turn on the light emitting element "LED" to display that the sync signal is normally detected, and if the sync signal is not detected normally, turn off the light emitting element "LED" and the system operates normally. 5. The sync signal detecting apparatus as claimed in claim 4, further comprising a display unit (160) indicating that the digital audio apparatus is not operating. 6. The logical operation unit (110) performs a logical product operation of a synchronization detection signal of the synchronization signal detection unit (80) and a count completion signal of the synchronization count unit (100) to obtain a calculated logical value. Is "1", the sync signal is normally detected and the value is output to the sync signal discriminating unit (140). If the logic value is "0", the value is set to the frame count. A first arithmetic unit (110A) that outputs to the unit (120), a signal output from the first arithmetic unit (110A), and a synchronization detection completion signal output from the synchronization signal determination unit (140). Second comparison and logical product operation
5. The synchronizing signal detecting device for a digital audio device according to claim 4, wherein the synchronizing signal detecting device is constituted by an arithmetic unit (110B).