JPH11331115A - Data pulse generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of a data pulse which shows the position of data in a signal stream superimposed on a time division multiplexed received digital signal at a prescribed bit interval. SOLUTION: The data pulse generator is provided with a bit extracting circuit 10 for successively extracting the respective bits of a signal stream ERD from a received digital signal RD and generating a clock pulse CRVCK according to the timing of the extraction, synchronous coincidence detecting circuit 11 for detecting a fixed pattern from the extracted signal stream ERD and outputting a synchronizing pulse SP which shows the reference position of the data of the signal stream based on this pattern, counter 12 initialized by the synchronizing pulse SP for outputting a data pulse DTP through operation in accordance with the clock pulse, and synchronous holding circuit 13 for predicting the output timing of the synchronizing pulse SP according to the clock pulse and stopping the output of the synchronizing pulse to the counter 12, when the synchronizing pulse SP is outputted with the predicted timing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data pulse generator for generating a data pulse for extracting a signal sequence superimposed at a predetermined bit interval on a time-division multiplexed received digital signal.

[0002]

2. Description of the Related Art In a digital communication network, a voice signal for a maintenance telephone is superimposed on a time-division multiplexed digital signal at predetermined bit intervals and transmitted. For example,
PCM 24 channel multiplex frame (1 frame 193
), When a signal sequence for a maintenance telephone is superimposed, a fixed pattern of 8 bits is added for every 8 bits of data, and one bit of the signal sequence is changed to an MD (Modified Dipulse) code every 12 bits of a multiplex frame. To insert using a coding rule violation (CRV: Code Rule Violation). Prior to separation of the multiplex frame, the receiving side detects a code rule violation in the multiplex frame and extracts the data sequence.

FIG. 4 shows a conventional data pulse generator provided on an interface board disposed between a digital signal transmission line and a maintenance telephone (that is, an order wire board). The data pulse generator extracts the maintenance telephone voice signal from the multiplex frame,
A pulse signal (hereinafter, referred to as a data pulse) indicating the position of the audio data is generated from the signal train. In the figure, C
The RV extraction circuit 30 receives the received digital signal RD from the transmission path.
, And sequentially detects bits that violate the coding rule, thereby extracting a signal sequence ERD for a maintenance telephone including the fixed pattern and data. Each bit of the signal sequence ERD to be extracted is superimposed on the digital signal RD at 12-bit intervals.
VCK is generated.

[0004] The synchronization coincidence detection circuit 31 outputs a clock pulse.
The logic of each bit of the extracted signal sequence ERD is determined based on CRVCK, and is compared with a predetermined fixed pattern bit sequence. Then, when the same bit sequence as the bit sequence of the fixed pattern is detected in the signal sequence ERD, a synchronization pulse SP is output. The counter 32 operates according to the clock pulse CRVCK and outputs a data pulse DTP indicating the position of data in the signal train ERD. The counter 32 is initialized by a synchronization pulse SP from the synchronization coincidence detection circuit 31, and counts 8 after receiving the pulse, that is, 8 data bits.
The data pulse DTP is output according to the bit. The signal train ERD is sent to the order wire board together with the data pulse DTP and the clock pulse CRVCK generated by the data pulse generator. In the order wire board, the signal train ERD is based on the data pulse DTP and the clock pulse CRVCK.
, A bit sequence of audio data is extracted and reproduced as audio.

[0005]

However, in the conventional data pulse generation device, when the bit sequence constituting the audio data in the signal sequence ERD is the same as the bit sequence of the fixed pattern, the data pulse DTP is correctly generated. There is a problem that is not done. That is, when the bit string of the audio data is the same as the bit string of the fixed pattern, the synchronization coincidence detection circuit 31 outputs the synchronization pulse SP at an incorrect position, and the initialization position of the counter 32 is shifted. For this reason, the output timing of the data pulse DTP is shifted, and audio data cannot be correctly extracted from the signal train ERD, which causes noise.

Accordingly, an object of the present invention is to provide a data pulse generation device capable of correctly outputting a data pulse even when a bit sequence constituting data in a signal sequence ERD matches a fixed pattern bit sequence. It is in.

[0007]

According to the present invention, a signal sequence consisting of a fixed pattern and data superimposed at a predetermined bit interval is extracted from a time-division multiplexed received digital signal, and a data sequence in the signal sequence is extracted. The present invention relates to a data pulse generation device that generates a data pulse indicating a position. The data pulse generation device of the present invention sequentially extracts each bit of the signal sequence from the received digital signal, and generates a clock pulse in accordance with the timing of the extraction, and a bit extraction unit configured to generate the fixed pulse from the extracted signal sequence. Synchronous coincidence detecting means for detecting a pattern and outputting a synchronous pulse indicating a reference position of the data of the signal sequence based on the pattern;
A counter which is initialized with the synchronization pulse and operates in accordance with the clock pulse to output the data pulse;
A synchronous holding unit configured to predict an output timing of the synchronization pulse according to the clock pulse, and to stop outputting the synchronization pulse to the counter when the synchronization pulse is output at the predicted timing. I have.

In this case, the synchronization holding means predicts an output timing of the synchronization pulse according to the clock pulse, and outputs a different signal depending on whether or not the synchronization pulse is output at the predicted timing. A logic circuit located between the synchronization coincidence detecting means and the counter, and passing or not passing a synchronization pulse from the synchronization coincidence detecting means to the counter in accordance with an output from the synchronization determining means. Can be configured.

Further, the present invention is suitable for use in a case where a signal sequence including the fixed pattern and data is superimposed on the received digital signal using a coding rule violation.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on one embodiment shown in the drawings. In the present embodiment, C
PCM24 encoded with MI (Coded Mark Inversion)
Channel multi-frame digital signal (1 frame 19
3 bits), fixed pattern 8 at the beginning of data 8 bits
The present invention will be described according to an example in which a signal sequence for a maintenance phone having bits inserted therein is superimposed due to a coding rule violation. Each bit of the maintenance phone signal sequence is represented by giving a code rule violation to every 12 bits of the multiplexed digital signal. That is, in the CMI coding rule, every time the signal “1” is generated, “00” and “11” are generated alternately, and the signal “0” is generated.
In this case, since “01” is generated, a signal that violates this rule is represented by a signal of every 12 bits (for example, when the signal “1” is continuous, “00” is continuously provided, and the signal “ By giving "10" in the case of "0"), each bit of the signal sequence for the maintenance telephone is expressed.

FIG. 1 is a block diagram showing a data pulse generator according to one embodiment of the present invention. The data pulse generation device according to the present embodiment is provided in an interface board arranged between a digital signal transmission path and an order wire board (OW board), similarly to the related art. As shown in the figure, the data pulse generating device according to the present invention has
And a CRV extraction circuit 10, a synchronization coincidence detection circuit 11 and a counter 12 as in the conventional example shown in FIG.
A synchronization holding circuit 13 including a synchronization determination circuit 14 and an AND circuit 15 is provided.

When the data pulse DTP from the counter 12 is synchronized, the synchronization holding circuit 13 maintains the state regardless of the output timing of the synchronization pulse SP. That is, the synchronization determination circuit 14 predicts the output timing of the synchronization pulse SP from the synchronization coincidence detection circuit 11 in accordance with the clock pulse CRVCK generated by the CRV extraction circuit 10, and when the output timing matches the predicted timing. Sets the output OWREC to "Low". If the output timing does not match the predicted timing, OWREC is set to “High”. In the embodiment, the OWREC is switched when the synchronization pulse SP and the predicted timing occur three consecutive times in order to provide redundancy.

The AND circuit 15 is provided with an OWREC and a synchronization pulse SP.
And the synchronization pulse SP is passed to the counter 12 only when the OWREC is in the “High” state, that is, when the output timing does not match the predicted timing (hereinafter, referred to as “the output timing”).
The synchronization pulse that has passed through the AND circuit is called a load pulse LP). In this case, the counter 12 is initialized by the load pulse LP, counts eight consecutive bits as data bits, and outputs a data pulse DTP during that time. On the other hand, when OWREC is “Low”, that is, when the output timing matches the predicted timing, the AND circuit 15 stops the output of the synchronization pulse SP to the counter 12 (that is, the load pulse LP is not output). ). In this case, the counter 12 outputs the clock pulse CR
Continue to rotate according to VCK, data pulse DTP at 8 bit interval
Is output.

FIG. 2 is a flowchart of the operation of the data pulse generating apparatus according to the present embodiment, and FIG. 3 is a timing chart of each output signal. Less than,
The operation of the data pulse generation device will be described with reference to these drawings. The signal line ERD for the maintenance telephone superimposed on the received multiplexed digital signal RD is extracted by the CRV extraction circuit 10. Since each bit of the signal sequence ERD is superimposed due to a coding rule violation every 12 bits of the received signal RD, the CRV extraction circuit 10 extracts the signal sequence ERD by detecting the coding rule violation bit, Further, a clock pulse CRVCK is generated at the timing of the extraction (201). An 8-bit fixed pattern (“00111111” in FIG. 3) is inserted into the extracted signal sequence ERD at data intervals of 8 bits, and the synchronization match detection circuit 11 sequentially converts each bit of the signal sequence ERD. When the same code sequence as the fixed pattern is detected in the signal sequence ERD, a synchronization pulse SP is output (202). Therefore,
The synchronization coincidence detection circuit 11 outputs a synchronization pulse SP at the end of each fixed pattern, that is, at a 16-bit interval of the signal sequence ERD.

On the other hand, the synchronization determination circuit 14 is driven based on the clock pulse CRVCK generated by the CRV extraction circuit 10, predicts the output timing of the synchronization pulse SP, and outputs the synchronization pulse SP at the predicted timing. Is determined (203). If the fixed pattern is correctly detected, the synchronization pulse SP is output at 16-bit intervals as described above, so that it is possible to determine whether the synchronization pulse SP is output correctly. The synchronization determination circuit 14 receives the synchronization pulse SP, and establishes synchronization (OWREC) when the pulse SP is output at three or more consecutive predicted times.
("Low" signal is output), and if the pulse SP is not output three or more times at the predicted timing, synchronization is not established ("High" signal is output as OWREC) (206). In the OWREC signal of FIG. 3,
It shows a transition from a state where synchronization is not established to a state where synchronization is established.

Depending on the state of the OWREC signal, the AND circuit 15 passes or does not pass the synchronization pulse SP to the counter 12. In step 206, the OWREC signal is “High”
When the synchronization pulse SP is output when the synchronization pulse SP is output, that is, when the synchronization is not established, the AND circuit 15 passes the output to the counter 12 (output of the load pulse LP). Then, upon receiving the load pulse LP, the counter 12 is initialized (207). The counter 12 recognizes the next bit after the bit that has received the load pulse LP as the first bit of the data, and outputs the data pulse DTP while counting the data bit length (8 bits) (209).

On the other hand, in step 206, the OWREC signal is "Low".
When the synchronization pulse SP is output (for example, the synchronization pulse 30 in FIG. 3) when the synchronization is established, the AND circuit 15 does not allow the synchronization pulse SP to pass. As a result, the counter 12 continues to rotate without being affected by the synchronization pulse SP (20
8). That is, the counter 12 counts at the previously initialized timing, and repeats the output of the data pulse DTP at 8-bit intervals (209). That is, as a result of the data code arrangement matching the fixed pattern, the synchronization pulse
If the SP is output at an incorrect timing, the synchronization pulse SP is ignored.

The embodiment of the present invention has been described with reference to the drawings. However, it is apparent that the present invention is not limited to the matters described in the above embodiments, and that changes, improvements, and the like can be made based on the description in the claims. In the above-described embodiment, the AND circuit 15 is used to pass or not pass the synchronization pulse SP to the counter 12. However, other logic circuits, for example, an OR circuit, An XOR circuit, a flip-flop circuit, or the like may be used. Also, the signal sequence to be superimposed on the multiplexed digital signal is not limited to the above-mentioned voice data for the maintenance telephone, and various information can be digitized and superimposed, and the superimposition method is also limited to the one using the coding rule violation. Not done.

[0019]

As described above, according to the present invention, a data pulse can be correctly output even when a bit sequence constituting data in a signal sequence matches a bit sequence of a fixed pattern. As a result, only data can be accurately extracted from the signal sequence.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a data pulse generation device according to an embodiment of the present invention.

FIG. 2 is a flowchart of an operation in the data pulse generation device of FIG. 1;

FIG. 3 is a timing chart of each output signal in the data pulse generation device of FIG. 1;

FIG. 4 is a block diagram showing a conventional data pulse generation device.

[Explanation of symbols]

 10 CRV extraction circuit 11 Synchronization coincidence detection circuit 12 Counter 13 Synchronization holding circuit 14 Synchronization judgment circuit 15 AND circuit RD reception digital signal ERD signal train CRVCK clock pulse SP synchronization pulse OWREC synchronization judgment circuit output LP load pulse DTP data pulse

Claims (3)

[Claims] 1. A signal sequence including a fixed pattern and data superimposed at a predetermined bit interval is extracted from a time-division multiplexed received digital signal, and a data pulse indicating a position of data in the signal sequence is generated. In the data pulse generation device, bit extraction means for sequentially extracting each bit of the signal sequence from the received digital signal and generating a clock pulse in accordance with the extraction timing, and detecting the fixed pattern from the extracted signal sequence And
A synchronization coincidence detecting unit that outputs a synchronization pulse indicating a reference position of the data of the signal train based on the signal; a counter that is initialized with the synchronization pulse and operates according to the clock pulse to output the data pulse; Data pulse generation means for predicting an output timing of the synchronization pulse according to a clock pulse, and synchronizing holding means for stopping output of the synchronization pulse to the counter when the synchronization pulse is output at the predicted timing. apparatus. 2. The synchronization holding unit predicts an output timing of the synchronization pulse according to the clock pulse, and outputs a different signal depending on whether or not the synchronization pulse is output at the predicted timing. Located between the synchronization coincidence detecting means and the counter,
2. The data pulse according to claim 1, further comprising: a logic circuit that passes or does not pass a synchronization pulse from the synchronization coincidence detection unit to the counter according to an output from the synchronization determination unit. Generator. 3. The data pulse generation device according to claim 1, wherein the signal sequence including the fixed pattern and the data is superimposed on the received digital signal using a coding rule violation.