JPH04185186A - Decoding circuit for image data - Google Patents

Abstract

PURPOSE:To save a frame buffer memory by permitting the reading out of the image data accumulated in a receiving buffer memory in synchronization with a frame synchronizing signal and decoding the image data read out of the receiving buffer memory. CONSTITUTION:A receiving buffer memory administration circuit 13 which permits the reading out of the image data accumulated in the receiving buffer memory 11 in synchronization with the frame synchronizing signal and a variable length coding/decoding circuit 15 which decodes the image data read out of the receiving buffer memory 11 are provided. The image data is read out in synchronization with the frame synchronizing signal when the image data for 2 1 frame components is accumulated in the receiving buffer memory 11 A and thin read-out image data in decoded. The image data Dv is read out by taking frame synchronization with the ensuing stage and is decoded in a decoding circuit 15. The need for a frame buffer memory is thus eliminated.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a decoding circuit for variable length encoded image data.

[Summary of the invention]

The present invention uses a decoding circuit for variable-length encoded image data to detect whether there is one frame or more of image data stored in a reception buffer memory, and if there is one frame or more, the image data is By synchronizing frames and reading and decoding at the same time, the frame buffer memory can be omitted.

[Conventional technology]

For example, in the video conference system of CCITT Recommendation JT-H320, the terminal equipment is configured as shown in FIG. That is, 100 indicates the terminal device, 111 the video output device, 112 the video codec, 121
122 is an audio input/output device, 122 is an audio codec, 123 is a delay circuit, and 131 is a telematic device, which are connected to a network interface section 142 through a multiplexer/demultiplexer 141. Further, 151 is a system control section, 152 is an end/end signal control section, and 153 is an end/network signal control section, and each section is controlled by these. Furthermore, the network interface section 142 is connected to an external network 20.
0, and the network 200 also has an MCU (
A multipoint control unit) 300 is connected. In this case, the video codec 112 has recommendation J.
Since T-H261 is applied and variable coding (VLC) is used as the image data encoding method, the data length of each frame of image data is not constant. That is, in FIG. 2A, Dv indicates the image data of each frame, which is encoded using a predetermined encoding method, and the data length is different depending on the content of the image. Also, a code called PSC is added to the beginning of these image data Dv, and this PS
C allows the beginning of each frame to be detected or identified. Therefore, in the video codec 112, a decoding circuit for decoding the received image data Dv is configured as shown in FIG. 4, for example. That is, the received image data Dv is temporarily stored in the reception buffer memory 41 according to the reception clock RXCK, and is sequentially read out. Then, this read image data Dv is supplied to the variable length code decoding circuit 42 and also supplied to the PSC detection circuit 42 to detect the PSC, and when this PSC is detected,
Based on the detection output, decoding of the decoding circuit 42 is permitted, and the image data Dv is decoded into the original fixed length image data. In this case, the received image data DV has different data lengths as described above, and therefore the time required to decode one frame of image data also varies. ) or later, frame synchronization is not achieved. Therefore, the decoded image data is sequentially written into the frame buffer memory 44, and the written image data is sequentially read out in synchronization with the frame synchronization pulse from the next stage and supplied to the next stage. Then, in the subsequent stages, necessary processing is performed on the image data read out from the memory 44, and
The image is supplied through the frame memory to a CRT display for display.

[Problem to be solved by the invention]

However, the above-described decoding circuit requires a frame buffer memory 44 in order to achieve frame synchronization with the next stage. The present invention attempts to omit this frame buffer memory 44.

[Means to solve the problem]

Therefore, in this invention, if the reference numerals of each part correspond to the embodiments described later, there is a reception buffer memory 11 that stores received variable-length encoded image data, and a reception buffer memory 11 that stores received variable-length encoded image data. a first detection circuit 12 that detects a frame of image data read from the reception buffer memory 11; a second detection circuit 14 that detects a frame of image data read from the reception buffer memory 11; and first and second detection circuits 12. 14 and a frame synchronization signal are supplied, and when image data for one frame or more is stored in the reception buffer memory 11, reading of the image data stored in the reception buffer memory 11 is controlled by the frame synchronization signal. A reception buffer frame management circuit 13 that permits permission in synchronization with the reception buffer memory 11 and a variable length code decoding circuit 15 that decodes image data read out from the reception buffer memory 11 are provided.

[Effect]

When image data for one frame or more is stored in the reception buffer memory 11, the image data is read out in synchronization with a frame synchronization signal, and the read image data is decoded.

【Example】

In FIG. 1, received image data pv is accumulated in the reception buffer memory 11 according to the reception clock RXCK, and is also supplied to the first PSC detection circuit 12, and as shown in FIG. The detection pulse pb is extracted for each PSC of the image data Dv, and this pulse Pb is supplied to the reception buffer frame management circuit 13. This management circuit 13 counts the pulses pb supplied thereto, and also operates a second PSC detection circuit 1 to be described later.
By counting the PSC detection pulses Pe from 4 to 4, the number of frames of image data Dv stored in the buffer memory 11 is managed. When the image data Dv for one frame or more is stored in the buffer memory 11, a frame synchronization pulse Pf is supplied from the next stage (not shown) to the management circuit 13, as shown in FIG. 2C. A read permission signal Pr is supplied from the management circuit 13 to the buffer memory 11 at the time of the frame synchronization pulse Pf. Therefore, as shown in the second diagram, reading of the image data Dv from the buffer memory 11 is started from the time of the frame synchronization pulse Pf. Then, this read image data Dv is supplied to the variable length code decoding circuit 15, and a signal for permitting the start of decoding is supplied from the management circuit 13 to the decoding circuit 15, and the read image data Dv is supplied to the variable length code decoding circuit 15. Dv is decoded into the original fixed length image data, and this decoded image data is supplied to the next stage. Also, at this time, the image data Dv read out from the buffer memory 11 is supplied to the second PSC detection circuit 14, and as shown in FIG.
For each PSC of v, its detection pulse Pe is taken out,
This pulse Pe is supplied to the management circuit 13. In this manner, the management circuit 13 manages the number of frames of the image data Dv stored in the buffer memory 11 by counting the pulses Pb and Pe. Note that when the decoded image data from the decoding circuit 15 is subjected to predetermined processing in the subsequent circuits, the frame memory converts the decoded image data into image data for display, and then the CR
The image is displayed on the T-display. Further, in the above description, the management circuit 13 can be configured by, for example, a counter that counts up the pulse pb and counts down the pulse Pe, and a logic circuit that takes the logic of the count output and the synchronization pulse Pf. Furthermore, when the received image data Dv is image data obtained by converting the original image data into blocks and then variable-length encoding, since the image data from the decoding circuit 15 has been formed into blocks, this is converted into the original image data. All you have to do is decode it to data.

【Effect of the invention】

In this way, according to the present invention, it is possible to decode the variable-length coded image data Dv. .14 is provided, and its detection output PbSPe is processed by the management circuit 13. When the image data Dv for one frame or more is stored in the buffer memory 11, the image data Dv can be synchronized with the next stage. Since the data is read out and decoded in the decoding circuit 15, the frame buffer memory 44 as shown in FIG. 4 is not required.

[Brief explanation of drawings]

FIG. 1 is a system diagram showing an example of this invention, FIG. 2 is a diagram showing the timing of the signals, and FIGS. 3 and 4 are system diagrams for explaining this invention. 11; Reception buffer memory 12: First PSC detection circuit 13; Reception buffer frame management circuit 14; Second PSC detection circuit 15; Variable length code decoding circuit Agent Patent attorney Tadashi Sato Miguchi s50 word giant seven each Concave Fig. 1 D Memory 116 η
i=i=]EP= timing °2 Fig. 2

Claims (1)

[Claims] A reception buffer memory that stores received variable-length encoded image data, a first detection circuit that detects a frame of the image data written to the reception buffer memory, and the reception buffer A second detection circuit detects a frame of the image data read from the memory, and the detection outputs of the first and second detection circuits and a frame synchronization signal are supplied, and the image data is processed for one frame. a reception buffer frame management circuit that allows reading of the image data stored in the reception buffer memory in synchronization with the frame synchronization signal when the image data is stored in the reception buffer memory; An image data decoding circuit including a variable length code decoding circuit that decodes the read image data.