KR100245599B1 - Head detector in hdtv - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-definition television header detection device that outputs a variable length decode of video data by separating bit stream data in which a header and video data are mixed. The header detection device detects a header and then generates necessary video data. A data generator; It consists of an address generator that generates an address in accordance with the timing of the video data and writes it to the memory, and generates a read address when reading the memory so that the data required in the next stage can be read from the memory. Applicable in the case of a video phone being delivered.

Description

High Definition TV Header Detection Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-definition television header detection apparatus for separating bit stream data in which a header and video data are mixed and outputting video data to the next stage.

In general, video data of a high definition television (hereinafter referred to as HDTV) has a hierarchical structure as shown in FIG. 1, and is a unit of all input sequences starting from the top layer. A frame layer in which fields are combined; A Slice layer located at the far left of the frame and arranged to terminate at the far right of the frame; A macroblock layer serving as a unit of motion estimation composed of eight luminance blocks and two chroma blocks; It consists of four layers of the block layer, which is the smallest data processing unit composed of 8x8 pixels, and generates a bit when coding data generated through an encoder. In order to reduce the number of data, most of the data is subjected to Variable Length Coding (VLC), and a place for bit stuffing in preparation for under flow is provided. Let go.

The buffer delay informs the decoder side of the decoder decoder virtual buffer buffer fullness on the encoder side, so that the decoder buffer underflows or overflows. As a code for preventing the code, it has a 16-bit length, and S Quant has a quantization interval size in slice units calculated by Rate Control according to the degree of buffer fullness ( As a step size, all macroblocks in one slice are applied to one quant, and have a length of 5 bits.

The macro block address is a code indicating the position of a macroblock in one slice, variable length coded (VLC), and indicates a relative position with the previous macroblock encoded rather than the absolute position of the macroblock. Type (MB Type) is encoded by 8 macroblock types, variable length coded (VLC), motion vector (Motion Vector) is present only when indicated by the macroblock type (MB Type), within the same slice The coefficient is encoded by the difference between the current motion vector and the previous motion vector, and the block coefficient is variable length coded according to a zero run length, and the end of block is a block of coefficient data of one block. Attached to the end of the block to indicate the end of the block represented by two bits.

In the above input format, a frame layer is charged at the beginning of each frame, and includes a 32-bit Picture Start Code (hereinafter referred to as PSC) and a 16-bit Buffer Delay Code (Buffer Delay Code). BDC), which indicates when to start a Variable Length Decoder (VLD), the frame has 60 slices and each slice is aligned to 24 bits. .

A header detector receives serial data of the above format, checks a header of a frame layer, and distributes slice data to a variable length decoder (VLD) by 24 bits. As a result, the 32-bit picture start code (PSC) and the 16-bit buffer delay code (BDC) are examined in the serial data.

This buffer delay code (BDC) data is a buffer address which started the transmission of all the buffers in the encoder buffer, and is a code designed to prevent overflow or underflow from occurring in the variable length decoder (VLD). Since the decoder buffer has the same amount as the encoder buffer, the video data is sequentially stored in the buffer, and the data is read from the buffer from the point where the increased address is equal to the buffer delay code (BDC). Decoding is started by sending to a variable length decoder (VLD).

The slice start code (hereinafter referred to as SSC), the slice vertical position and the video data after the buffer delay code (BDC) are stored in the buffer in units of 24 bits, and 4 slice data are outputted. When the output of the video data is stopped by the slice stop signal (hereinafter referred to as SLSP), the video data is output again by the slice start signal (hereinafter referred to as SLST).

1 is an exemplary input format of a bit stream.

2 is a block diagram of a header detection apparatus for a high definition television of the present invention.

3 is a detailed configuration diagram of the data generator of FIG.

4 is a detailed block diagram of the address generator of FIG.

* Explanation of symbols for main parts of the drawings

10: data generator 20: address generator

11: Serial / parallel converter 12: Image start code checker

13: buffer delay code checker 14: data generator

21: recording counter 22: register

23: comparator 24: readout controller

25: read clock generator 26: read counter

27: multiplexer

As shown in FIG. 2, the header detecting apparatus of the high definition television according to the present invention is a header detecting apparatus for separating the bit stream data containing the header video data and outputting the video data to a variable length decoder. Detects the 32-bit image start code and the 16-bit buffer delay code, converts the serial input data into parallel data in synchronization with the falling edge of the input clock, and converts the converted parallel data into a 16-bit buffer delay code and 24-bit A data generator for outputting divided clock data and outputting one clock selection signal every 24 bits of video data output and one buffer delay code check signal for each 16-bit buffer delay code output. Wow; And a write address of the memory in synchronism with 24-bit data by the one-clock selection signal output from the data generator. It receives the buffer delay code check signal for latching the buffer delay code, receives the slice start signal for starting data reading and the slice stop signal for stopping data reading, and is required by the slice divider and variable length decoder (VLD). Outputs a read clock signal and a chip enable signal for enabling the memory chip, and generates a read address of the memory when the write address is the same as the buffer delay code (BDC) input from the data generator. And an address generator.

As illustrated in FIG. 3, the data generator 10 converts serial data input at 17.89M bps into 32-bit parallel data in synchronization with a falling edge of a clock. (11); An image start code checker 12 that checks the 32-bit data of the serial / parallel converter 11 and outputs a square wave control signal when it is an image start code (PSC); The image start code (PSC) is inputted from the image start code checker 12, and 16 bits which are continued are output as a buffer delay code (BDC). A buffer delay code checker (13) for outputting a square wave control signal (BCODE) of; The control signal of the image start code checker 12 and the control signal of the buffer delay code checker 13 are inputted to output data by 24 bits, and each time the 24-bit data is output, a selection signal SCON of 1 clock is output. It consists of the data generator 14 which outputs.

As shown in FIG. 4, the address generator 20 is initially set to 0000 as a 16-bit counter, and is counted at each rising edge of the control signal SCON of the data generator 14. A write counter 21 which generates a write address for every 24-bit data and writes it to a memory; When the buffer delay code (BDC) and buffer delay code check (BDCC) signals generated by the buffer delay code checker 13 are input, the clock is a rising edge, and the buffer delay code check (BDCC) signal is " high " A register 22 for latching a delay code BDC; A comparator (23) for comparing the write address of the write counter (21) with the buffer delay code (BDC) of the register (22) and outputting a read start (RDST) control signal when they become equal; A read controller 24 for reading data in the memory when the clock is a falling edge and the read start (RDST) signal or the slice start (SLST) signal is " high "; A read clock generator 25 which receives the read signal of the read controller 24 and outputs the read clock signal RCLK required by the slice divider and the variable length decoder and the chip enable signal CE2 for enabling the memory chip. Wow; A read counter 26 for counting the read address of the memory when the read clock signal RCLK generated by the read clock generator 25 rises; The multiplexer 27 receives the write address and read address and outputs the write address or read address by the selection signal SCON.

Referring to the operation of the present invention configured in this way in detail as follows.

The data generation unit 10 first checks the image start code (PSC) on the serial input through the image start code checker 12, and does not perform any operation after the power reset until the initial start code (PSC) is checked. Do not. The front end of the image start code checker 12 has a 32-bit serial / parallel converter 11, so that the bit serial data is input at 7.89 MHz, and the 1-bit data is received at the falling edge of the clock CLK. The data is outputted to the image start code checker 12 in sequence. The image start code checker 12 receives 32-bit data of 17.89 MHz and outputs a square wave control pulse when it is an image start code (PSC). The buffer delay code checker 13 receives the image start code (PSC), extracts 16 bits after the image start code (PSC), outputs it as a buffer delay code (BDC), and is the first buffer delay code (BDC). Only when one clock delay buffer control signal BDCC is outputted, the subsequent buffer delay code control signal BDCC continues to " low ". In the state, the control signal BCODE outputs a square wave of one clock each time the buffer delay code BDC appears. The buffer delay code control signal BDCC is input to the 16-bit register 22 of the address generator 20 to read the buffer delay code BDC and used when the buffer is read. The control signal BCODE is a data generator ( 14) and used to generate 24-bit data after the buffer delay code (BDC).

The data generator 14 receives the control signal PSC of the image start code checker 12 and the control signal BCODE of the buffer delay code checker 13 and outputs data by 24 bits. The clock CLK is lowered. The control signal BCODE at the edge is " high " After checking the acknowledgment, the slice data is output by 24 bits, and when the image start code control signal is encountered, the operation is stopped, and after the control signal is met, the 24-bit data is output again.

Here, when a 24-bit register is used to generate 24-bit data, 24 bits of the following 32-bit image start codes are output as slice data. Therefore, in order to eliminate this error, a shift register of 33 bits or more is used, and an address generator 20 is generated by generating a selection signal SCON of the first cycle every time data is output by 24 bits. ) Generates a write address signal in accordance with the signal and writes it to the buffer. The write counter 21 is a 16-bit counter that is initially set to 0000 and counts every rising edge of the selection signal SCON of the data generator 14 to generate a write address for every 24 bits of data. Will be recorded.

The register 22 receives the buffer delay code BDC and the buffer delay code control signal BDCC generated by the buffer delay code checker 13, and is set to 0000 first, and the clock CLK is a rising edge and the buffer delay code. The control signal BDCC is " high " In this case, the buffer delay code (BDC) data is latched.

At this time, the buffer delay code control signal BDCC is a signal that is turned on only once after power is applied. The comparator 23 compares the write address of the write counter 21 with the buffer delay code BDC of the register 22 and outputs the read start signal RDST when it becomes equal, and this signal RDST is applied after the power is applied. It is a signal that is turned ON only once, which means that it is time to read a memory. After this signal, four slice data are read out from the buffer and outputted, and the reading is stopped at the rising edge of the slice stop signal SLSP of the variable length decoder VLD.

When the clock CLK is at the falling edge and the read start control signal or the slice start signal SLST is " high ", the read control signal RD is " low " High ", the read control signal RD becomes " high " to " low " when the clock is a falling edge and the slice stop signal SLSP is " high ". While the read control signal RD is at " high ", data in the memory is read. The read clock generator 25 receives a read control signal RD of the read controller 24 to enable a read clock signal RCLK and a memory chip necessary for a slice divider and variable length decoding VLD. Outputs the enable signal CE2.

The read counter 26 is a 16-bit counter, which is initially set to 0000 and counts when the read clock RCLK is at the rising edge, and this 16-bit count number is the read address of the memory. The multiplexer 27 receives a write address and a read address and receives a selection signal SCON. When the selection signal SCON is " high ", the write address is output in the memory write cycle, and when the selection signal SCON is " low ", the read address is output in the memory read cycle. Therefore, the write address and the read address are selected by the multiplexer 27 to proceed with the write and read processing of the buffer.

As described in detail above, the present invention separates the header and the video data from the video data including the header input as a bit stream, and outputs the video data to a variable length decoder. There is a usable effect.

Claims (3)

A header detector for separating bit stream data containing header video data and outputting the video data to a variable-length decoder, wherein the input serial input data is received to detect a 32-bit image start code and a 16-bit buffer delay code. In synchronism with the falling edge of the clock, the serial input data is converted into parallel data. The converted parallel data is divided into 16-bit buffer delay codes and 24-bit video data, and each time the video data is output by 24 bits. A data generator which outputs a clock selection signal and outputs a buffer delay code check signal of one clock each time a 16-bit buffer delay code is output; And a write address of the memory in synchronization with the 24-bit data by the one-clock selection signal output from the data generator. It receives the buffer delay code check signal for latching the buffer delay code, receives the slice start signal for starting data reading and the slice stop signal for stopping data reading, and is required by the slice divider and the variable length decoder (VLD). Outputs a read clock signal and a chip enable signal for enabling the memory chip, and generates a read address of the memory when the write address is the same as the buffer delay code (BDC) input from the data generator. A high-definition television header detection device, comprising: an address generator. The apparatus of claim 1, wherein the data generator comprises: a serial / parallel converter for converting input serial data into 32-bit parallel data in synchronization with a falling edge of a clock; An image start code checker for checking the 32-bit data of the serial / parallel converter and outputting a square wave control signal when it is an image start code (PSC); It receives the image start code (PSC) from the image start code checker and outputs the 16 bits which are continued as a buffer delay code (BDC), and controls a square wave of 1 clock only in the case of the buffer delay code (BDC) first inputted after system reset. A buffer delay code checker for outputting a signal BCODE; It consists of a data generator which receives the control signal of the image start code checker and the control signal of the buffer delay code checker and outputs data by 24 bits, and outputs a selection signal (SCON) of one clock every 24 bits of data. Header detection apparatus for high-definition television, characterized in that. 2. The apparatus of claim 1, wherein the address generator comprises: a write counter counting every rising edge of the control signal SCON of the data generator to generate a write address for every 24-bit data and to write the write address to memory; When the buffer delay code (BDC) and buffer delay code check (BDCC) signals are input from the buffer delay code checker and the clock is rising edge, and the buffer delay code check (BDCC) signal is " high ", the buffer delay code ( A register for latching BDC); A comparator for comparing a write address of the write counter with a buffer delay code (BDC) of the register and outputting a read start (RDST) control signal when they become equal; A read controller for reading data in the memory when the clock is a falling edge and the read start (RDST) signal or the slice start (SLST) signal is " high "; A read clock generator for receiving a read signal of the read controller and outputting a read clock signal RCLK required by a slice divider and a variable length decoder and a chip enable signal CE2 for enabling a memory chip; A read counter for counting a memory read address when the read clock signal RCLK generated by the read clock generator is at the rising edge; And a multiplexer which receives a write address and a read address and outputs a write address or read address by a selection signal (SCON).