KR0171443B1 - Apparatus and method of variable length code decoding of digital video cassette recorder - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable length decoding apparatus of a digital video cassette recorder, and more particularly, to a technique of unifying and decoding a data path by parallel processing a variable length code into a plurality of bits.

2. The technical problem to be solved by the invention

If the decoding apparatus processes the video signal bit by bit, the system becomes complicated because the processing speed does not follow the input speed of the reproduction data, and a plurality of decoders having the same function must be made and processed in parallel, and then arranged in serial data again. It also solves the problem of bulky system.

3. Summary of Solution to Invention

After storing variable-length coded data in a unit of segment, storing the data in the segment unit, detecting the code length, determining the number of shift bits, and shifting the data, and outputting the shifted data. The valid data value is subtracted by the length corresponding to the output code, and the valid data is inspected to read and shift the combined data in the segment unit when the valid data is smaller than the set value, and shift the shifted data according to the codeword length. The codeword inputted by the window is compared with the variable length table to generate run and amp data.

4. Important uses of the invention

Used for decoding device of digital video cassette recorder.

Description

Variable length decoding apparatus and method of digital video cassette recorder

1 is a block diagram of a general variable length decoding apparatus.

2 is a block diagram of a variable length decoding apparatus according to the present invention.

3 is a memory map configuration diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

101: segment combination unit 102: frame memory

104: segment memory 106: data control unit

108: MR and VR residual data memory 110: data shift

112: run and amp data generator 114: variable length decoder

The present invention relates to a variable length decoding apparatus of a digital video cassette recorder, and more particularly, to a variable length decoding apparatus and method for unifying and decoding a data path by parallel processing a variable length code into a plurality of bits.

In general, a video cassette recorder (VCR) performs encoding and decoding to record and store image data.

FIG. 1 is a block diagram of a general decoding apparatus. The error detection and correction unit 10 for inputting a video signal detects an error and then corrects and outputs the error.

The error corrected data from the error detection and correction unit 10 is stored in the frame memory 12 by a controller (not shown). At this time, the segment combination unit 14 combines and outputs the data read from the frame memory 12 into segments, which are units for fixing the data amount during compression. The data combined from the segment combination unit 14 is stored in the segment memory 16 by a controller (not shown). The data read out from the segment memory 16 is converted into original quantization coefficients through the variable length decoder 18. Here, one segment is composed of a plurality of macro blocks smaller than this. One macro block is composed of four luminance signal blocks consisting of 8x8 pixels and two color difference signal blocks. The amount of data after the variable length encoding process is fixed in units of segments. When the amount of data after encoding is smaller than the allocated amount, dummy data is added, and when the amount of data exceeds the allocated number of bits, excess data is discarded. When segments are formed by extracting adjacent portions from a general image, the difference in the amount of information of each segment is large, resulting in an unbalanced image quality and consequently deteriorating image quality. In order to prevent this, the segments are extracted and configured to be close to a random form in various parts of the image.

The data past DCT are the DC and AC component coefficients of each block. Double variable-length coded AC coefficients are used. First find the run and amp of AC coefficients. run is the number of consecutive zeros, and amp is the first nonzero number of consecutive zeros. Once run and amp are found, they are coded according to the specified table. The coded data is 3 to 16 bits long, including sign bits.

The amount of data after encoding is determined for each of the luminance signal block and the color difference signal block. If the amount of data after encoding in one block exceeds this size, the excess data is stored in the MR memory existing for each macro block. As a result, the same macroblock is stored in bits in memory. After processing one macro block, the data in the MR memory is sequentially filled in the remaining areas. Even in this way, the data remaining without being stored is stored in the VR memory. After the above process is performed on the macroblock forming one segment, the unsaved VR memory data is filled in the empty space of the remaining macroblock, and the data that cannot be stored are discarded. Since data that cannot be stored corresponds to high frequency components in each block, the effect on the image is relatively small. When recording, the error correction internal code is added in units of units corresponding to one macroblock. The order in which the tapes are recorded is recorded differently in the segment ordering of the encoding process in order to reduce the effects of errors. Therefore, the playback side must first collect the data of the same segment that is scattered. The original segmented data is first decoded in units. One unit is composed of six blocks, and the variable length decoder 18 performs variable length decoding on each block. In order to variably decode the data read from the segment memory 16, the length of each code must be obtained. As described above, since each code has a length of 3 to 16 bits, first, the length of each code is obtained, and only the length thereof is decoded and the next code is decoded again. When all one block is decoded in one block of data, the remaining data from the next to the last data of the block are data from the MR or VR memory. If one block is not completely decoded with one block of data, MR or VR data is required. The variable length decoder 18 first obtains run and amp from the variable length code, and then uses this value to convert the original coefficients into original coefficients.

When MR data is generated in one macroblock, the remaining portion of the block that is not completely decoded is decoded using the MR data, and the data remaining after decoding among the data in the MR memory is stored in the VR memory. After the decoding process is performed on all the macroblocks, the remaining portions of the blocks that are not completely decoded are decoded using the data stored in the VR memory.

The data transformed from the variable length decoder 18 into original quantization coefficients is quantized by the quantization decoder 20 and decoded by converting the number of data bits. The data quantized and decoded by the quantization decoder 20 is output by performing an inverse DCT transform on the inverse DCT converter 22.

In the conventional decoding apparatus as described above, the data recorded in the MR / VR memory should be sequentially read as data in bit units having a non-uniform length, and for this purpose, a FIFO type memory storing in bit units is required. In the case of bit unit processing, the processing speed does not follow the input speed of the reproduction data. Therefore, it is necessary to make a plurality of decoders that perform the same function, process them in parallel, and arrange them in serial data again. There was a problem.

Accordingly, an object of the present invention is to provide a variable length decoding apparatus and method for solving the above problems.

It is another object of the present invention to provide a variable length decoding apparatus and method which can simplify the system and reduce the volume by introducing a concept of byte or word processing into a bit unit processing in a digital video cassette recorder, thereby simplifying the system by single path. Is in.

It is still another object of the present invention to provide a variable length decoding apparatus and method for performing decoding on a segment basis by changing codes of variable length into run and amp data in a digital video cassette recorder.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a variable length decoding apparatus according to the present invention,

3 is a memory map configuration diagram according to the present invention.

One preferred embodiment of the present invention will be described in detail with reference to FIGS.

The segment combination unit 301 is connected to the frame memory 102, and is discontinuous in the frame memory 102 with the same rules as when segmenting non-contiguous macroblocks on the screen for variable length coding in an encoder (not shown). The data stored in the segment are combined and stored in the segment memory 302. In this case, the data controller 106 reads data from the segment memory and stores the data in the data shift unit 110. The data shift unit 110 is not a general serial shift or a FIFO memory, but is configured to allow parallel load in the function of a barrel shift that can be shifted by an arbitrary length. The data control unit 106 detects the length of the code to determine how many bits of data should be shifted, and controls the shift according to the value. In the variable-length coding rule, one code length is a maximum of 16 bits including a sine bit. The data control unit 106 has a valid bit value stored in the data shifting unit 110, and subtracts the value corresponding to the code that is output every time the data is output by shifting. If the value is smaller than 16, data stored in the data shift 110 may not form a single complete code, and as a result, accurate decoding cannot be performed. The data control unit 106 reads the data stored in the segment memory 104 when the valid data bit in the data shift 110 is smaller than 16 bits, and fills the data shift 110 with the data. When filling this data, add as many bits as filled.

The data output from the data shift 110 is sent to the run and amp data generator 112. Data input to the data shift 110 is one code word and the length of the code word. The run and amp data generator 112 compares the input code word with a variable length code table by using a separate window according to the length of the code word, and obtains the corresponding run and amp data to the variable length decoder 114. send. The method of detecting the code length in the data control unit 106 is as follows. The coded data can be obtained by comparing the values of the first 8 bits (near the output terminals) of the data stored in the data shift 106, regardless of the length of the code word, as shown in Table 1 below. Here, not only the length of the code word but also the EOB End Of Block pattern indicating the end of the code corresponding to one block can be detected.

If a block termination pattern is detected before processing all the bits corresponding to one block, the remaining data that has not yet been processed among the data of the block (the data remaining in the data shift portion and the segment memory among the data corresponding to the block) The data not read in 104) is MR or VR data, and the data are stored in the MR VR residual data memory. The MR, VR residual data memory 108 should in principle store data in the form of a serial bitstream. In this case, however, a single processing path cannot follow the incoming data rate and the same functional blocks must be configured in parallel. In the present invention, the MR and VR residual data memory is processed using a general 8-bit or 16-bit memory, and the data is processed in units of bytes or more rather than units of bits. In addition, the data at the end of the block does not have a single code but can be decoded only when there is MR or VR data. This residual data is a maximum of 15 bits, with Naha present or not present in one block. A memory for storing this residual data is also required separately.

The MR, VR and residual data memory 108 is composed of a size memory as shown in FIG. 3 (a) and a size memory as shown in FIG. 3 (b) which stores how many bits of data are actually valid among the recorded data and the recorded data. do. One segment is composed of n blocks (n is a multiple of 6), and MR data that can occur in one block does not exceed 64 bytes. With this in mind, 64 × 8 bits or 32 × 16 bits of memory are allocated to one block. That is, the MR data is stored in the segment memory 104 corresponding to the block without storing the MR data in the order of occurrence.

When a block termination pattern is detected while processing a block like this, data remaining without being output from the data shift 110 is then broken into 8 bits or a multiple thereof and stored at the first address of a segment corresponding to the block, and valid among them. The number of data bits is written to the size memory of the same address. The size memory uses only 4 or 5 bits, so 3 to 4 bits remain. One bit is used as a flag indicating whether the last MR data of the block is present or if there are no more MR data. The data of the data shift 110 is stored in the MR memory, and then the data corresponding to the block but not yet read in the segment memory 104 are read and stored in the MR memory as shown in FIG. When one block is finished, the next block is processed.

After the processing of six blocks constituting a block with one bit is completed, the size and data of the residual data are read at the address allocated to the first block of the macro block, and only valid data is stored in the data shift 110. In addition, only the valid data bits are converted back into the data shift 110 by using the flags stored in the MR memory allocated to the first block and the size data stored in the sized memory such as the third (b). Send them and process them with the residual data. When the end pattern of the block is detected in the MR process, the next block is continued by combining the MR data with the residual data of the next block. In the MR process, a block requiring additional data may not be processed, and this data must go through a VR process. In the MR processing, the MR data remaining after the processing is completed for all blocks included in one macroblock, that is, even after a block end pattern is detected in all blocks is stored as VR data for decoding other macroblocks. Same as If the MR data remaining in the data shift 110 is 16 bits or less, the remaining MR data is stored in the place where the residual data was stored. If the MR data is longer than 16 bits, the first 16 bits are stored in the residual data memory, and the rest are the first of the block. The first MR data address. For data that has not been read from the MR memory yet, the first address of the unread MR data in the last MR memory of the block is recorded. Residual data and VR data remaining after MR data processing for all macroblocks are stored in the residual data memory and the existing MR memory.In order to process them, the address of the MR memory to be read first from the last MR memory of each block is processed. Read and perform VR processing from that address.

As described above, the present invention processes the variable length coded data into bytes or more parallel data rather than bytes in the form of a bit stream when converting the run-amp data into a byte stream, and processes MR, VR and residual data in bytes or more. By reducing the processing speed required for the system, it is possible to simplify the system and increase the stability of the system by processing in a single path instead of distributing the processing into multiple functional blocks.

Claims (3)

A variable length decoding apparatus of a digital video cassette recorder having a frame memory for storing a video signal in a frame unit and a segment memory for storing a video signal in a segment unit, the variable length decoding apparatus being connected to the frame memory and configured on the screen for variable length encoding. Segment combination unit for combining data stored in the frame memory discontinuously in the segment unit and storing them in the segment memory according to the same rules as when segmenting non-adjacent macroblocks into segments, and reading data from the segment memory. A data control unit for detecting the length of the code to determine how many bits the data should be shifted, and controlling the shift according to the value, a residual data memory for storing residual data and valid data under control of the data control unit, and Data The data shift constitutes a barrel shift function capable of shifting a signal output from a negative length to an arbitrary length, and a separate window is input according to the length of a code word of data shifted from the data shift. And a run and amp data generator for comparing the codeword with the variable length code table to obtain corresponding run and amp data. In a variable length decoding method of a digital video cassette recorder, a method of storing variable length coded data in a segment unit, storing the data in the segment unit, and detecting a code length to determine the number of shift bits. Performing a shift process, subtracting a valid data value by a length corresponding to an output code each time the shifted data is output, and combining the segment by the segment when the valid data is smaller than a set value. And a step of reading the shifted data and generating a run and amp data by comparing the inputted codeword with a variable length table by covering the shifted data with a window according to a codeword length. Decryption method. 3. The variable length decoding method of claim 2, wherein the code length detection detects the coded data by comparing the coded data with the shifted data value regardless of a codeword length.